Errata Sheet for Arria II GX Devices

Transcription

1 Errata Sheet or rria II GX evices ES Errata Sheet This errata sheet provides updated inormation about known device issues aecting rria II GX devices. Table 1 lists the speciic issues and which rria II GX devices are aected. Table 1. Issues or rria II GX evices (Part 1 o 2) Issue ected evices Planned Fix ECC False Error The error detection CC (SEU detection) eature may alsely assert the CC_EO signal when no SEU event has occurred. ll production devices PLL phasedone Signal Stuck at Low In some cases, the rria II GX phase-locked loop (PLL) blocks exhibit the phasedone signal stuck at low during the PLL dynamic phase shit. Transmitter PLL Lock (pll_locked) Status Signal The transmitter PLL lock status signal (pll_locked) does not de-assert when the pll_powerdown signal is asserted in conigurations that use the reerence clock pre-divider o 2, 4, or 8. ynamic econiguration Issue Between PCIe Mode and ny Other Transceiver Mode The transceiver may not be initialized correctly i your application uses dynamic reconiguration to change the transceiver channel between PCI Express (PCIe ) mode and any other transceiver mode. Quartus II Sotware Incorrect Setting or the Transceiver C in ll Modes Except PCIe Mode The Quartus II sotware incorrectly sets the C unit when the transceiver channel is conigured in any mode except PCIe mode and you conigure the C to automatic lock mode. External Memory Interace LL Frequency ange Update New MIN or the LL requency range and a new requency mode 6. Quartus II Mapping Issue with PCIe Interaces Using the Hard IP Block The Quartus II sotware incorrectly maps the PCIe interaces when using the hard IP block. ll production devices ll production devices ll rria II GX (ES and Production) evices ll rria II GX (ES and Production) evices ll rria II GX (ES and Production) devices ll rria II GX (ES and production) devices Quartus II sotware version 12.0 and later. No plan to ix silicon. For a sot-ix solution, reer to Transmitter PLL Lock (pll_locked) Status Signal. No plan to ix silicon. pply the reset workaround in ynamic econiguration Issue Between PCIe Mode and ny Other Transceiver Mode. Quartus II sotware version 10.1 and later. Patches are available or the Quartus II sotware versions 9.1SP2 and 10.0SP1. Sotware ix Sotware ix 101 Innovation rive San Jose, C ltera Corporation. ll rights reserved. LTE, I, CYCLONE, HCOPY, MX, MEGCOE, NIOS, QUTUS and STTIX words and logos are trademarks o ltera Corporation and registered in the U.S. Patent and Trademark Oice and in other countries. ll other words and logos identiied as trademarks or service marks are the property o their respective holders as described at ltera warrants perormance o its semiconductor products to current speciications in accordance with ltera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. ltera assumes no responsibility or liability arising out o the application or use o any inormation, product, or service described herein except as expressly agreed to in writing by ltera. ltera customers are advised to obtain the latest version o device speciications beore relying on any published inormation and beore placing orders or products or services. ISO 9001:2008 egistered pril 2013 ltera Corporation Subscribe

2 Page 2 ECC False Error Table 1. Issues or rria II GX evices (Part 2 o 2) XUI State Machine Failure Channel 0 Shited by One Cycle Channel 0 data is shited by one cycle with respect to Channels 1, 2, and 3. ECC False Error Issue ected evices Planned Fix High I/O Pin Leakage Current ll I/O pins have higher leakage than the published evice atasheet or rria II evices chapter, version 1.2 speciications. Error etection CC Feature When enabled, the Error etection CC eature may cause the MLB M blocks to operate incorrectly. M9 M Block Lock-Up The M9 M blocks may lock up due to a glitchy non-pll clock. utomatic Clock Switchover The automatic clock switchover eature may not operate correctly. emote System Upgrade The remote system upgrade eature ails when loading an invalid coniguration image. EP2GX125 ES EP2GX125 ES EP2GX125 ES EP2GX125 ES EP2GX125 ES ll rria II GX (ES and Production) evices The error detection cyclic redundancy check (CC) (single event upset [SEU] detection) eature may alsely assert the CC_EO signal when no SEU event has occurred. This happens because the coniguration M is incorrectly read or the ECC checks. In this scenario, the coniguration M data and the unctionality o the device are not aected. I ECC is not critical to your system, turn it o. I ECC is required, insert a sot IP in your design. Production devices Production devices EP2GX125 production devices EP2GX125 production devices None Sotware ix For more support and to request the sot IP, ile a service request using mysupport. PLL phasedone Signal Stuck at Low Solution In some cases, the rria II GX PLL blocks exhibit the phasedone signal stuck at low during the PLL dynamic phase shit. When the PLL phasedone signal is stuck at low, the intended phase shit does not happen. You can recover rom the PLL phasedone signal being stuck at low by resetting the PLL or by restarting the phase shit operation by asserting the phasestep signal. To resolve the PLL phasedone signal stuck at low issue, the ltera PLL megaunction is enhanced to automatically restart the phase shit operation internally in the ltera PLL megaunction whenever the PLL phasedone signal is stuck at low. estarting the phase shit operation compensates or the missing phase shit operation and also recovers the phasedone signal. pril 2013 ltera Corporation Errata Sheet or rria II GX evices

3 Transmitter PLL Lock (pll_locked) Status Signal Page 3 This ltera PLL megaunction solution will be implemented in the Quartus II sotware version 12.0 and later. ltera recommends upgrading to the latest Quartus II sotware, regenerating the PLL megaunction, and recompiling your design. dditionally, sotware patches are available or the Quartus II sotware versions 9.1 SP2 and 10.1 SP1 to upgrade the PLL megaunction with the solution. To download and install the Quartus II sotware patch, reer to the PLL Phasedone Stuck at Low Solution. I you need additional support, ile a service request using mysupport. Transmitter PLL Lock (pll_locked) Status Signal The transmitter phase-locked loop (PLL) lock status signal (pll_locked) does not de-assert when the pll_powerdown signal is asserted in conigurations that use the reerence clock pre-divider o 2, 4, or 8. Figure 1 shows the reerence clock pre-divider inside transmitter PLLs. This issue impacts the pll_locked status signal in the clock multiplier unit (CMU) PLL. Figure 1. eerence Clock Pre-ividers in Transmitter PLLs CMU PLL Lock etect pll_locked /M Input eerence Clock /1, /2, /4, /8 Charge Pump PF + Loop Filter VCO /L CMU0 High-Speed Clock eerence Clock Pre-ivider esigns that implement the recommended transceiver reset sequence described in the eset Control and Power own in rria II evices chapter in volume 2 o the rria II evice Handbook could potentially see a link ailure ater coming out o reset. Errata Sheet or rria II GX evices pril 2013 ltera Corporation

4 Page 4 Transmitter PLL Lock (pll_locked) Status Signal You can determine i the Transmitter PLL in your design uses a reerence clock pre-divider o 2, 4, or 8 by reerring to the Quartus II sotware Compilation eport. Figure 2 shows an example o the GXB Transmitter PLL report, which you ind in the esources Section under Fitter in the Compilation eport. I the value in the ivide By column reads 2, 4, or 8, your design is impacted by the pll_locked status signal issue. Figure 2. etermining eerence Clock Pre-ivider Value in the Compilation eport Workaround I the pll_locked issue impacts your design, instantiate and connect the pll_locked_sot_logic module, as shown in Figure 3. You must use the pll_locked_to_corelogic output rom this module in the transceiver reset logic and any user logic that relies on the transmitter PLL lock status signal. Figure 3. Instantiating and Connecting the pll_locked_sot_logic Module serdes_io top_cal_blk_clk cal_blk_clk pll_locked[0..0] top_pll_inclk xcvr_async_reset system_clk xcvr_reset_logic xcvr_async_reset clk pll_locked inst3 pll_powerdown tx_digitalreset pll_inclk pll_powerdown[0..0] tx_datain[39..0] tx_datain[39..0] tx_digitalreset[0..0] inst tx_clkout[0..0] tx_dataout[0..0] top_tx_dataout pll_locked_sot_logic clk pll_locked_to_corelogic reset pll_locked_rom_altgx inst2 Click pll_locked_sot_logic to obtain the module. pril 2013 ltera Corporation Errata Sheet or rria II GX evices

5 ynamic econiguration Issue Between PCIe Mode and ny Other Transceiver Mode Page 5 Use the calibration block clock (cal_blk_clk) or the pll_locked_sot_logic module. The cal_blk_clk requency speciication ranges rom 10 MHz to 125 MHz. epending on your cal_blk_clk requency, set the parameter p_delay_counter in the pll_locked_sot_logic so that the delay is equal to 100 s (worst-case transmitter PLL lock time). ynamic econiguration Issue Between PCIe Mode and ny Other Transceiver Mode I your application uses dynamic reconiguration to change the transceiver channel between PCIe mode and any other transceiver mode, the transceiver may not be initialized correctly, resulting in receiver bit errors. 1 This problem only aects dynamic reconiguration between PCIe mode and any other transceiver mode. ynamic reconiguration between any transceiver modes other than PCIe mode is not aected. Workaround I you see bit errors, apply the reset sequence described in the eset Sequence Solution. I you need additional support, ile a service request at ltera's mysupport. Quartus II Sotware Incorrect Setting or the Transceiver C in ll Modes Except PCIe Mode The Quartus II sotware versions up to and including 10.0 SP1 incorrectly set the clock and data recovery (C) unit when the transceiver channel is conigured in any mode except PCIe mode and the C is conigured in automatic lock mode. When there are no data transitions on the transceiver data inputs or an extended period o time (in the ms range), the C may keep the rx_reqlocked signal asserted. The C does not return to the lock-to-reerence state and incorrect data may be recovered. 1 The transceiver channels conigured in PCIe mode are NOT aected by this issue. Solution This issue is ixed in the Quartus II sotware versions 10.1 and later. ltera recommends upgrading to the latest Quartus II sotware and recompiling your design. For complete details o the solution, reer to the Transceiver C Solution. dditionally, sotware patches are available or the Quartus II sotware versions 9.1 SP2 and 10.0 SP1. To download and install the patch, reer to the Transceiver C Solution. Errata Sheet or rria II GX evices pril 2013 ltera Corporation

6 Page 6 External Memory Interace LL Frequency ange Update 1 I your transceiver channels are conigured to use rx_signaldetect with the C in automatic lock mode, you must apply the reset sequence described in the Transceiver C Solution. I you need additional support, ile a service request at ltera's mysupport. External Memory Interace LL Frequency ange Update Table 3. ecompilation Condition (1) Megaunction/ IP Core The rria II GX delay-locked loop (LL) range has been updated in the Quartus II sotware version 10.0 SP1 and later. Table 2 lists the updated LL requency ranges. Table 2. rria II GX LL Frequency ange Frequency Frequency ange (MHz) Mode C4 I3, C5, I5 C Table 3 lists the conditions and designs that are aected by these changes. esigns that all into these categories must be recompiled in the Quartus II sotware version 10.0 SP1 and later. For example, a 2 SM LTMEMPHY design with a memory clock running within the 150 MHz to 170 MHz requency range requires recompilation. ll designs using the LTLL megaunction require recompilation regardless o the requency and memory standard. Memory Standard 100 MHz to 120 MHz Memory Clock Frequency ange 150 MHz to 170 MHz 180 MHz to 201 MHz 220 MHz to 250 MHz 270 MHz to 300 MHz LTMEMPHY 2 SM No Yes Yes Yes Yes SM Yes Yes Yes No No UniPHY QII/II+ SM Yes Yes Yes Yes No LTLL ll Conditions Note to Table 3: (1) : Yes - ecompilation is needed pril 2013 ltera Corporation Errata Sheet or rria II GX evices

7 Quartus II Mapping Issue with PCIe Interaces Using the Hard IP Block Page 7 I any invalid LL coniguration critical warning appears ater recompilation in the Quartus II sotware version 10.0 SP1 and later, as shown in Example 1, you must regenerate the megaunction or the IP core and recompile the design. Example 1. Invalid LL Coniguration Critical Warning Critical Warning: LL atom ddr2_230:ddr2_230_inst ddr2_230_controller_phy:ddr2_230_controller_phy_inst ddr2_230_phy:ddr2_230_phy_inst ddr2_230_phy_alt_mem_phy:ddr2_230_phy_alt _mem_phy_inst ddr2_230_phy_alt_mem_phy_clk_reset:clk dll is using a clock period o 4.35 ns, which is outside the valid range or its coniguration mode. When the delay buer mode is LOW and the delay chain length is "8", the valid range is rom 4.55 ns to 5.88 ns. Quartus II Mapping Issue with PCIe Interaces Using the Hard IP Block The Quartus II sotware versions 9.1, 9.1 SP1, and 9.1 SP2 incorrectly allow logical channel 0 to be placed in any physical channel or x1 and x4 PCIe Gen1 interaces with the hard IP block. For correct operation with the hard IP block, logical channel 0 must be placed in physical channel 0. This issue is ixed in the Quartus II sotware version 10.0; however, ltera recommends upgrading to the Quartus II sotware version 10.0 SP1. I you have already designed or abricated your boards using the incorrect mapping, ile a service request using mysupport.altera.com to remedy this problem. High I/O Pin Leakage Current I/O pins on rria II ES devices have a higher leakage current than what is speciied in the rria II GX ata Sheet version 1.2. For rria II GX ES device I/O pin leakage current or all I/O pins, reer to Table 4. Table 4. I/O Pin Leakage Current or rria II GX ES evices Symbol escription Conditions Min Type Max Unit I I Input pin V I = 0V to V CCIOMX I OZ Tri-stated I/O Pin V O = 0V to V CCIOMX ll rria II GX production devices will have a lower leakage current. For production device speciications, reer to the evice atasheet or rria II GX evices chapter in volume 3 o the rria II GX evice Handbook. Errata Sheet or rria II GX evices pril 2013 ltera Corporation

8 Page 8 XUI State Machine Failure Channel 0 Shited by One Cycle XUI State Machine Failure Channel 0 Shited by One Cycle Figure 4. ate Matcher FIFO Skew Correct Channel lignment In XUI unctional mode, the data out o the channel 0 ate Match FIFO may be shited by one byte with respect to the data o the other three channels. This causes incorrect idle ordered set conversion, resulting in incorrect received parallel data. This issue happens only during initialization or receiver channel reset (assertion o rx_analogreset or rx_digitalreset). Figure 4 shows the channel skew. Master channel or XUI Protocol Purposes channel 0 channel 1 channel 2 channel 3 S T Skewed Channel 0 Master channel or XUI Protocol Purposes channel 0 channel 1 channel 2 channel 3 S T S = Start o packet T = End o packet = ata packet = lignment character = Lane Synchronization character = Clock ate Compensation character Workaround ltera provides a sot IP solution and associated documentation, available or download at: This sot IP should be integrated into the XUI receiver data path. This issue is ixed in production devices. Error etection CC Feature The Error etection CC eature is typically used to detect single event upsets (SEUs). When enabled, the Error etection CC eature may cause the memory logic array block (MLB) M to operate incorrectly in rria II GX ES devices. Only write operations in the MLB M blocks are aected. 1 The Error etection CC eature and CC error lag operate correctly. FPG coniguration bits are not aected by this issue. I you do not use Error etection CC, no action is required. The MLB M blocks will operate correctly. I you enable Error etection CC, disabling the Error etection CC resolves the problem. lso, using M9 M blocks or Logic Cells (LCs) instead o MLB M blocks resolves the problem. This issue will be ixed in production devices. pril 2013 ltera Corporation Errata Sheet or rria II GX evices

9 M9 M Block Lock-Up Page 9 M9 M Block Lock-Up Workarounds The M9 M blocks can lock up i the read clock glitches when rden=1, which can occur i the clock source is not rom a PLL. In this state, a M block no longer responds to read or write operations and requires an FPG reconiguration to restore operation. The issue occurs in the ead Timer Trigger circuitry, where a glitchy non-pll clock may inadvertently reeze the ead Timer Trigger circuitry, locking the M block in its last operation. ll M block modes are aected. MLBs are not aected. The workarounds or this issue are to add clock-enable logic, an internal PLL, or clock generation logic (or example, a clock divider). You can add clock-enable logic (internal or external) to disable the M block operation until the clock is stable. You can also gate the clock internally or externally. I your FPG resources permit, use an internal PLL or clock generation logic to ensure a stable clock source at the M block input. This issue will be ixed in production devices. utomatic Clock Switchover The automatic clock switchover eature may ail to operate correctly on rria II GX devices when the two clocks are running at dierent requencies. I both clocks are running at the same requency, there is no impact to your design. The ollowing modes are aected: utomatic utomatic with manual override You may observe two possible issues: Switchover rom inclk0 to inclk1, even though inclk0 is active (and vice-versa) clkbad[0,1] status signals may glitch, even i the input clocks are active 1 Manual clock switchover mode operates correctly and is not aected by this issue. There is no planned ix or this issue. emote System Upgrade The remote system upgrade eature does not operate correctly when you initiate a reconiguration cycle that goes rom a actory coniguration image to an invalid application coniguration image. In this scenario, the rria II GX device ails to revert back to the actory coniguration image ater a coniguration error is detected while loading the invalid application coniguration image. The ailure is indicated by a continuous toggling o the nsttus pin. In correct operation, the rria II GX device reverts back to the actory coniguration image ater a coniguration error is detected with the invalid coniguration image. Errata Sheet or rria II GX evices pril 2013 ltera Corporation

10 Page 10 ocument evision History 1 n invalid application coniguration image is classiied as one o the ollowing: partially programmed application image blank application image n application image assigned with a wrong start address The remote system upgrade eature works correctly with all other reconiguration trigger conditions. This issue is addressed by enabling the econig POF Checking eature in the updated LTEMOTE_UPTE megaunction and is available in the Quartus II sotware version 9.1 and later. For more inormation about how to enable the econig POF Checking eature, reer to N 603: ctive Serial emote System Upgrade eerence esign. ocument evision History Table 5. ocument evision History Table 5 lists the revision history or this errata sheet. ate Version Changes pril Updated the XUI State Machine Failure Channel 0 Shited by One Cycle section, per FogBugz # Minor text edits. pril dded the ECC False Error section. June dded the PLL phasedone Signal Stuck at Low section. September Updated the emote System Upgrade section. Minor text edits. February dded the Transmitter PLL Lock (pll_locked) Status Signal section. November dded the ynamic econiguration Issue Between PCIe Mode and ny Other Transceiver Mode and Quartus II Sotware Incorrect Setting or the Transceiver C in ll Modes Except PCIe Mode sections. Minor text edits. October dded the External Memory Interace LL Frequency ange Update section. September dded the Quartus II Mapping Issue with PCI Express (PCIe) Interaces Using the Hard IP Block section. pplied the new document template. ugust dded High I/O Pin Leakage Current and XUI State Machine Failure Channel 0 Shited by One Cycle sections. June Initial release. pril 2013 ltera Corporation Errata Sheet or rria II GX evices