VS8300 SOM Reference Manual

Transcription

1 VS8300 SOM Reference Manual VEST-VS8300-USG-001 Copyright 2016 Advanced Products Corporation Pte Ltd. All rights reserved. No part of this document may be photocopied, reproduced, or translated to another language without the prior written permission of Advanced Products Corporation Pte Ltd. Page 1 APC Proprietary Information June 2, 2017

2 TABLE OF CONTENTS 1 Overview General Information Feature Summary Block Diagram List of Acronyms Reference Documents Main Hardware Components NXP i.mx 6Solo/6DualLite/6Dual/6Quad/6DualPlus/6QuadPlus Overview Features /100/100Mbps Ethernet Transceiver Memory DDR3L SDRAM emmc Flash Memory NAND Flash Memory On-board I2C EEPROM PMIC On Board WLAN and Bluetooth Module Board Variant Configuration Settings External Interface Per Block/Instance Asynchronous Sample Rate Converter (ASRC) Digital Audio Mux (AudMux) Clock Controller Module (CCM) Display Content Integrity Checker (DCIC) Enhanced Configurable SPI (ECSPI) Enhanced Periodic Interrupt Timer (EPIT) Flexible Controller Area Network (FLEXCAN) General Purpose Input/Output (GPIO) General Purpose Timer (GPT) HDMI I2C Image Processing Unit (IPU) LVDS Display Bridge (LDB) MIPI- Camera Serial Interface Host Controller (MIPI_CSI) MIPI Display Serial Interface Host Controller (MIPI_DSI) PCI Express (PCIe) Pulse Width Modulation (PWM) Serial Advanced Technology Attachment PHY (SATA PHY) System JTAG Controller (SJC) Sony/Philips Digital Interface (SPDIF) Universal Asynchronous Receiver/Transmitter (UART) Universal Serial Bus Controller (USB) Ultra Secured Digital Host Controller (usdhc) Watchdog Timer (WDOG) Page 2 APC Proprietary Information June 2, 2017

3 4.25 Crystal Oscillator (XTALOSC) /100/1000-Mbps Ethernet (ENET) Electrical Specification Absolute Maximum Characteristics Operational Characteristics Power Supplies Power Consumption Layout Recommendations SOM Board Trace Length Trace Length of SO-DIMM s PCI Express Interface Recommendations LVDS Recommendations USB Recommendations MIPI CSI Recommendations MIPI DSI Recommendations SD Interface Recommendations CSI Parallel Recommendations I2S Recommendations SPI Interface Recommendations ENET Interface Recommendations HDMI Recommendations SATA Recommendations Environment Specification Temperature Specification Humidity Mechanical Specifications Module Dimension Height On Top Height on Bottom Mechanical Drawing Board Options Revision History Legal Notices Page 3 APC Proprietary Information June 2, 2017

4 LIST OF TABLES Table 1-1: LIST OF ACRONYMS... 9 Table 2-1: GPIO bits Settings Table 2-2: The BOARD VARIANT configuration settings Table 3-1: SO-DIMM Assignments Table 3-2: Resistors Loading Configurations for HDMI DDC vs. I2C Table 3-3: SOM Board Boot Source Settings Table 3-4: Resistors Loading Configurations for SATA vs. AUD Table 3-5: Resistors Loading Configurations for HDMI vs. MIPI DSI Table 4-1: External s of ASRC Table 4-2: External s of AUDMUX Table 4-3: External s of CCM Table 4-4: External s of DCIC Table 4-5: External s of ECSPI Table 4-6: External s of ECSPI Table 4-7: External s of ECSPI Table 4-8: External s of ECSPI Table 4-9: External s of ECSPI Table 4-10: External s of EPIT Table 4-11: External s of FLEXCAN Table 4-12: External s of GPiO Table 4-13: External s of GPIO Table 4-14: External s of GPIO Table 4-15: External s of GPIO Table 4-16: External s of GPIO Table 4-17: External s of GPIO Table 4-18: External s of GPI5_IO Table 4-19: External s of GPO6_IO Table 4-20: External s of GPT Table 4-21: External s of HDMI Table 4-22: External s of I2C Table 4-23: External s of I2C Table 4-24: External s of I2C Table 4-25: External s of I2C Table 4-26: External s of IPU Table 4-27: External s of LDB Table 4-28: External s of MIPI_CSI Table 4-29: External s of MIPI_DSI Table 4-30: External s of PCIe Table 4-31: External s of PWM Table 4-32: External s of SATA Table 4-33: External s of SJC Table 4-34: External s of SPDIF Table 4-35: External s of UART Table 4-36: External s of UART Table 4-37: External s of UART Table 4-38: External s of UART Table 4-39: External s of USB Table 4-40: External s of USDHC Page 4 APC Proprietary Information June 2, 2017

5 Table 4-41: External s of USDHC Table 4-42: External s of WDOG Table 4-43: External s of XTALSOC Table 4-44: External s of ENET Table 5-1: Absolute Maximum Characteristics Table 5-2: Power Suppliers Requirement Table 5-3: VS8300 SOM power consumption Table 6-1: Trace Length of SO-DIMM s Table 9-1: Board Options and Ordering Part Numbers Page 5 APC Proprietary Information June 2, 2017

6 LIST OF FIGURES/DIAGRAMS VEST-VS8300-USG-001, REV A Figure 1-1: VS8300 SOM Board Block Diagram... 8 Figure 8-1: Top View Figure 8-2: Bottom View Page 6 APC Proprietary Information June 2, 2017

7 1 OVERVIEW 1.1 GENERAL INFORMATION This document is the hardware reference manual for the VEST VS8300 SOM (System-On-Module) based on the NXP s i.mx6 ARM Cortex -A9 architecture processors. The SOM provides an ideal building block that easily integrates with a wide range of target markets requiring rich multimedia functionality, powerful graphics, and video capabilities, as well as high-processing, compact, cost effective and with low power consumption. The VS8300 SOM is tested to work in the following operating system environment: Android Embedded Linux 1.2 FEATURE SUMMARY NXP i.mx6 processors (Solo/DualLite/Dual/Quad/DualPlus/QuadPlus ARM Cortex-A9 Core, up to 1.0 GHz/Core) Up to 4GB of DDR3L SDRAM Up to 64GB of emmc or up to 8GB NAND Flash for boot/operating system/application/storage USB 2.0 OTG (up to 480Mbps), with integrated HS USB PHY USB 2.0 Host (480Mbps) Dual LVDS Serial Ports(one port up to 165Mpixels/sec or two ports up to 85Mpixels/sec) PCIe V2.0 SATA II,3.0Gbps HDMI 1.4 Port AC97/I2S/SSI, up to 1.4Mbps MMC/SD/SDIO(SD2 support SDR-104) I2C ecspi UART CAN PWM MIPI CSI(2 lanes for Solo/DualLite, 4 lanes for Dual/Quad/DualPlus/QuadPlus) MIPI DSI - 2 lanes at 1Gbps(shared the pinout with HDMI) Parallel CSI - 12bit GPIO Page 7 APC Proprietary Information June 2, 2017

8 On board 2Kb I2C EEPROM(AT24MAC402-MAHM-T) On board 10/100/1000 Mbps Ethernet PHY On board WLAN(IEEE a/b/g/n/ac) and Bluetooth 4.1 BR/EDR/LE(class 2) module JTAG Single 3.3V Input Power Supply Support boot from emmc or NAND Flash or SD2 (4-bit) 68mm x 42mm Form Factor 204 pin SO-DIMM Interface 1.3 BLOCK DIAGRAM Figure 1-1: VS8300 SOM Board Block Diagram 1.4 LIST OF ACRONYMS Acronyms ARM CAN CPU Abbreviations Advanced RISC Machine Controller Area Network Central Processing Unit Page 8 APC Proprietary Information June 2, 2017

9 Acronyms CSI DDR3L DSI ecspi emmc GB GPIO HDMI I2C IC JTAG LCD LVDS MB Mbps MHz MIPI MMC PWM PCIe RMII ROM SATA SD SDIO SDRAM SJC SOM SPI SSI UART USB USB OTG Acronym VEST APC ISO Abbreviations Camera Serial Interface Double Data Rate 3 Low Display Serial Interface Enhanced Configurable Serial Peripheral Interface Enhanced Multi Media Card Giga Byte General Purpose Input Output High-Definition Multi-media Interface Inter-Integrated Circuit Integrated Circuit Joint Test Action Group Liquid Crystal Display Low Differential Mega Byte Megabits per second Mega Hertz Mobile Industry Processor Interface Multi-Media Card Pulse Width Modulation Peripheral Component Interconnect Express Reduced Media Independent Interface Read-Only Memory Serial Advanced Technology Attachment Secure Digital Secure Digital Input Output Synchronous Dynamic Random Access Memory System JTAG Controller System On Module Serial Peripheral Interface Synchronous Serial Interface Universal Asynchronous Receiver/Transmitter Universal Serial Port Universal Serial Port on the Go Abbreviation Venture Embedded Solutions Technology Advanced Products Corporation Private Limited International Organization for Standardization Table 1-1: LIST OF ACRONYMS 1.5 REFERENCE DOCUMENTS i.mx 6Solo/6DualLite Automotive and Infotainment Applications Processors Technical Data (Document Number: IMX6SDLAEC) i.mx 6DualPlus/6QuadPlus Applications Processor Consumer Products (Document Number: IMX6DQPCEC) Page 9 APC Proprietary Information June 2, 2017

10 i.mx 6Solo/6DualLite Applications Processor Reference Manual (Document Number: IMX6SDLRM) i.mx 6DualPlus/6QuadPlus Application Processor Reference Manual(Document Number: IMX6DQPRM) Common Hardware Design for i.mx 6Dual/6Quad and i.mx 6Solo/6DualLite (Document Number: AN4397) Hardware Development Guide for i.mx6quadplus,6quad,6dualplus,6dual,6duallite,6solo Families of Application Processors (Document Number: IMX6DQ6SDLHDG.pdf) i.mx 6Dual/6Quad and i.mx 6DualPlus/6QuadPlus Applications Processor Comparison (Document Number: EB810) i.mx 6Solo/6DualLite Product Lifetime Usage Estimates (Document Number: AN4725) i.mx 6Dual/6Quad and 6DualPlus/6QuadPlus Family Product Lifetime Usage Estimates (Document Number: AN4724) Page 10 APC Proprietary Information June 2, 2017

11 2 MAIN HARDWARE COMPONENTS This section summarizes the main hardware building blocks of the SOM 2.1 NXP I.MX 6SOLO/6DUALLITE/6DUAL/6QUAD/6DUALPLUS/6QUADPLUS Overview The i.mx 6Solo/6DualLite/6Dual/6Quad/6DualPlus/6QuadPlus processors represent NXP Semiconductor s latest achievement in integrated multimedia-focused products. The processors feature NXP s advanced implementation of single/dual/quad ARMCortex-A9 core, which operates at speeds up to 1GHz. They include 2D and 3D graphics processors, 1080p video processing, and integrated power management. Each processor provides a 64bit (32bit for Solo) DDR3L memory interface and some other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, display, and camera sensors Features The i.mx 6Solo/6DualLite/6Dual/6Quad/6DualPlus/6QuadPlus processors are based on ARM Cortex- A9 MPCore Platform, which has the following features: ARM Cortex-A9 MPCore (up to 4 x CPU processors, with TrustZone) The core configuration is symmetric, where each core includes: - 32 KByte L1 Instruction Cache - 32 KByte L1 Data Cache - Private Timer and Watchdog - Cortex-A9 NEON MPE (Media Processing Engine) Co-processor The ARM Cortex-A9 MPCore complex includes: General Interrupt Controller with 128 interrupt support Global Timer Snoop Control Unit (SCU) The SoC-level memory system consists of the following additional components: Boot ROM, including HAB (96 KB) Internal multimedia / shared, fast access RAM (OCRAM, 128 KB) Secure/non-secure RAM (16 KB) External memory interfaces: The i.mx 6Solo/6DualLite/6Dual/6Quad/6DualPlus/6QuadPlus processors support latest, high volume, cost effective handheld DRAM, NOR, and NAND Flash memory standards. Up to 64 bit DDR3L bit NAND Flash Each i.mx 6Solo/6DualLite/6Dual/6Quad/6DualPlus/6QuadPlus processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously): Displays Page 11 APC Proprietary Information June 2, 2017

12 - Dual LVDS serial ports One port up to 165 Mpixels/sec or two ports up to 85Mpixels/sec (for example, WUXGA at 60 Hz) - HDMI 1.4 port - MIPI DSI, two lanes at 1Gbps Camera sensors: - One parallel Camera ports (up to 12 bit and up to 240MHz peak) - MIPI CSI-2 Serial port, supporting up to 1000Mbps/lane in 1/2/3-lane mode and up to 800Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to four data lanes(solo and DualLite processor only support two lanes). MMC/SD/SDIO cards USB: - One high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY PCI Express Port (PCIe) V2.0 one lane: - PCI Express (Gen2.0) dual mode complex, supporting Root complex operations and Endpoint operations. Use x1 PHY configuration. Miscellaneous IPs and interfaces: - Up to three I2S - Up to four UARTs, up to 5.0 Mbps each: Providing 4 wire(rts,cts,rxd,txd) RS232 interface Supporting 9-bit RS485 multidrop mode - Up to five ecspi (Enhanced CSPI) - Up to four I2C(I2C4 only support by Solo and DualLite processor), supporting 400 kbps - 10/100/1000Mbps Ethernet Controller - Up to four Pulse Width Modulators (PWM) - System JTAG Controller (SJC) - GPIO with interrupt capabilities - Two Controller Area Network (FlexCAN), 1 Mbps each - Two Watchdog timers (WDOG) - Two Clock Controller Module(CCM) The i.mx 6Solo/6DualLite/6Dual/6Quad/6DualPlus/6QuadPlus processors integrate advanced power management unit and controllers: Provide PMU, including LDO supplies, for on-chip resources Use Temperature Sensor for monitoring the die temperature Support DVFS techniques for low power modes Page 12 APC Proprietary Information June 2, 2017

13 Use SW State Retention and Power Gating for ARM and MPE Support various levels of system power modes Use flexible clock gating control scheme The i.mx 6Solo/6DualLite/6Dual/6Quad/6DualPlus/6QuadPlus processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers while having the CPU core relatively free for performing other tasks. The i.mx 6Solo/6DualLite/6Dual/6Quad/6DualPlus/6QuadPlus processors incorporate the following hardware accelerators: VPU - Video Processing Unit IPUv3H - Image Processing Unit version 3H GPU3Dv4-3D Graphics Processing Unit (OpenGL ES 2.0) version 4 for Dual and Quad GPU3Dv5-3D Graphics Processing Unit (OpenGL ES 2.0) version 5 for Solo and DualLite GPU3Dv6-3D Graphics Processing Unit (OpenGL ES 3.0) version 6 for DualPlus and QuadPlus GPU2Dv3-2D Graphics Processing Unit (BitBlt) version 3 ASRC - Asynchronous Sample Rate Converter Note: 1. Please refer the latest i.mx6 datasheet from NXP website for detail 2. The i.mx6 internal RTC of VS8300 SOM is using imx6 internal ring oscillator which is not accurate, and there isn t RTC backup battery on the SOM, so recommend customer use external RTC chip /100/100MBPS ETHERNET TRANSCEIVER The SOM features the Atheros AR8035 Gigabit Ethernet PHY. The AR8035 is Atheros s 4 th generation, single port, 10/100/1000 Mbps, Tri-speed Ethernet PHY. It supports RGMII interface to the MAC. The key new features supported by the device are: 10/100/1000 BASE-T IEEE compliant Supports 1000 BASE-T PCS and auto-negotiation with next page support Error-free operation up to 140 metres of CAT5 cable RGMII timing modes support internal delay and external delay on Rx path Supports IEEE802.3az (Energy Efficient Ethernet) Automatic channel swap (ACS) Automatic MDI/MDIX crossover Page 13 APC Proprietary Information June 2, 2017

14 2.3 MEMORY DDR3L SDRAM The SOM uses four DDR3L SDRAM ICs(Solo processor only support 2 DDR3L SDRAM) to support onboard SDRAM memory. These SDRAM operated at 1.35V voltage level. The SDRAM calibration resistor used on SOM is 240ohm 1% resistor. Please see Section titled Board Options for various memory options emmc Flash Memory The SOM has up to 64GB of emmc Flash memory installed. The emmc flash can be used for Flash Disk, O.S. run- time-image and the Boot-loader. emmc is directly connected to i.mx6 SDHC 4 and operating under 3.3V voltage level. The emmc Flash memory is physically located on the bottom side of the SOM. Please see Section titled Board Options for various emmc Flash options NAND Flash Memory The SOM can support up to 8GB NAND Flash for Flash Disk, O.S. run-time-image and the boot-loader The NANF Flash is shared NANDF_RE_B and NANDF_WE_B and PCB location with emmc, so they are not available simultaneously On-board I2C EEPROM The SOM features a 2Kb I2C EEPROM (AT24MAC402-MAHM-T) and this EEPROM is directly connect to I2C2 bus. 2.4 PMIC The SOM uses the NXP PMPF0100 as a Power Management Integrated Circuit (PMIC) solution. The PMPF0100 designed specifically for use with NXP s i.mx series of application processors. The PMPF0100 regulates all power rails required on SOM from a single 3.3 V power supply. The PMIC is fully programmable via the I2C interface and associated register map. Additional communication is provided by direct logic interfacing including interrupt, watchdog and reset. 2.5 ON BOARD WLAN AND BLUETOOTH MODULE The SOM can be configured with an SX-SDMAC-2831S wireless module from Silex technology. The SX- SDMAC-2831S features a 2.4GHz / 5GHz dual band IEEE a/b/g/n/ac WLAN and Bluetooth 4.1 BR/EDR/LE (class 2) chipset from Qualcomm Atheros. The module provides provision for two 50 ohm MHF connectors for external dual band antennas for antenna diversity. Please note that both the WiFi and Bluetooth functionality can be achieved with only the primary antenna connected to the module. Page 14 APC Proprietary Information June 2, 2017

15 2.6 BOARD VARIANT CONFIGURATION SETTINGS Nine GPIO bits are used for different board variant configuration settings for internal use only. These GPIO bits are either pull up or pull down by 10k resistor. These bits are: Name i.mx6 pad BOARD_CFG1 DISP0_DAT14 GPIO5_IO08 I 3.3V Board configuration 1 BOARD_CFG2 DISP0_DAT13 GPIO5_IO07 I 3.3V Board configuration 2 BOARD_CFG3 DISP0_DAT12 GPIO5_IO06 I 3.3V Board configuration 3 BOARD_CFG4 DISP0_DAT11 GPIO5_IO05 I 3.3V Board configuration 4 BOARD_CFG5 DISP0_DAT10 GPIO4_IO31 I 3.3V Board configuration 5 BOARD_CFG6 DISP0_DAT17 GPIO5_IO11 I 3.3V Board configuration 6 BOARD_CFG7 DISP0_DAT16 GPIO5_IO10 I 3.3V Board configuration 7 BOARD_CFG8 DISP0_DAT15 GPIO5_IO09 I 3.3V Board configuration 8 BOARD_CFG9 DISP0_DAT7 GPIO4_IO28 I 3.3V Board configuration 9 Table 2-1: GPIO bits Settings The BOARD VARIANT CONFIGURATION settings are: Board Configuration Bit BOARD_CFG9 BOARD_CFG8 BOARD_CFG[7:6] BOARD_CFG[5:1] Meaning 0 -> NAND Flash 1->eMMC 0-> 32-bit wide DDR3L interface 1-> 64 bit wide DDR3L interface Reserved (default:00) > Hynix 2Gb H5TC2G63FFR-PBA > Hynix 8Gb H5TC8G63AMR-PBA > PM Tech 4Gb PMF412816EBR-KADN > Samsung 2Gb K4B2G1646F-BYK > Samsung 4Gb K4B4G1646E-BYK > Samsung 8Gb K4B8G1646D-MYK0 Table 2-2: The BOARD VARIANT configuration settings Page 15 APC Proprietary Information June 2, 2017

16 3 EXTERNAL INTERFACE The VS8300 SOM employs a 204-pin SO-DIMM standard interface. The recommended mating connector for baseboard interfacing is Lotes AAA-DDR-109-K01 or equivalent. Note: The i.mx6 contains a limited number of pins, most of which have multiple signal options called Muxing. These signal to pin and pin to signal options are selected by the input-output multiplexer called IOMUX. Below assignments lists the pad s of the chip, the various signals that can be assigned to each of the pads, for more detail please refer the latest i.mx6 datasheet : : i.mx 6 pad : : : : : number on the connector on the connector Pad on i.mx6 on the pad type of this pin level of this pin Short pin functionality description 1 GND Ground 0V GND 2 GND Ground 0V GND 3 HDMI_TX_DDC _SDA EIM_D16 ECSPI1_SCLK HDMI_TX_DDC_S DA GPIO3_IO16 (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note 1. I2C4_SDA_GPIO ENET_TXD1 GPIO1_IO29 I2C4_SDA(for Solo and DualLite only) 3,3V Muxing (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note 1. 4 TXRXP_A From AR8035 pin TRXP0 5 HDMI_TX_DDC _SCL EIM_EB2 ECSPI1_SS0 HDMI_TX_DDC_S CL GPIO2_IO30 Differential Media-dependent interface 0, differential 100ohm transmission line (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note 1. Page 16 APC Proprietary Information June 2, 2017

17 I2C4_SCL_GPIO ENET_TX_EN GPIO1_IO28 I2C4_SCL(for Solo and DualLite only) (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note 1. 6 TXRXN_A From AR8035 pin TRXN0 7 AUD4_RXD DISP0_DAT23 ECSPI1_SS0 AUD4_RXD GPIO5_IO17 Differential 8 GND GND Ground 0V GND 9 AUD4_TXFS DISP0_DAT22 ECSPI1_MISO AUD4_TXFS GPIO5_IO16 10 TXRXP_B From AR8035 pin TRXP1 11 VOL_DN_GPIO DISP0_DAT18 ECSPI2_SS0 AUD5_TXFS AUD4_RXFS GPIO5_IO12 12 TXRXN_B From AR8035 pin TRXN1 13 VOL_UP_GPIO DISP0_DAT19 ECSPI2_SCLK AUD5_RXD AUD4_RXC GPIO5_IO13 Differential Differential Media-dependent interface 0, differential 100ohm transmission line 14 GND GND Ground 0V GND 15 AUD4_TXC DISP0_DAT20 ECSPI1_SCLK AUD4_TXC GPIO5_IO14 16 TXRXP_C From AR8035 pin TRXP2 17 AUD4_TXD DISP0_DAT21 ECSPI1_MOSI AUD4_TXD GPIO5_IO15 18 TXRXN_C From AR8035 pin TRXN2 Media-dependent interface 1, differential 100ohm transmission line Media-dependent interface 1, differential 100ohm transmission line 19 GND GND Ground 0V GND 20 GND GND Ground 0V GND 21 PWM2_OUT DISP0_DAT9 PWM2_OUT WDOG2_B GPIO4_IO30 22 TXRXP_D From AR8035 pin TRXP3 23 PWM1_OUT DISP0_DAT8 PWM1_OUT WDOG1_B GPIO4_IO29 Media-dependent interface 2, differential 100ohm transmission line Media-dependent interface 2, differential 100ohm transmission line Media-dependent interface 3, differential 100ohm transmission line Page 17 APC Proprietary Information June 2, 2017

18 24 TXRXN_D From AR8035 pin TRXN3 25 SPI3_SCLK DISP0_DAT0 ECSPI3_SCLK GPIO4_IO21 26 GND GND Ground 0V GND 27 SPI3_CS1 DISP0_DAT4 ECSPI3_SS1 GPIO4_IO25 28 RGMII_LED_AC From AR8035 T pin LED_ACT 29 SPI3_CS0 DISP0_DAT3 ECSPI3_SS0 GPIO4_IO24 30 RGMII_LED_10 From AR8035 _100_1000 pin LED_1000 and LED_10_ SPI3_MOSI DISP0_DAT1 ECSPI3_MOSI GPIO4_IO22 32 SPI3_CS3 DISP0_DAT6 ECSPI3_SS3 GPIO4_IO27 33 SPI3_MISO DISP0_DAT2 ECSPI3_MISO GPIO4_IO23 34 SPI3_CS2 DISP0_DAT5 ECSPI3_SS2 GPIO4_IO26 VEST-VS8300-USG-001, REV A Media-dependent interface 3, differential 100ohm transmission line Output 3.3V Parallel LED output for 10/100/1000 BASE-T activity; need pulled up during power on, active low. Output 3.3V Parallel LED output for 10/100/1000 BASE-T link; need pulled up during power on, active low. 35 GND GND Ground 0V GND 36 GND GND Ground 0V GND 37 UART1_CTS EIM_D19 ECSPI1_SS1 UART1_CTS_B GPIO3_IO19 EPIT1_OUT 38 SD2_CLK SD2_CLK SD2_CLK ECSPI5_SCLK AUD4_RXFS GPIO1_IO10 39 UART1_RTS EIM_D20 ECSPI4_SS0 UART1_RTS_B GPIO3_IO20 EPIT2_OUT 40 GND GND Ground 0V GND 41 UART1_TXD_C SD3_DAT7 GPO6_IO17 UART1_TX_DATA 42 SD2_CD_B GPIO_4 GPIO1_IO04 SD2_CD_B 43 UART1_RXD_C SD3_DAT6 GPI5_IO18 UART1_RX_DATA 44 SD2_DATA1 SD2_DAT1 SD2_DATA1 ECSPI5_SS0 AUD4_TXFS GPIO1_IO14 45 UART2_RTS EIM_D29 ECSPI4_SS0 GPIO3_IO29 UART2_RTS_B Output Input Page 18 APC Proprietary Information June 2, 2017

19 46 SD2_CMD SD2_CMD SD2_CMD ECSPI5_MOSI AUD4_RXC GPIO1_IO11 47 UART2_CTS EIM_D28 I2C1_SDA ECSPI4_MOSI UART2_CTS_B GPIO3_IO28 48 SD2_DATA2 SD2_DAT2 SD2_DATA2 ECSPI5_SS1 AUD4_TXD GPIO1_IO13 49 UART2_RXD EIM_D27 UART2_RX_DATA GPIO3_IO27 50 SD2_DATA3 SD2_DAT3 SD2_DATA3 ECSPI5_SS3 AUD4_TXC GPIO1_IO12 51 UART2_TXD EIM_D26 UART2_TX_DATA GPIO3_IO26 52 SD2_DATA0 SD2_DAT0 SD2_DATA0 ECSPI5_MISO AUD4_RXD GPIO1_IO15 DCIC2_OUT 53 GND GND Ground 0V GND 54 GND GND Ground 0V GND 55 USB_HOST_OC EIM_D30 IPU1_CSI0_DATA 03 GPIO3_IO30 USB_H1_OC 56 PWM4_OUT_S D1_CMD SD1_CMD SD1_CMD ECSPI5_MOSI PWM4_OUT GPT_COMPARE1 GPIO1_IO18 57 USBHUB_nRST EIM_D17 ECSPI1_MISO DCIC1_OUT GPIO3_IO17 I2C3_SCL 58 GPIO03_SD1_D ATA0 59 USB_HOST_PW R_EN 60 PWM3_OUT_S D1_DATA1 SD1_DAT0 GPIO_0 SD1_DAT1 SD1_DATA0 ECSPI5_MISO GPT_CAPTURE1 GPIO1_IO16 CCM_CLKO1 ASRC_EXT_CLK EPIT1_OUT GPIO1_IO00 USB_H1_PWR SD1_DATA1 ECSPI5_SS0 PWM3_OUT GPT_CAPTURE2 GPIO1_IO17 Page 19 APC Proprietary Information June 2, 2017

20 61 USB_HOST_VB US 62 GPIO04_SD1_D ATA2 VEST-VS8300-USG-001, REV A USB_H1_VBUS USB_H1_VBUS Power 4.5 to USB VBUS 5.25V SD1_DAT2 SD1_DATA2 ECSPI5_SS1 GPT_COMPARE2 PWM2_OUT WDOG1_B GPIO1_IO19 WDOG1_RESET_ B_DEB 63 GND GND Ground 0V GND 64 GPIO05_SD1_D ATA3 SD1_DAT3 SD1_DATA3 ECSPI5_SS2 GPT_COMPARE3 PWM1_OUT WDOG2_B GPIO1_IO21 WDOG2_RESET_ B_DEB 65 BOOT_SEL1 EIM_DA6 SRC_BOOT_CFG0 6 Input 3.3V Boot configuration signal 1 Note 2 66 GPIO01_SD1_C NANDF_CS3 GPIO6_IO16 3.3V GPIO D_B 67 BOOT_SEL0 EIM_DA5 SRC_BOOT_CFG0 5 Input 3.3V Boot configuration signal 0 Note 2 68 GND GND Ground 0V GND 69 CCM_CLKO2_G PIO 70 GPIO02_SD1_C LK NANDF_CS2 SD1_CLK CCM_CLKO2 GPIO6_IO15 SD1_CLK ECSPI5_SCLK XTALOSC_OSC32 K_32K_OUT GPT_CLKIN GPIO1_IO20 71 USB_OTG_OC EIM_D21 ECSPI4_SCLK USB_OTG_OC GPIO3_IO21 I2C1_SCL SPDIF_IN 72 GND GND Ground 0V GND 73 USB_OTG_VBU S 74 USB_OTG_PWR _EN USB_OTG_VBU S EIM_D22 75 USB_OTG_ID GPIO_1 WDOG2_B USB_OTG_ID PWM2_OUT GPIO1_IO01 SD1_CD_B USB_OTG_VBUS Power 4.5 to 5.25V USB VBUS ECSPI4_MISO USB_OTG_PWR GPIO3_IO22 SPDIF_OUT 76 CPUPWRON ONOFF SRC_ONOFF Input 3.0V Power on/off (100K pull up) 77 GND GND Ground 0V GND Page 20 APC Proprietary Information June 2, 2017

21 78 PMIC_REST PMIC pin PWRON - Input (68K pull up) VEST-VS8300-USG-001, REV A 3.0V Reset 79 USB_HOST_DN USB_H1_DN USB_H1_DN Differential 3.0V USB host data 80 SOM_3V3 Power Power 3.3V 3.3V power input Note 3 81 USB_HOST_DP USB_H1_DP USB_H1_DP Differential 3.0V USB host data 82 SOM_3V3 Power Power 3.3V 3.3V power input Note 3 83 GND GND Ground 0V GND 84 SOM_3V3 Power Power 3.3V 3.3V power input Note 3 85 USB_OTG_DP USB_OTG_DP USB_OTG_DP Differential 3.0V USB OTG data 86 SOM_3V3 Power Power 3.3V 3.3V power input Note 3 87 USB_OTG_DN USB_OTG_DN USB_OTG_DN Differential 3.0V USB OTG data 88 SOM_3V3 Power Power 3.3V 3.3V power input Note 3 89 GND GND Ground 0V GND 90 Power Power 3.3V 3.3V power input SOM_3V3 Note 3 91 SATA_RXP SATA_RXP SATA_PHY_RX_P Differential 2.5V SATA receive input differential (shared pinout with SATA, resistor configurable, default is SATA) Note 4 AUD3_TXC CSI0_DAT4 IPU1_CSI0_DATA 04 ECSPI1_SCLK AUD3_TXC GPIO5_IO22 1.8V Muxing (shared pinout with SATA, resistor configurable, default is SATA) Note 4 92 SOM_3V3 Power Power 3.3V 3.3V power input Note 3 93 SATA_RXN SATA_RXM SATA_PHY_RX_N Differential 2.5V SATA receive input differential (shared pinout with SATA, resistor configurable, default is SATA) Note 4 AUD3_RXD CSI0_DAT7 IPU1_CSI0_DATA 07 ECSPI1_SS0 AUD3_RXD GPIO5_IO25 1.8V Muxing (shared pinout with SATA, resistor configurable, default is SATA) Note 4 94 SOM_3V3 Power Power 3.3V 3.3V power input Note 3 95 GND GND Ground 0V GND 96 SOM_3V3 Power Power 3.3V 3.3V power input Note 3 Page 21 APC Proprietary Information June 2, 2017

22 97 SATA_TXP SATA_TXP SATA_PHY_TX_P Differential 2.5V SATA transmit output differential (shared pinout with SATA, resistor configurable, default is SATA) Note 4 AUD3_TXD CSI0_DAT5 IPU1_CSI0_DATA 05 ECSPI1_MOSI AUD3_TXD GPIO5_IO23 1.8V Muxing (shared pinout with SATA, resistor configurable, default is SATA) Note 4 98 GND GND Ground 0V GND 99 SATA_TXN SATA_TXM SATA_PHY_TX_N Differential 2.5V SATA transmit output differential (shared pinout with SATA, resistor configurable, default is SATA) Note 4 AUD3_TXFS CSI0_DAT6 IPU1_CSI0_DATA 06 ECSPI1_MISO AUD3_TXFS GPIO5_IO24 1.8V Muxing (shared pinout with SATA, resistor configurable, default is SATA) Note CSI_D1P CSI_D1P CSI_DATA1_P Differential 2.5V MIPI CSI differential data GND GND Ground 0V GND 102 CSI_D1M CSI_D1M CSI_DATA1_N Differential 2.5V MIPI CSI differential data JTAG_TDO JTAG_TDO JTAG_TDO Output 3.3V Test data output 104 CSI_D2P CSI_D2P CSI_DATA2_P Differential 2.5V MIPI CSI differential data JTAG_TDI JTAG_TDI JTAG_TDI Input 3.3V Test data input (47K pull up) 106 CSI_D2M CSI_D2M CSI_DATA2_N Differential 2.5V MIPI CSI differential data JTAG_TCK JTAG_TCK JTAG_TCK Input 3.3V Test clock (47K pull up) 108 GND GND Ground 0V GND 109 JTAG_TMS JTAG_TMS JTAG_TMS Input 3.3V Test mode select (47K pull up) 110 CSI_D0P CSI_D0P CSI_DATA0_P Differential 2.5V MIPI CSI differential data JTAG_nTRST JTAG_TRSTB JTAG_TRSTB Input 3.3V Test reset (47K pull up) 112 CSI_D0M CSI_D0M CSI_DATA0_N Differential 2.5V MIPI CSI differential data GND GND Ground 0V GND 114 CSI_D3M CSI_D3M CSI_DATA3_N Differential 2.5V MIPI CSI differential data 3 Page 22 APC Proprietary Information June 2, 2017

23 115 PCIE_TXP PCIE_TXP PCIE_TX_P Differential 2.5V PCIe differential transmit,0.1uf AC coupling 116 CSI_D3P CSI_D3P CSI_DATA3_P Differential 2.5V MIPI CSI differential data PCIE_TXM PCIE_TXM PCIE_TX_N Differential 2.5V PCIe differential transmit,0.1uf AC coupling 118 GND GND Ground 0V GND 119 GND GND Ground 0V GND 120 CSI_CLK0P CSI_CLK0P CSI_CLK0_P Differential 2.5V MIPI CSI differential clock 121 PCIE_RXP PCIE_RXP PCIE_RX_P Differential 2.5V PCIe differential receive 122 CSI_CLK0M CSI_CLK0M CSI_CLK0_N Differential 2.5V MIPI CSI differential clock 123 PCIE_RXM PCIE_RXM PCIE_RX_N Differential 2.5V PCIe differential receive 124 GND GND Ground 0V GND 125 GND GND Ground 0V GND 126 CSI0_DAT13 CSI0_DAT13 IPU1_CSI0_DATA 1.8V Muxing 13 UART4_RX_DATA GPIO5_IO CLK1_N CLK1_N XTALOSC_CLK1_N Differential 2.5V PCIe clock differential pair 128 CSI0_DAT17 CSI0_DAT17 IPU1_CSI0_DATA 1.8V Muxing 17 UART4_CTS_B GPIO6_IO CLK1_P CLK1_P XTALOSC_CLK1_P Differential 2.5V PCIe clock differential pair 130 CSI0_DAT16 CSI0_DAT16 IPU1_CSI0_DATA 16 UART4_RTS_B GPIO6_IO02 1.8V Muxing 131 GND GND Ground 0V GND 132 CSI0_DAT19 CSI0_DAT19 IPU1_CSI0_DATA 19 UART5_CTS_B GPIO6_IO GPIO7_HDMI_T X_CEC_LINE EIM_A25 ECSPI4_SS1 ECSPI2_RDY GPIO5_IO02 HDMI_TX_CEC_LI NE 1.8V Muxing 134 CSI0_DAT10 CSI0_DAT10 IPU1_CSI0_DATA 1.8V Muxing 10 AUD3_RXC ECSPI2_MISO UART1_TX_DATA GPIO5_IO HDMI_HPD HDMI_HPD HDMI_TX_HPD Input 2.5V HDMI hot plug detect Page 23 APC Proprietary Information June 2, 2017

24 136 CSI0_DAT12 CSI0_DAT12 IPU1_CSI0_DATA 12 UART4_TX_DATA GPIO5_IO GPIO08 GPIO_2 GPIO1_IO02 SD2_WP VEST-VS8300-USG-001, REV A 1.8V Muxing 138 CSI0_DAT11 CSI0_DAT11 IPU1_CSI0_DATA 11 AUD3_RXFS ECSPI2_SS0 UART1_RX_DATA GPIO5_IO29 1.8V Muxing 139 GND GND Ground 0V GND 140 CSI0_DAT14 CSI0_DAT14 IPU1_CSI0_DATA 1.8V Muxing 14 UART5_TX_DATA GPIO6_IO HDMI_CLKM HDMI_CLKM HDMI_TX_CLK_N Differential 2.5V HDMI differential clock (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note 5 DSI_CLK0M DSI_CLK0M DSI_CLK0_N Differential 2.5V DSI differential clock (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note CSI0_DAT15 CSI0_DAT15 IPU1_CSI0_DATA 1.8V Muxing 15 UART5_RX_DATA GPIO6_IO HDMI_CLKP HDMI_CLKP Differential 2.5V HDMI differential clock HDMI_TX_CLK_P (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note 5 DSI_CLK0P DSI_CLK0P Differential 2.5V DSI differential clock DSI_CLK0_P (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note CSI0_DAT18 CSI0_DAT18 IPU1_CSI0_DATA 1.8V Muxing 18 UART5_RTS_B GPIO6_IO GND GND Ground 0V GND 146 CSI0_DAT8_I2C 1_SDA CSI0_DAT8 IPU1_CSI0_DATA 08 ECSPI2_SCLK I2C1_SDA GPIO5_IO26 1.8V Muxing Page 24 APC Proprietary Information June 2, 2017

25 147 HDMI_D0M HDMI_D0M HDMI_TX_DATA0 _N 148 CSI0_DAT9_I2C 1_SCL CSI0_DAT9 IPU1_CSI0_DATA 09 ECSPI2_MOSI I2C1_SCL GPIO5_IO HDMI_D0P HDMI_D0P HDMI_TX_DATA0 _P VEST-VS8300-USG-001, REV A Differential 2.5V HDMI differential data 0 1.8V Muxing Differential 2.5V HDMI differential data CSI0_VSYNCH CSI0_VSYNC IPU1_CSI0_VSYN C GPIO5_IO21 1.8V Muxing 151 GND GND Ground 0V GND 152 CSI0_STROBE CSI0_DATA_EN IPU1_CSI0_DAT_ EN GPIO5_IO HDMI_D1M HDMI_D1M HDMI_TX_DATA1 _N 1.8V Muxing Differential 2.5V HDMI differential data 1 (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note 5 DSI_D0M DSI_D0M DSI_DATA0_N Differential 2.5V DSI differential data 0 (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note CSI0_HSYNCH CSI0_MCLK IPU1_CSI0_HSYN C CCM_CLKO1 GPIO5_IO19 1.8V Muxing 155 HDMI_D1P HDMI_D1P HDMI_TX_DATA1 _P Differential 2.5V HDMI differential data 1 (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note 5 DSI_D0P DSI_D0P DSI_DATA0_P Differential 2.5V DSI differential data 0 (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note GND GND Ground 0V GND 157 HDMI_D2M HDMI_D2M HDMI_TX_DATA2 _N Differential 2.5V HDMI differential data 2 (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note 5 Page 25 APC Proprietary Information June 2, 2017

26 DSI_D1M DSI_D1M DSI_DATA1_N Differential 2.5V DSI differential data 1 (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note CSI0_PIXCLK CSI0_PIXCLK IPU1_CIS0_PIXCL K GPIO5_IO18 1.8V Muxing 159 HDMI_D2P HDMI_D2P HDMI_TX_DATA2 _P Differential 2.5V HDMI differential data 2 (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note 5 DSI_D1P DSI_D1P DSI_DATA1_P Differential 2.5V DSI differential data 1 (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Note GND GND Ground 0V GND 161 GND GND Ground 0V GND 162 I2C3_SCL GPIO_3 I2C3_SCL XTALOSC_REF_CL K_24M CCM_CLKO2 GPIO1_IO03 USB_H1_OC 163 GPIO6_SPDIF_I N ENET_RX_ER USB_OTG_ID SPDIF_IN GPIO1_IO I2C3_SDA GPIO_6 I2C3_SDA GPIO1_IO06 SD2_LCTL 165 GPIO19_SPDIF_ OUT_CCM_CLK 01 GPIO_19 SPDIF_OUT CCM_CLKO1 ECSPI1_RDY GPIO4_IO I2C2_SDA KEY_ROW3 I2C2_SDA I/O (4.7K pull up) 167 CAN1_RX_SPDI F_SR_CLK GPIO_8 XTALOSC_REF_CL K_32K EPIT2_OUT FLEXCAN1_RX UART2_RX_DATA GPIO1_IO08 SPDIF_SR_CLK 168 I2C2_SCL KEY_COL3 I2C2_SCL O (4.7K pull up) 3.3V I2C2 SDA 3.3V I2C2 SCL Page 26 APC Proprietary Information June 2, 2017

27 169 CAN1_TX_SPDI F_LOCK GPIO_7 ECSPI5_RDY EPIT1_OUT FLEXCAN1_TX UART2_TX_DATA GPIO1_IO07 SPDIF_LOCK VEST-VS8300-USG-001, REV A 170 UART4_RXD KEY_ROW0 ECSPI1_MOSI AUD5_TXD UART4_RX_DATA GPIO4_IO07 DCIC2_OUT 171 CAN2_TX KEY_COL4 FLEXCAN2_TX USB_OTG_OC UART5_RTS_B GPIO4_IO UART4_TXD KEY_COL0 ECSPI1_SCLK AUD5_TXC UART4_TX_DATA GPIO4_IO06 DCIC1_OUT 173 CAN2_RX KEY_ROW4 FLEXCAN2_RX USB_OTG_PWR UART5_CTS_B GPIO4_IO UART5_RXD KEY_ROW1 ECSPI1_SS0 AUD5_RXD UART5_RX_DATA GPIO4_IO GND GND Ground 0V GND 176 UART5_TXD KEY_COL1 ECSPI1_MISO AUD5_TXFS UART5_TX_DATA GPIO4_IO LVDS0_TX1_P LVDS0_TX1_P LVDS0_DATA1_P Differential 2.5V LVDS0 Differential pair GND GND Ground 0V GND 179 LVDS0_TX1_N LVDS0_TX1_N LVDS0_DATA1_N Differential 2.5V LVDS0 Differential pair LVDS1_DATA0_N Differential 2.5V LVDS1 Differential pair 0 LVDS1_TX0_N LVDS1_TX0_N 181 LVDS0_TX0_P LVDS0_TX0_P LVDS0_DATA0_P Differential 2.5V LVDS0 Differential pair LVDS1_DATA0_P Differential 2.5V LVDS1 Differential pair 0 LVDS1_TX0_P LVDS1_TX0_P 183 LVDS0_TX0_N LVDS0_TX0_N LVDS0_DATA0_N Differential 2.5V LVDS0 Differential pair LVDS1_DATA1_P Differential 2.5V LVDS1 Differential pair 1 LVDS1_TX1_P LVDS1_TX1_P 185 GND GND Ground 0V GND 186 LVDS1_DATA1_N Differential 2.5V LVDS1 Differential pair 1 LVDS1_TX1_N LVDS1_TX1_N 187 LVDS0_CLK_P LVDS0_CLK_P LVDS0_CLK_P Differential 2.5V LVDS0 clock differential pair 188 GND GND Ground 0V GND Page 27 APC Proprietary Information June 2, 2017

28 189 LVDS0_CLK_N LVDS0_CLK_N LVDS0_CLK_N Differential 2.5V LVDS0 clock differential pair 190 LVDS1_CLK_P Differential 2.5V LVDS1 clock differential LVDS1_CLK_P LVDS1_CLK_P pair 191 GND GND Ground 0V GND 192 LVDS1_CLK_N Differential 2.5V LVDS1 clock differential LVDS1_CLK_N LVDS1_CLK_N pair 193 LVDS0_TX2_P LVDS0_TX2_P LVDS0_DATA2_P Differential 2.5V LVDS0 Differential pair GND GND Ground 0V GND 195 LVDS0_TX2_N LVDS0_TX2_N LVDS0_DATA2_N Differential 2.5V LVDS0 Differential pair LVDS1_DATA3_N Differential 2.5V LVDS1 Differential pair 3 LVDS1_TX3_N LVDS1_TX3_N 197 LVDS0_TX3_P LVDS0_TX3_P LVDS0_DATA3_P Differential 2.5V LVDS0 Differential pair LVDS1_DATA3_P Differential 2.5V LVDS1 Differential pair 3 LVDS1_TX3_P LVDS1_TX3_P 199 LVDS0_TX3_N LVDS0_TX3_N LVDS0_DATA3_N Differential 2.5V LVDS0 Differential pair LVDS1_TX2_N LVDS1_TX2_N LVDS1_DATA2_N Differential 2.5V LVDS1 Differential pair GND GND Ground 0V GND 202 LVDS1_TX2_P LVDS1_TX2_P LVDS1_DATA2_P Differential 2.5V LVDS1 Differential pair PWR_GOOD Output 3.0V SOM power good indicator 204 GND GND Ground 0V GND Table 3-1: SO-DIMM Assignments Notes: 1. The HDMI DDC and I2C4 (for Solo and DualLite only) interface are shared same pinout of pin 3 and 5, its resistor configurable and the default is HDMI DDC interface. Populated Non-populated HDMI DDC Interface (default) R88,R89 R86,R87 I2C4 Interface R86,R87 R88,R89 Table 3-2: Resistors Loading Configurations for HDMI DDC vs. I2C4 2. The SOM board support boot from serial downloader or emmc or NAND Flash or SD2 (4-bit) by the configuration of BOOT_SEL1 and BOOT_SEL0. Serial Downloader emmc SD2(4-bit) NAND Flash BOOT_SEL BOOT_SEL Table 3-3: SOM Board Boot Source Settings 3. The SOM SO-DIMM interface has 9 x SOM_3V3 power input pins which can supply total 2.7A maximum current to SOM, in addition, the SOM also provide 2 x contact pins for extra SOM_3V3 Page 28 APC Proprietary Information June 2, 2017

29 current for QuadPlus CPU, The recommended mating connector for carrier board interfacing is TE: or equivalent. The detail mechanical location for these 2 x contact pins please refer to section The SATA and AUD3 interface are shared same pinout of pin 91,93,97 and 99, its resistor configurable and the default is SATA interface. Populated Non-populated SATA Interface (default) R23,R25,R26,R28 R29,R30,R31,R32 AUD3 Interface R29,R30,R31,R32 R23,R25,R26,R28 Table 3-4: Resistors Loading Configurations for SATA vs. AUD3 5. The HDMI and MIPI DSI interface are shared same pinout of pin 141,143,153,155,157 and 159, its resistor configurable and the default is HDMI interface. Populated Non-populated HDMI Interface (default) R34,R35,R36,R37,R38,R39 R40,R41,R42,R43,R44,R46 MIPI DSI Interface R40,R41,R42,R43,R44,R46 R34,R35,R36,R37,R38,R39 Table 3-5: Resistors Loading Configurations for HDMI vs. MIPI DSI Page 29 APC Proprietary Information June 2, 2017

30 4 SIGNAL DESCRIPTION PER BLOCK/INSTANCE This chapter describes in detail the external interfaces per block/instance, referring to the default SOM pin s. SIGNAL: on the block/instance PIN NO. : number on the connector PIN NAME: on the connector I.MX6 PAD NAME: Pad on imxi.mx6 SIGNAL TYPE: I In O - Out I/O Input/output DESCRIPTION: Short pin functionality description 4.1 ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a signal associated with an input clock into a signal associated with a different output clock. The ASRC is implemented as a co-processor in hardware, with minimal ARM Platform intervention required. The following table describes the external signals of ASRC: ASRC_EXT_CLK 59 USB_HOST_PWR_EN GPIO_0 O 3.3V Table 4-1: External s of ASRC 4.2 DIGITAL AUDIO MUX (AUDMUX) The Digital Audio Multiplexer (AUDMUX) provides a programmable interconnected device for voice, audio, and synchronous data routing between Synchronous Serial Interface Controller (SSI) and audio/voice codec s (also known as coder-decoders) peripheral serial interfaces. The following table describes the external signals of AUDMUX: AUD3_RXC 134 CSI0_DAT10 CSI0_DAT10 I/O 1.8V Receive clock signal AUD3_RXD 93 AUD3_RXD CSI0_DAT7 I/O 1.8V Data receive signal Page 30 APC Proprietary Information June 2, 2017

31 VEST-VS8300-USG-001, REV A (shared with SATA pinout, and default is SATA) AUD3_RXFS 138 CSI0_DAT11 CSI0_DAT11 I/O 1.8V Receive frame sync signal AUD3_TXC 91 AUD3_TXC CSI0_DAT4 I/O 1.8V Transmit clock signal (shared with SATA pinout, and default is SATA) AUD3_TXD 97 AUD3_TXD CSI0_DAT5 I/O 1.8V Data transmit signal (shared with SATA pinout, and default is SATA) AUD3_TXFS 99 AUD3_TXFS CSI0_DAT6 I/O 1.8V Transmit frame sync signal (shared with SATA pinout, and default is SATA) AUD4_RXC 13 VOL_UP_GPIO DISP0_DAT19 I/O 3.3V 46 SD2_CMD SD2_CMD 3.3V Receive clock signal AUD4_RXD AUD4_RXFS AUD4_TXC AUD4_TXD AUD4_TXFS 7 AUD4_RXD DISP0_DAT23 I/O 3.3V 52 SD2_DATA0 SD2_DAT0 I/O 3.3V 11 VOL_DN_GPIO DISP0_DAT18 I/O 3.3V 38 SD2_CLK SD2_CLK I/O 3.3V 15 AUD4_TXC DISP0_DAT20 I/O 3.3V 50 SD2_DATA3 SD2_DAT3 I/O 3.3V 17 AUD4_TXD DISP0_DAT21 I/O 3.3V 48 SD2_DATA2 SD2_DAT2 I/O 3.3V 9 AUD4_TXFS DISP0_DAT22 I/O 3.3V 44 SD2_DATA1 SD2_DAT1 I/O 3.3V Data receive signal Receive frame sync signal Transmit clock signal Data transmit signal Transmit frame sync signal AUD5_RXD 174 UART5_RXD KEY_ROW1 I/O 3.3V Data receive signal 13 VOL_UP_GPIO DISP0_DAT19 I/O 3.3V AUD5_TXC 172 UART4_TXD KEY_COL0 I/O 3.3V Transmit clock signal AUD5_TXD 170 UART4_RXD KEY_ROW0 I/O 3.3V Data transmit signal AUD5_TXFS 176 UART5_TXD KEY_COL1 I/O 3.3V Transmit frame sync signal 11 VOL_DN_GPIO DISP0_DAT18 I/O 3.3V Table 4-2: External s of AUDMUX 4.3 CLOCK CONTROLLER MODULE (CCM) The Clock Control Module (CCM) generates and controls clocks to the various modules in the design and manages low power modes. This module uses the available clock sources to generate the clock roots. The following table describes the external signals of CCM: CCM_CLKO1 154 CSI0_HSYNCH CSI0_MCLK O 1.8V Observability 59 USB_HOST_PWR_EN GPIO_0 3.3V clock 1 output 165 GPIO19_SPDIF_OUT_CCM_CLK01 GPIO_19 3.3V CCM_CLKO2 162 I2C3_SCL GPIO_3 O 3.3V Observability 69 CCM_CLKO2_GPIO NANDF_CS2 3.3V clock 2 output Table 4-3: External s of CCM Page 31 APC Proprietary Information June 2, 2017

32 4.4 DISPLAY CONTENT INTEGRITY CHECKER (DCIC) The goal of the DCIC is to verify that a safety-critical information sent to a display is not corrupted. Such a verification is mandatory for warning icons in the instrument cluster of a car, to comply with the ASIL B (Automotive Safety Integrity B) specification. It is also required in other safetysensitive systems. Using external muxing DCIC can monitor either one of the IPU display port outputs or feedback signals going from IO pads of Parallel display interface. The following table describes the external signals of DCIC: DCIC1_OUT DCIC2_OUT 57 USBHUB_nRST EIM_D17 O 3.3V DCIC1 172 UART4_TXD KEY_COL0 3.3V 170 UART4_RXD KEY_ROW0 O 3.3V DCIC2 52 SD2_DATA0 SD2_DAT0 3.3V Table 4-4: External s of DCIC 4.5 ENHANCED CONFIGURABLE SPI (ECSPI) The Enhanced Configurable Serial Peripheral Interface (ECSPI) is a full-duplex, synchronous, four-wire serial communication block. The ECSPI contains a 64 x 32 receive buffer (RXFIFO) and a 64 x 32 transmit buffer (TXFIFO). With data FIFOs, the ECSPI allows rapid data communication with fewer software interrupts. The following table describes the external signals of ECSPI 1: ECSPI1_MISO ECSPI1_MOSI ECSPI1_RDY ECSPI1_SCLK ECSPI1_SS0 99 AUD3_TXFS CSI0_DAT6 I/O 1.8V (shared pinout with SATA, resistor Master data configurable, default is SATA) in; slave 9 AUD4_TXFS DISP0_DAT22 3.3V data out 57 USBHUB_nRST EIM_D17 3.3V 176 UART5_TXD KEY_COL1 3.3V 97 AUD3_TXD CSI0_DAT5 I/O 1.8V (shared pinout with SATA, resistor Master data configurable, default is SATA) out; slave 17 AUD4_TXD DISP0_DAT21 3.3V data in 170 UART4_RXD KEY_ROW0 3.3V 165 GPIO19_SPDIF_OUT_CCM_CLK01 GPIO_19 I 3.3V SPI data ready signal 91 AUD3_TXC CSI0_DAT4 I/O 1.8V (shared pinout with SATA, resistor configurable, default is SATA) 15 AUD4_TXC DISP0_DAT20 3.3V SPI clock 3 HDMI_TX_DDC_SDA EIM_D16 3.3V signal (shared pinout with I2C4,resistor configurable, default is HDMI_DDC) 172 UART4_TXD KEY_COL0 3.3V 93 AUD3_RXD (shared pinout with SATA, resistor configurable, default is SATA) CSI0_DAT7 I/O 1.8V Chip select signal 7 AUD4_RXD DISP0_DAT23 3.3V Page 32 APC Proprietary Information June 2, 2017

33 ECSPI1_SS1 5 HDMI_TX_DDC_SCL EIM_EB2 3.3V (shared pinout with I2C4,resistor configurable, default is HDMI_DDC) 174 UART5_RXD KEY_ROW1 3.3V 37 UART1_CTS EIM_D19 I/O 3.3V Chip select signal Table 4-5: External s of ECSPI 1 The following table describes the external signals of ECSPI 2: ECSPI2_MISO ECSPI2_MOSI ECSPI2_RDY ECSPI2_SCLK ECSPI2_SS0 134 CSI0_DAT10 CSI0_DAT10 I/O 1.8V Master data in; slave data out 148 CSI0_DAT9_I2C1_SCL CSI0_DAT9 I/O 1.8V Master data out; slave data in 133 GPIO7_HDMI_TX_CEC_LINE EIM_A25 I 3.3V SPI data ready signal 146 CSI0_DAT8_I2C1_SDA CSI0_DAT8 I/O 1.8V 13 VOL_UP_GPIO DISP0_DAT19 3.3V SPI clock signal 138 CSI0_DAT11 CSI0_DAT11 I/O 1.8V 11 VOL_DN_GPIO DISP0_DAT18 3.3V Chip select signal Table 4-6: External s of ECSPI 2 The following table describes the external signals of ECSPI 3: ECSPI3_MISO 33 SPI3_MISO DISP0_DAT2 I/O 3.3V Master data in; slave data out ECSPI3_MOSI 31 SPI3_MOSI DISP0_DAT1 I/O 3.3V Master data out; slave data in ECSPI3_SCLK 25 SPI3_SCLK DISP0_DAT0 I/O 3.3V SPI clock signal ECSPI3_SS0 29 SPI3_CS0 DISP0_DAT3 I/O 3.3V Chip select signal ECSPI3_SS1 27 SPI3_CS1 DISP0_DAT4 I/O 3.3V Chip select signal ECSPI3_SS2 34 SPI3_CS2 DISP0_DAT5 I/O 3.3V Chip select signal ECSPI3_SS3 32 SPI3_CS3 DISP0_DAT6 I/O 3.3V Chip select signal Table 4-7: External s of ECSPI 3 The following table describes the external signals of ECSPI 4: ECSPI4_MISO 74 USB_OTG_PWR_EN EIM_D22 I/O 3.3V Master data in; slave data out ECSPI4_MOSI 47 UART2_CTS EIM_D28 I/O 3.3V Master data out; slave data in ECSPI4_SCLK 71 USB_OTG_OC EIM_D21 I/O 3.3V SPI clock signal ECSPI4_SS0 39 UART1_RTS EIM_D20 I/O 3.3V Chip select signal 45 UART2_RTS EIM_D29 I/O 3.3V ECSPI4_SS1 133 GPIO7_HDMI_TX_CEC_LINE EIM_A25 I/O 3.3V Chip select signal Table 4-8: External s of ECSPI 4 The following table describes the external signals of ECSPI 5: Page 33 APC Proprietary Information June 2, 2017

34 ECSPI5_MISO 52 SD2_DATA0 SD2_DAT0 I/O 3.3V Master data in; 58 GPIO03_SD1_DATA0 SD1_DAT0 3.3V slave data out ECSPI5_MOSI 46 SD2_CMD SD2_CMD I/O 3.3V Master data out; 56 PWM4_OUT_SD1_CMD SD1_CMD 3.3V slave data in ECSPI5_RDY 169 CAN1_TX_SPDIF_LOCK GPIO_7 I 3.3V SPI data ready signal ECSPI5_SCLK 38 SD2_CLK SD2_CLK I/O 3.3V SPI clock signal 70 GPIO02_SD1_CLK SD1_CLK 3.3V ECSPI5_SS0 44 SD2_DATA1 SD2_DAT1 I/O 3.3V Chip select signal 60 PWM3_OUT_SD1_DATA1 SD1_DAT1 3.3V ECSPI5_SS1 62 GPIO04_SD1_DATA2 SD1_DAT2 I/O 3.3V Chip select signal 48 SD2_DATA2 SD2_DAT2 3.3V ECSPI5_SS2 64 GPIO05_SD1_DATA3 SD1_DAT3 I/O 3.3V Chip select signal ECSPI5_SS3 50 SD2_DATA3 SD2_DAT3 I/O 3.3V Chip select signal Table 4-9: External s of ECSPI ENHANCED PERIODIC INTERRUPT TIMER (EPIT) EPIT is a 32-bit set-and-forget timer that is capable of providing precise interrupts at regular intervals with minimal processor intervention. EPIT begins counting after it is enabled by software. The following table describes the external signals of EPIT: EPIT1_OUT EPIT2_OUT 37 UART1_CTS EIM_D19 O 3.3V Output 1 pin at chip boundary 169 CAN1_TX_SPDIF_LOCK GPIO_7 3.3V for indicating the occurrence of an output compare event 59 USB_HOST_PWR_EN GPIO_0 3.3V through a specified transition. 39 UART1_RTS EIM_D20 O 3.3V Output 2 pin at chip boundary 167 CAN1_RX_SPDIF_SR_CLK GPIO_8 3.3V for indicating the occurrence of an output compare event through a specified transition. Table 4-10: External s of EPIT 4.7 FLEXIBLE CONTROLLER AREA NETWORK (FLEXCAN) The Flexible Controller Area Network (FLEXCAN) module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification. The CAN protocol was primarily designed to be used as a vehicle serial data bus meeting the specific requirements of this field: realtime processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FLEXCAN module is a full implementation of the CAN protocol specification, which supports both standard and extended message frames. 64 Message Buffers are supported. The following table describes the external signals of FLEXCAN: FLEXCAN1_RX 167 CAN1_RX_SPDIF _SR_CLK GPIO_8 I 3.3V FLEXCAN receive pin. This pin is the receive pin from the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'. Page 34 APC Proprietary Information June 2, 2017

35 FLEXCAN1_TX 169 CAN1_TX_SPDIF _LOCK GPIO_7 O 3.3V FLEXCAN transmit pin. This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'. FLEXCAN2_RX FLEXCAN2_TX 173 CAN2_RX KEY_ROW4 I 3.3V FLEXCAN receive pin. This pin is the receive pin from the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'. 171 CAN2_TX KEY_COL4 O 3.3V FLEXCAN transmit pin. This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'. Table 4-11: External s of FLEXCAN 4.8 GENERAL PURPOSE INPUT/OUTPUT (GPIO) The GPIO general-purpose input/output peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an output, it is possible to write to an internal register to control the state driven on the output pin. When configured as an input, it is possible to detect the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce CORE interrupts. The following table describes the external signals of GPIO1: GPIO1_IO00 59 USB_HOST_PWR_EN GPIO_0 I/O 3.3V GPIO1_IO01 75 USB_OTG_ID GPIO_1 I/O 3.3V GPIO1_IO GPIO08 GPIO_2 I/O 3.3V GPIO1_IO I2C3_SCL GPIO_3 I/O 3.3V GPIO1_IO04 42 SD2_CD_B GPIO_4 I/O 3.3V GPIO1_IO I2C3_SDA GPIO_6 I/O 3.3V GPIO1_IO07 GPIO1_IO CAN1_TX_SPDIF_LOCK GPIO_7 I/O 3.3V 167 CAN1_RX_SPDIF_SR_CLK GPIO_8 I/O 3.3V GPIO1_IO10 38 SD2_CLK SD2_CLK I/O 3.3V GPIO1_IO11 46 SD2_CMD SD2_CMD I/O 3.3V GPIO1_IO12 50 SD2_DATA3 SD2_DAT3 I/O 3.3V GPIO1_IO13 48 SD2_DATA2 SD2_DAT2 I/O 3.3V Page 35 APC Proprietary Information June 2, 2017

36 GPIO1_IO14 44 SD2_DATA1 SD2_DAT1 I/O 3.3V GPIO1_IO15 52 SD2_DATA0 SD2_DAT0 I/O 3.3V GPIO1_IO16 58 GPIO03_SD1_DATA0 SD1_DAT0 I/O 3.3V GPIO1_IO17 60 PWM3_OUT_SD1_DATA1 SD1_DAT1 I/O 3.3V GPIO1_IO18 56 PWM4_OUT_SD1_CMD SD1_CMD I/O 3.3V GPIO1_IO19 62 GPIO04_SD1_DATA2 SD1_DAT2 I/O 3.3V GPIO1_IO20 70 GPIO02_SD1_CLK SD1_CLK I/O 3.3V GPIO1_IO21 64 GPIO05_SD1_DATA3 SD1_DAT3 I/O 3.3V GPIO1_IO GPIO6_SPDIF_IN ENET_RX_ER I/O 3.3V 5 I2C4_SCL_GPIO ENET_TX_EN I/O 3.3V GPIO1_IO28 (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) I2C4_SDA_GPIO ENET_TXD1 I/O 3,3V GPIO1_IO29 3 (shared pinout with HDMI DDC, resistor configurable, default is HDMI DDC) Table 4-12: External s of GPiO1 The following table describes the external signals of GPIO2: GPIO2_IO30 5 HDMI_TX_DDC_SCL (shared pinout with I2C4, resistor configurable, default is HDMI DDC) EIM_EB2 I/O 3.3V Table 4-13: External s of GPIO2 The following table describes the external signals of GPIO3: 3 HDMI_TX_DDC_SDA EIM_D16 I/O (Default) GPIO3_IO16 (shared pinout with I2C4, resistor configurable, default is HDMI DDC) GPIO3_IO17 57 USBHUB_nRST EIM_D17 I/O 3.3V GPIO3_IO19 37 UART1_CTS EIM_D19 I/O 3.3V GPIO3_IO20 39 UART1_RTS EIM_D20 I/O 3.3V GPIO3_IO21 71 USB_OTG_OC EIM_D21 I/O 3.3V GPIO3_IO22 74 USB_OTG_PWR_EN EIM_D22 I/O 3.3V Page 36 APC Proprietary Information June 2, 2017

37 GPIO3_IO26 51 UART2_TXD EIM_D26 I/O 3.3V GPIO3_IO27 49 UART2_RXD EIM_D27 I/O 3.3V GPIO3_IO28 47 UART2_CTS EIM_D28 I/O 3.3V GPIO3_IO29 45 UART2_RTS EIM_D29 I/O 3.3V GPIO3_IO30 55 USB_HOST_OC EIM_D30 I/O 3.3V Table 4-14: External s of GPIO3 The following table describes the external signals of GPIO4: GPIO4_IO GPIO19_SPDIF_OUT_CCM_CLK01 GPIO_19 3.3V GPIO4_IO UART4_TXD KEY_COL0 3.3V GPIO4_IO UART4_RXD KEY_ROW0 3.3V GPIO4_IO UART5_TXD KEY_COL1 3.3V GPIO4_IO UART5_RXD KEY_ROW1 3.3V GPIO4_IO CAN2_TX KEY_COL4 3.3V GPIO4_IO CAN2_RX KEY_ROW4 3.3V GPIO4_IO21 25 SPI3_SCLK DISP0_DAT0 3.3V GPIO4_IO22 31 SPI3_MOSI DISP0_DAT1 3.3V GPIO4_IO23 33 SPI3_MISO DISP0_DAT2 3.3V GPIO4_IO24 29 SPI3_CS0 DISP0_DAT3 3.3V GPIO4_IO25 27 SPI3_CS1 DISP0_DAT4 3.3V GPIO4_IO26 34 SPI3_CS2 DISP0_DAT5 3.3V GPIO4_IO27 32 SPI3_CS3 DISP0_DAT6 3.3V GPIO4_IO29 23 PWM1_OUT DISP0_DAT8 3.3V GPIO4_IO30 21 PWM2_OUT DISP0_DAT9 3.3V Table 4-15: External s of GPIO4 The following table describes the external signals of GPIO5: GPIO5_IO GPIO7_HDMI_TX_CEC_LINE EIM_A25 I/O 3.3V GPIO5_IO12 11 VOL_DN_GPIO DISP0_DAT18 I/O 3.3V GPIO5_IO13 13 VOL_UP_GPIO DISP0_DAT19 I/O 3.3V GPIO5_IO14 15 AUD4_TXC DISP0_DAT20 I/O 3.3V GPIO5_IO15 17 AUD4_TXD DISP0_DAT21 I/O 3.3V Page 37 APC Proprietary Information June 2, 2017

38 GPIO5_IO16 9 AUD4_TXFS DISP0_DAT22 I/O 3.3V GPIO5_IO17 7 AUD4_RXD DISP0_DAT23 I/O 3.3V GPIO5_IO CSI0_PIXCLK CSI0_PIXCLK I/O 1.8V GPIO5_IO CSI0_HSYNCH CSI0_MCLK I/O 1.8V GPIO5_IO CSI0_STROBE CSI0_DATA_EN I/O 1.8V GPIO5_IO CSI0_VSYNCH CSI0_VSYNC I/O 1.8V 9 AUD3_TXC CSI0_DAT4 I/O 1.8V GPIO5_IO22 (shared pinout with SATA, resistor configurable, default is SATA) 97 AUD3_TXD CSI0_DAT5 I/O 1.8V GPIO5_IO23 (shared pinout with SATA, resistor configurable, default is SATA) 99 AUD3_TXFS CSI0_DAT6 I/O 1.8V GPIO5_IO24 (shared pinout with SATA, resistor configurable, default is SATA) 93 AUD3_RXD CSI0_DAT7 I/O 1.8V GPIO5_IO25 (shared pinout with SATA, resistor configurable, default is SATA) GPIO5_IO CSI0_DAT8_I2C1_SDA CSI0_DAT8 I/O 1.8V GPIO5_IO CSI0_DAT9_I2C1_SCL CSI0_DAT9 I/O 1.8V GPIO5_IO CSI0_DAT10 CSI0_DAT10 I/O 1.8V GPIO5_IO CSI0_DAT11 CSI0_DAT11 I/O 1.8V GPIO5_IO CSI0_DAT12 CSI0_DAT12 I/O 1.8V GPIO5_IO CSI0_DAT13 CSI0_DAT13 I/O 1.8V Muxing Table 4-16: External s of GPIO5 The following table describes the external signals of GPIO6: GPIO6_IO CSI0_DAT14 CSI0_DAT14 I/O 1.8V GPIO6_IO CSI0_DAT15 CSI0_DAT15 I/O 1.8V GPIO6_IO CSI0_DAT16 CSI0_DAT16 I/O 1.8V GPIO6_IO CSI0_DAT17 CSI0_DAT17 I/O 1.8V GPIO6_IO CSI0_DAT18 CSI0_DAT18 I/O 1.8V GPIO6_IO CSI0_DAT19 CSI0_DAT19 I/O 1.8V Page 38 APC Proprietary Information June 2, 2017

39 GPIO6_IO15 69 CCM_CLKO2_GPIO NANDF_CS2 I/O 3.3V GPIO6_IO16 66 GPIO01_SD1_CD_B NANDF_CS3 I/O 3.3V Table 4-17: External s of GPIO6 The following table describes the external signals of GPI5_IO18: GPI5_IO18 43 UART1_RXD_C SD3_DAT6 I 3.3V General purpose input Table 4-18: External s of GPI5_IO18 The following table describes the external signals of GPO6_IO17: GPO6_IO17 41 UART1_TXD_C SD3_DAT7 O 3.3V General purpose output Table 4-19: External s of GPO6_IO GENERAL PURPOSE TIMER (GPT) The GPT has a 32-bit up-counter. The timer counter value can be captured in a register using an event on an external pin. The capture trigger can be programmed to be a rising or/and falling edge. The GPT can also generate an event on the DO_CMPOUTn pins and an interrupt when the timer reaches a programmed value. The GPT has a 12-bit prescaler, which provides a programmable clock frequency derived from multiple clock sources. The following table describes the external signals of GPT: GPT_CAPTURE1 GPT_CAPTURE2 GPT_CLKIN GPT_COMPARE1 GPT_COMPARE2 58 GPIO03_SD1_DATA0 SD1_DAT0 I 3.3V Input pin for a capture event for Input Capture Channel 1 60 PWM3_OUT_SD1_DATA1 SD1_DAT1 I 3.3V Input pin for a capture event for Input Capture Channel 2 70 GPIO02_SD1_CLK SD1_CLK I 3.3V Input pin for an external clock that the counter can be operated at 56 PWM4_OUT_SD1_CMD SD1_CMD O 3.3V Output pin that indicates a "compare event" occurrence in Output Compare Channel 1 62 GPIO04_SD1_DATA2 SD1_DAT2 O 3.3V Output pin that indicates a "compare event" occurrence in Output Compare Channel 2 Page 39 APC Proprietary Information June 2, 2017

40 GPT_COMPARE3 64 GPIO05_SD1_DATA3 SD1_DAT3 O 3.3V Output pin that indicates a "compare event" occurrence in Output Compare Channel 3 Table 4-20: External s of GPT 4.10 HDMI The High Definition Multimedia Interface (HDMI) is a wired digital interconnect that replaces the analog TV out or VGA out. HDMI is capable of transferring uncompressed video, audio, and data using a single cable. The following table describes the external signals of HDMI. HDMI_TX_CEC_LINE 133 GPIO7_HDMI_TX_CEC_LINE EIM_A25 I/O 3.3V CEC line between source and sink HDMI_TX_CLK_N 141 HDMI_CLKM (shared pinout with MIPI DSI, resistor configurable, default is HDMI) HDMI_CLKM I 2.5V HDMI differential clock HDMI_TX_CLK_P 143 HDMI_CLKP (shared pinout with MIPI DSI, resistor configurable, default is HDMI) HDMI_CLKP I 2.5V HDMI differential clock HDMI_TX_DATA0_N HDMI_TX_DATA0_P 147 HDMI_D0M HDMI_D0M I/O 2.5V HDMI differential data HDMI_D0P HDMI_D0P I/O 2.5V HDMI differential data 0 HDMI_TX_DATA1_N HDMI_TX_DATA1_P HDMI_TX_DATA2_N 153 HDMI_D1M (shared pinout with MIPI DSI, resistor configurable, default is HDMI) 155 HDMI_D1P (shared pinout with MIPI DSI, resistor configurable, default is HDMI) 157 HDMI_D2M (shared pinout with MIPI DSI, resistor configurable, default is HDMI) HDMI_D1M I/O 2.5V HDMI differential data 1 HDMI_D1P I/O 2.5V HDMI differential data 1 HDMI_D2M I/O 2.5V HDMI differential data 2 Page 40 APC Proprietary Information June 2, 2017

41 HDMI_TX_DATA2_P HDMI_TX_DDC_SCL HDMI_TX_DDC_SDA 159 HDMI_D2P (shared pinout with MIPI DSI, resistor configurable, default is HDMI) 5 HDMI_TX_DDC_SCL (shared pinout with I2C4, resistor configurable, default is HDMI DDC) 3 HDMI_TX_DDC_SDA (shared pinout with I2C4, resistor configurable, default is HDMI DDC) HDMI_D2P I/O 2.5V HDMI differential data 2 EIM_EB2 I/O 3.3V HDMI DDC SCL signal EIM_D16 I/O 3.3V HDMI DDC SDA signal HDMI_TX_HPD 135 HDMI_HPD HDMI_HPD I/O 2.5V HDMI hot plug detect Table 4-21: External s of HDMI 4.11 I2C The Inter IC (I2C) provides functionality of a standard I2C slave and master. The I2C is designed to be compatible with the standard NXP I2C bus protocol. I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. The flexible I2C standard allows additional devices to be connected to the bus for expansion and system development. The following table describes the external signals of I2C 1: I2C1_SCL I2C1_SDA 148 CSI0_DAT9_I2C1_SCL CSI0_DAT9 I/O 1.8V Serial clock 71 USB_OTG_OC EIM_D21 3.3V 146 CSI0_DAT8_I2C1_SDA CSI0_DAT8 I/O 1.8V Serial data 47 UART2_CTS EIM_D28 3.3V Table 4-22: External s of I2C 1 The following table describes the external signals of I2C 2: I2C2_SCL I2C2_SDA 168 I2C2_SCL KEY_COL3 O (4.7K pull up) 166 I2C2_SDA KEY_ROW3 I/O (4.7K pull up) 3.3V Serial clock 3.3V Serial data Table 4-23: External s of I2C 2 The following table describes the external signals of I2C 3: Page 41 APC Proprietary Information June 2, 2017

42 I2C3_SCL 57 USBHUB_nRST EIM_D17 I/O 3.3V Serial clock 162 I2C3_SCL GPIO_3 3.3V I2C3_SDA 164 I2C3_SDA GPIO_6 I/O 3.3V Serial data Table 4-24: External s of I2C 3 The following table describes the external signals of I2C 4(for Solo and DualLite only): I2C4_SCL I2C4_SDA 5 I2C4_SCL_GPIO ENET_TX_EN I/O 3.3V Serial clock (shared pinout with HDMI DDC, (for Solo resistor configurable, default is and DualLite HDMI DDC) only) 3 I2C4_SDA_GPIO ENET_TXD1 I/O 3,3V Serial data (shared pinout with HDMI DDC, (for Solo resistor configurable, default is and DualLite HDMI DDC) only) Table 4-25: External s of I2C IMAGE PROCESSING UNIT (IPU) The IPU is planned to be a part of the video and graphics subsystem in an application processor. The goal of the IPU is to provide comprehensive support for the flow of data from an image sensor and/or to a display device. The following table describes the external signals of IPU: IPU1_CSI0_DATA03 55 USB_HOST_OC EIM_D30 I 3.3V 91 AUD3_TXC CSI0_DAT4 I 1.8V IPU1_CSI0_DATA04 (shared pinout with SATA, resistor configurable, default is SATA) 97 AUD3_TXD CSI0_DAT5 I 1.8V IPU1_CSI0_DATA05 (shared pinout with SATA, resistor configurable, default is SATA) 99 AUD3_TXFS CSI0_DAT6 I 1.8V IPU1_CSI0_DATA06 (shared pinout with SATA, resistor configurable, default is SATA) 93 AUD3_RXD CSI0_DAT7 I 1.8V IPU1_CSI0_DATA07 (shared pinout with SATA, resistor configurable, default is SATA) IPU1_CSI0_DATA CSI0_DAT8_I2C1_SDA CSI0_DAT8 I 1.8V IPU1_CSI0_DATA CSI0_DAT9_I2C1_SCL CSI0_DAT9 I 1.8V IPU1_CSI0_DATA CSI0_DAT10 CSI0_DAT10 I 1.8V IPU1_CSI0_DATA CSI0_DAT11 CSI0_DAT11 I 1.8V IPU1_CSI0_DATA CSI0_DAT12 CSI0_DAT12 I 1.8V IPU1_CSI0_DATA CSI0_DAT13 CSI0_DAT13 I 1.8V IPU1_CSI0_DATA CSI0_DAT14 CSI0_DAT14 I 1.8V IPU1_CSI0_DATA CSI0_DAT15 CSI0_DAT15 I 1.8V Page 42 APC Proprietary Information June 2, 2017

43 IPU1_CSI0_DATA CSI0_DAT16 CSI0_DAT16 I 1.8V IPU1_CSI0_DATA CSI0_DAT17 CSI0_DAT17 I 1.8V IPU1_CSI0_DATA CSI0_DAT18 CSI0_DAT18 I 1.8V IPU1_CSI0_DATA CSI0_DAT19 CSI0_DAT19 I 1.8V IPU1_CSI0_DATA_EN 152 CSI0_STROBE CSI0_DATA_EN I 1.8V IPU1_CSI0_HSYNC 154 CSI0_HSYNCH CSI0_MCLK I 1.8V IPU1_CSI0_PIXCLK 158 CSI0_PIXCLK CSI0_PIXCLK I 1.8V IPU1_CSI0_VSYNC 150 CSI0_VSYNCH CSI0_VSYNC I 1.8V Table 4-26: External s of IPU 4.13 LVDS DISPLAY BRIDGE (LDB) The LVDS Display Bridge (LDB) connects the IPU (Image Processing Unit) to an External LVDS Display Interface. The purpose of the LDB is to support flow of synchronous RGB data from the IPU to external display devices through LVDS interface. The following table describes the external signals of LDB: LVDS0_CLK_N LVDS0_CLK_P LVDS0_DATA0_N LVDS0_DATA0_P LVDS0_DATA1_N LVDS0_DATA1_P LVDS0_DATA2_N LVDS0_DATA2_P LVDS0_DATA3_N LVDS0_DATA3_P LVDS1_CLK_N LVDS1_CLK_P LVDS1_DATA0_N LVDS1_DATA0_P LVDS1_DATA1_N LVDS1_DATA1_P LVDS1_DATA2_N LVDS1_DATA2_P 189 LVDS0_CLK_N LVDS0_CLK_N O 2.5V LVDS0 clock differential pair 187 LVDS0_CLK_P LVDS0_CLK_P O 2.5V LVDS0 clock differential pair 183 LVDS0_TX0_N LVDS0_TX0_N O 2.5V LVDS0 Differential pair LVDS0_TX0_P LVDS0_TX0_P O 2.5V LVDS0 Differential pair LVDS0_TX1_N LVDS0_TX1_N O 2.5V LVDS0 Differential pair LVDS0_TX1_P LVDS0_TX1_P O 2.5V LVDS0 Differential pair LVDS0_TX2_N LVDS0_TX2_N O 2.5V LVDS0 Differential pair LVDS0_TX2_P LVDS0_TX2_P O 2.5V LVDS0 Differential pair LVDS0_TX3_N LVDS0_TX3_N O 2.5V LVDS0 Differential pair LVDS0_TX3_P LVDS0_TX3_P O 2.5V LVDS0 Differential pair O 2.5V LVDS1 clock differential pair LVDS1_CLK_N LVDS1_CLK_N 190 O 2.5V LVDS1 clock differential pair LVDS1_CLK_P LVDS1_CLK_P 180 O 2.5V LVDS1 Differential pair 0 LVDS1_TX0_N LVDS1_TX0_N 182 O 2.5V LVDS1 Differential pair 0 LVDS1_TX0_P LVDS1_TX0_P 186 O 2.5V LVDS1 Differential pair 1 LVDS1_TX1_N LVDS1_TX1_N 184 O 2.5V LVDS1 Differential pair 1 LVDS1_TX1_P LVDS1_TX1_P 200 LVDS1_TX2_N LVDS1_TX2_N O 2.5V LVDS1 Differential pair LVDS1_TX2_P LVDS1_TX2_P O 2.5V LVDS1 Differential pair 2 Page 43 APC Proprietary Information June 2, 2017

44 LVDS1_DATA3_N LVDS1_DATA3_P LVDS1_TX3_N LVDS1_TX3_N O 2.5V LVDS1 Differential pair 3 LVDS1_TX3_P LVDS1_TX3_P O 2.5V LVDS1 Differential pair 3 Table 4-27: External s of LDB 4.14 MIPI- CAMERA SERIAL INTERFACE HOST CONTROLLER (MIPI_CSI) CSI-2 is a high performance serial interconnect bus for mobile applications connecting camera sensors to the host system. The CSI-2 Host Controller is a digital core that implements all protocol functions defined in the MIPI CSI-2 Specification, providing an interface between the System and the MIPID-PHY, allowing the communication with a MIPI CSI-2 compliant Camera Sensor. The following table describes the external signals of MIPI_CSI: CSI_CLK0_N CSI_CLK0_P CSI_DATA0_N CSI_DATA0_P CSI_DATA1_N CSI_DATA1_P CSI_DATA2_N CSI_DATA2_P CSI_DATA3_N CSI_DATA3_P 122 CSI_CLK0M CSI_CLK0M I 2.5V MIPI CSI differential clock 120 CSI_CLK0P CSI_CLK0P I 2.5V MIPI CSI differential clock 112 CSI_D0M CSI_D0M I 2.5V MIPI CSI differential data CSI_D0P CSI_D0P I 2.5V MIPI CSI differential data CSI_D1M CSI_D1M I 2.5V MIPI CSI differential data CSI_D1P CSI_D1P I 2.5V MIPI CSI differential data CSI_D2M CSI_D2M I 2.5V MIPI CSI differential data CSI_D2P CSI_D2P I 2.5V MIPI CSI differential data CSI_D3M CSI_D3M I 2.5V MIPI CSI differential data CSI_D3P CSI_D3P I 2.5V MIPI CSI differential data 3 Table 4-28: External s of MIPI_CSI 4.15 MIPI DISPLAY SERIAL INTERFACE HOST CONTROLLER (MIPI_DSI) DSI is a high performance serial interconnect bus for mobile applications connecting display system to the host system. The DSI Host Controller is a digital core that implements all protocol functions defined in the MIPI DSI Specification, providing an interface between the System and the MIPI D-PHY, and allowing communication with a MIPI DSI-compliant Display. The following table describes the external signals of MIPI_DSI: Page 44 APC Proprietary Information June 2, 2017

45 DSI_CLK0_N 141 DSI_CLK0M (shared pinout with HDMI, resistor configurable, default is HDMI) DSI_CLK0M I 2.5V DSI differential clock DSI_CLK0_P 143 DSI_CLK0P (shared pinout with HDMI, resistor configurable, default is HDMI) DSI_CLK0P I 2.5V DSI differential clock DSI_DATA0_N DSI_DATA0_P DSI_DATA1_N DSI_DATA1_P 153 DSI_D0M (shared pinout with HDMI, resistor configurable, default is HDMI) 155 DSI_D0P (shared pinout with HDMI, resistor configurable, default is HDMI) 157 DSI_D1M (shared pinout with HDMI, resistor configurable, default is HDMI) 159 DSI_D1P (shared pinout with HDMI, resistor configurable, default is HDMI) DSI_D0M I 2.5V DSI differential data 0 DSI_D0P I 2.5V DSI differential data 0 DSI_D1M I 2.5V DSI differential data 1 DSI_D1P I 2.5V DSI differential data 1 Table 4-29: External s of MIPI_DSI 4.16 PCI EXPRESS (PCIE) PCI Express includes the following cores: PCI Express Dual Mode (DM) core PCI Express Root Complex (RC) core PCI Express Endpoint (EP) core The following table describes the external signals of PCIe: PCIE_RX_N 123 PCIE_RXM PCIE_RXM I 2.5V PCIe differential receive PCIE_RX_P 121 PCIE_RXP PCIE_RXP I 2.5V PCIe differential receive PCIE_TX_N PCIE_TX_P 117 PCIE_TXM PCIE_TXM O 2.5V PCIe differential transmit,0.1uf AC coupling 115 PCIE_TXP PCIE_TXP O 2.5V PCIe differential transmit,0.1uf AC coupling Table 4-30: External s of PCIe Page 45 APC Proprietary Information June 2, 2017

46 4.17 PULSE WIDTH MODULATION (PWM) The Pulse Width Modulation (PWM) has a 16-bit counter, and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bitresolution and a 4 x 16 data FIFO. The following table describes the external signals of PWM: PWM1_OUT PWM2_OUT PWM3_OUT PWM4_OUT PWM1_OUT GPIO05_SD1_DATA3 DISP0_DAT8 SD1_DAT3 O 3.3V 3.3V This is the PWM1 functional output of the PWM. A modulated signal of the block is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50% PWM2_OUT USB_OTG_ID DISP0_DAT9 GPIO_1 O 3.3V 3.3V This is the PWM2 functional output of the PWM. A modulated signal of the block is observed at this pin. It can 62 GPIO04_SD1_DATA2 SD1_DAT2 3.3V be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50%. 60 PWM3_OUT_SD1_DATA1 SD1_DAT1 O 3.3V This is the PWM3 functional output of the PWM. A modulated signal of the block is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50%. 56 PWM4_OUT_SD1_CMD SD1_CMD O 3.3V This is the PWM4 functional output of the PWM. A modulated signal of the block is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50%. Table 4-31: External s of PWM 4.18 SERIAL ADVANCED TECHNOLOGY ATTACHMENT PHY (SATA PHY) The Serial-ATA PHY is an ultra-low-power SATA physical layer that complies with Serial ATA, Revision 2.5. The following table describes the external signals of SATA PHY: SATA_PHY_RX_N 93 SATA_RXN (shared pinout with AUD3, resistor configurable, default is SATA) SATA_RXM I 2.5V SATA receive input differential Page 46 APC Proprietary Information June 2, 2017

47 SATA_PHY_RX_P SATA_PHY_TX_N SATA_PHY_TX_P 91 SATA_RXP (shared pinout with AUD3, resistor configurable, default is SATA) 99 SATA_TXN (shared pinout with AUD3, resistor configurable, default is SATA) 97 SATA_TXP (shared pinout with AUD3, resistor configurable, default is SATA) SATA_RXP I 2.5V SATA receive input differential SATA_TXM O 2.5V SATA transmit output differential SATA_TXP O 2.5V SATA transmit output differential Table 4-32: External s of SATA 4.19 SYSTEM JTAG CONTROLLER (SJC) The System JTAG Controller (SJC) provides debug and test control with the maximum security. The following table describes the external signals of SJC: JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRSTB 107 JTAG_TCK JTAG_TCK I 3.3V Test Clock (TCK). This is used to synchronize the test logic and includes an internal pull-up resistor 105 JTAG_TDI JTAG_TDI I 3.3V Test Data Input (TDI). Serial test instruction and data are received through the test data input (TDI) pin. TDI is sampled on the rising edge of TCK and includes an internal pull up resistor 103 JTAG_TDO JTAG_TDO O 3.3V Test Data Output (TDO). The serial output for test instructions and data. TDO is tri-statable and is actively driven in the shift-ir and shift-dr controller states. TDO changes on the falling edge of TCK 109 JTAG_TMS JTAG_TMS I 3.3V Test Mode Select (TMS). This is used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and includes an internal pull up resistor 111 JTAG_nTRST JTAG_TRSTB I 3.3V Test Reset (TRST). This is used to asynchronously initialize the test controller. The TRST pin has an internal pull up resistor Table 4-33: External s of SJC Page 47 APC Proprietary Information June 2, 2017

48 4.20 SONY/PHILIPS DIGITAL INTERFACE (SPDIF) The Sony/Philips Digital Interface (SPDIF) audio block is a stereo transceiver that allows the processor to receive and transmit digital audio. The following table describes the external signals of SPDIF: SPDIF_IN 163 GPIO6_SPDIF_IN ENET_RX_ER I 3.3V Input line 71 USB_OTG_OC EIM_D21 3.3V SPDIF_LOCK 169 CAN1_TX_SPDIF_LOCK GPIO_7 O 3.3V Lock signal SPDIF_OUT 74 USB_OTG_PWR_EN EIM_D22 O 3.3V Output line 165 GPIO19_SPDIF_OUT_CCM_CLK01 GPIO_19 3.3V signal SPDIF_SR_CLK 167 CAN1_RX_SPDIF_SR_CLK GPIO_8 O 3.3V SR lock signal Table 4-34: External s of SPDIF 4.21 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) Universal Asynchronous Receiver/Transmitter (UART) provides serial communication capability with external devices through a level converter and an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA compatibility. UART supports NRZ encoding format, RS485 compatible 9-bit data format and IrDA-compatible infrared slow data rate (SIR) format. The following table describes the external signals of UART1: UART1_CTS_B 37 UART1_CTS EIM_D19 O 3.3V Clear to send UART1_RTS_B 39 UART1_RTS EIM_D20 I 3.3V Request to send UART1_RX_DATA UART1_TX_DATA 138 CSI0_DAT11 CSI0_DAT11 I 1.8V Serial / infrared data receive 43 UART1_RXD_C SD3_DAT6 3.3V 134 CSI0_DAT10 CSI0_DAT10 O 1.8V Serial / infrared data transmit 41 UART1_TXD_C SD3_DAT7 3.3V Table 4-35: External s of UART1 The following table describes the external signals of UART2: UART2_CTS_B 47 UART2_CTS EIM_D28 O 3.3V Clear to send UAT2_RTS_B 45 UART2_RTS EIM_D29 I 3.3V Request to send UART2_RX_DATA 49 UART2_RXD EIM_D27 I 3.3V Serial / infrared data 167 CAN1_RX_SPDIF_SR_CLK GPIO_8 3.3V receive Page 48 APC Proprietary Information June 2, 2017

49 UART2_TX_DATA 169 CAN1_TX_SPDIF_LOCK GPIO_7 O 3.3V Serial / infrared data 51 UART2_TXD EIM_D26 3.3V transmit Table 4-36: External s of UART2 The following table describes the external signals of UART4: UART4_CTS_B 128 CSI0_DAT17 CSI0_DAT17 O 1.8V Clear to send UART4_RTS_B 130 CSI0_DAT16 CSI0_DAT16 I 1.8V Request to send UART4_RX_DATA UART4_TX_DATA 126 CSI0_DAT13 CSI0_DAT13 I 1.8V Serial / infrared 170 UART4_RXD KEY_ROW0 3.3V data receive 172 UART4_TXD KEY_COL0 O 3.3V Serial / infrared 136 CSI0_DAT12 CSI0_DAT12 1.8V data transmit Table 4-37: External s of UART4 The following table describes the external signals of UART5: UART5_CTS_B UART5_RTS_B UART5_RX_DATA UART5_TX_DATA 173 CAN2_RX KEY_ROW4 O 3.3V Clear to send 132 CSI0_DAT19 CSI0_DAT19 1.8V 144 CSI0_DAT18 CSI0_DAT18 I 1.8V Request to send 171 CAN2_TX KEY_COL4 3.3V 174 UART5_RXD KEY_ROW1 I 3.3V Serial / infrared 142 CSI0_DAT15 CSI0_DAT15 1.8V data receive 176 UART5_TXD KEY_COL1 O 3.3V Serial / infrared 140 CSI0_DAT14 CSI0_DAT14 1.8V data transmit Table 4-38: External s of UART UNIVERSAL SERIAL BUS CONTROLLER (USB) The USB controller block provides high performance USB functionality that conforms to the Universal Serial Bus Specification, Rev. 2.0, and the On-The-Go and Embedded Host Supplement to the USB Revision2.0 Specification. The following table describes the external signals of USB: USB_H1_DN USB_H1_DP 79 USB_HOST_DN USB_H1_DN I/O 3.0V USB host data 81 USB_HOST_DP USB_H1_DP I/O 3.0V USB host data Page 49 APC Proprietary Information June 2, 2017

50 USB_H1_OC USB_H1_PWR USB_OTG_DN USB_OTG_DP USB_OTG_ID USB_OTG_OC USB_OTG_PWR USB_HOST_OC I2C3_SCL EIM_D30 GPIO_3 I 3.3V 3.3V USB host external input for VBUS over current detection 59 USB_HOST_PWR_EN GPIO_0 O 3.3V To control power switch to supply VBUS voltage 87 USB_OTG_DN USB_OTG_DN I/O 3.0V USB OTG data 85 USB_OTG_DP USB_OTG_DP I/O 3.0V USB OTG data 75 USB_OTG_ID GPIO_1 I 3.3V USB OTG ID signal 163 GPIO6_SPDIF_IN ENET_RX_ER 3.3V USB_OTG_OC CAN2_TX EIM_D21 KEY_COL4 I 3.3V 3.3V USB OTG external input for VBUS over current detection USB_OTG_PWR_EN CAN2_RX EIM_D22 KEY_ROW4 O 3.3V 3.3V To control power switch to supply VBUS voltage Table 4-39: External s of USB 4.23 ULTRA SECURED DIGITAL HOST CONTROLLER (USDHC) The Ultra Secured Digital Host Controller (usdhc) provides the interface between the host system and the SD/SDIO/MMC cards. The usdhc acts as a bridge, passing host bus transactions to the SD/SDIO/MMC cards by sending commands and performing data accesses to/from the cards. It handles the SD/SDIO/MMC protocols at the transmission level. The following table describes the external signals of USDHC1: SD1_CD_B 75 USB_OTG_ID GPIO_1 I 3.3V Card detection pin If not used (for the embedded memory), tie low to indicate there is a card attached. SD1_CLK 70 GPIO02_SD1_CLK SD1_CLK O 3.3V Clock for MMC/SD/SDIO card SD1_CMD 56 PWM4_OUT_SD1_CMD SD1_CMD I/O 3.3V CMD line connect to card SD1_DATA0 58 GPIO03_SD1_DATA0 SD1_DAT0 I/O 3.3V DATA0 line SD1_DATA1 60 PWM3_OUT_SD1_DATA1 SD1_DAT1 I/O 3.3V DATA1 line SD1_DATA2 62 GPIO04_SD1_DATA2 SD1_DAT2 I/O 3.3V DATA2 line Page 50 APC Proprietary Information June 2, 2017

51 SD1_DATA3 64 GPIO05_SD1_DATA3 SD1_DAT3 I/O 3.3V DATA3 line Table 4-40: External s of USDHC1 The following table describes the external signals of USDHC2: SD2_CD_B 42 SD2_CD_B GPIO_4 I 3.3V Card detection pin If not used (for the embedded memory), tie low to indicate there is a card attached. SD2_CLK 38 SD2_CLK SD2_CLK O 3.3V Clock for MMC/SD/SDIO card SD2_CMD 46 SD2_CMD SD2_CMD I/O 3.3V CMD line connect to card SD2_DATA0 52 SD2_DATA0 SD2_DAT0 I/O 3.3V DATA0 line SD2_DATA1 44 SD2_DATA1 SD2_DAT1 I/O 3.3V DATA1 line SD2_DATA2 48 SD2_DATA2 SD2_DAT2 I/O 3.3V DATA2 line SD2_DATA3 50 SD2_DATA3 SD2_DAT3 I/O 3.3V DATA3 line SD2_LCTL 164 I2C3_SDA GPIO_6 O 3.3V LED control used to drive an external LED Active high Fully controlled by the driver Optional output 137 GPIO08 GPIO_2 I 3.3V Card write protect detect SD2_WP If not used (for the embedded memory), tie low to indicate it's not write protected. Table 4-41: External s of USDHC WATCHDOG TIMER (WDOG) The Watchdog Timer (WDOG) protects against system failures by providing a method by which to escape from unexpected events or programming errors. Once the WDOG is activated, it must be serviced by the software on a periodic basis. If servicing does not take place, the timer times out. Upon timeout, the WDOG asserts the internal system reset signal, WDOG_RESET_B_DEB to the System Reset Controller (SRC). The following table describes the external signals of WDOG: WDOG1_B WDOG1_RESET_B_DEB 23 PWM1_OUT DISP0_DAT8 I/O 3.3V This signal will power down the 62 GPIO04_SD1_DATA2 SD1_DAT2 3.3V chip. 62 GPIO04_SD1_DATA2 SD1_DAT2 O 3.3V This signal is a reset source for the chip. Page 51 APC Proprietary Information June 2, 2017

52 WDOG2_B WDOG2_RESET_B_DEB 21 PWM2_OUT DISP0_DAT9 I/O 3.3V This signal will power down the 75 USB_OTG_ID GPIO_1 3.3V chip. 64 GPIO05_SD1_DATA3 SD1_DAT3 3.3V 64 GPIO05_SD1_DATA3 SD1_DAT3 O 3.3V This signal is a reset source for the chip. Table 4-42: External s of WDOG 4.25 CRYSTAL OSCILLATOR (XTALOSC) This block comprises both the 24 MHz and 32 khz implementation of a biased amplifier that when combined with a suitable external quartz crystal and external load capacitors, implements an oscillator. The following table describes the external signals of XTALOSC: XTALOSC_CLK1_N XTALOSC_CLK1_P XTALOSC_OSC32K_32K_OUT XTALOSC_REF_CLK_24M XTALOSC_REF_CLK_32K 127 CLK1_N CLK1_N I/O 2.5V Negative differential clock 129 CLK1_P CLK1_P 2.5V Positive differential clock 70 GPIO02_SD1_CLK SD1_CLK 3.3V 162 I2C3_SCL GPIO_3 3.3V 24MHz reference clock 167 CAN1_RX_SPDIF_SR_CLK GPIO_8 3.3V 32KHz reference clock Table 4-43: External s of XTALSOC /100/1000-MBPS ETHERNET (ENET) The ENET is connect from AR8035, the AR8035 is Atheros 4 th generation, single port, 10/100/1000 Mbps, Tri-speed Ethernet PHY which compliant with the IEEE standard. The following table describes the external signals of ENET: TXRXN_D 24 TXRXN_D From AR8035_TXRXN3 I/O - Media-dependent interface 3, differential 100ohm transmission line TXRXP_D 22 TXRXP_D From AR8035_TXRXP3 I/O - Media-dependent interface 3, differential 100ohm transmission line Page 52 APC Proprietary Information June 2, 2017

53 TXRXN_C 18 TXRXN_C From AR8035_TXRXN2 I/O - Media-dependent interface 2, differential 100ohm transmission line TXRXP_C 16 TXRXP_C From AR8035_TXRXP2 I/O - Media-dependent interface 2, differential 100ohm transmission line TXRXN_B 12 TXRXN_B From AR8035_TXRXN1 I/O - Media-dependent interface 1, differential 100ohm transmission line TXRXP_B 10 TXRXP_B From AR8035_TXRXP2 I/O - Media-dependent interface 1, differential 100ohm transmission line TXRXN_A 6 TXRXN_A From AR8035_TXRXN0 I/O - Media-dependent interface 0, differential 100ohm transmission line TXRXP_A 4 TXRXP_A From AR8035_TXRXP0 I/O - Media-dependent interface 0, differential 100ohm transmission line LED_ACT 28 RGMII_LED_ACT From AR8035 LED_ACT I/O 3.3V Parallel LED output for 10/100/1000 BASE-T activity; need pull up to 3.3V during power on reset, active low. See note 1 LED_10_1 00_ RGMII_LED_10_100_1000 AND From AR8035 LED_LINK10_100 and LED_LINK1000 I/O 3.3V Parallel LED output for 10/100 /1000 BASE-T link, need pull up to 3.3V during power on reset, active low. See note 1 Table 4-44: External s of ENET Note 1: LED Status 10M Link 10M Active 100M Link 100M Active 1000M Link 1000M Active LED_ACT Active Blink Active Blink Active Blink LED_10_100_100 Inactive Inactive Active Active Active Active Page 53 APC Proprietary Information June 2, 2017

54 5 ELECTRICAL SPECIFICATION 5.1 ABSOLUTE MAXIMUM CHARACTERISTICS Minimum Maximum Unit Main Power Supply, DC-IN V Table 5-1: Absolute Maximum Characteristics 5.2 OPERATIONAL CHARACTERISTICS Power Supplies The VS8300 SOM is designed to be driven with a single +3.3VDC input power. Minimum Typical Maximum Unit of Input Power V Current of Input Power 3 A Table 5-2: Power Suppliers Requirement Power Consumption The VS8300 SOM power consumption is measured in VC8300 carrier board while running different power scripts under Android Power Script Power Script Operation 3.3V Input 1 Power Script 1 LVDS/RGB Play video Audio Headphone in USB Keyboard and Mouse??A (Solo)??A (DualLite)??A (Dual)??A (Quad)??A (DualPlus)??A (QuadPlus) 2 Power Script 2 LVDS/RGB Play video Audio Headphone in Ethernet g test CPU Run Stability TEST Utility??A (Solo)??A (DualLite)??A (Dual)??A (Quad)??A (DualPlus)??A (QuadPlus) 3 Standby OS is in idle mode??a (Solo)??A (DualLite)??A (Dual)??A (Quad)??A (DualPlus)??A (QuadPlus) Page 54 APC Proprietary Information June 2, 2017

55 Table 5-3: VS8300 SOM power consumption Note: Power consumption is measured in particular condition and it may vary platform to platform based on board configuration. Depending upon board configuration, overall system design and cooling mechanism, customer may need to choose the appropriate heat solution. Page 55 APC Proprietary Information June 2, 2017

56 6 LAYOUT RECOMMENDATIONS This chapter provides recommendations to assist design engineers with the correct layout of their SOM based systems. 6.1 SOM BOARD TRACE LENGTH Length matching is needed to be considered for each groups of the high speed signals. The trace lengths of each SOM board signals are listed below. The designer of the carrier board needs to take note of the trace length on the SOM when performing system signals length matching Trace Length of SO-DIMM s Trace Length (Unit: mil) Trace Length (Unit: mil) 1 GND 2 GND 3 HDMI_TX_DDC_SDA TXRXP_A I2C4_SDA_GPIO HDMI_TX_DDC_SCL TXRXN_A I2C4_SCL_GPIO AUD4_RXD GND 9 AUD4_TXFS TXRXP_B VOL_DN_GPIO TXRXN_B VOL_UP_GPIO GND 15 AUD4_TXC TXRXP_C AUD4_TXD TXRXN_C GND 20 GND 21 PWM2_OUT TXRXP_D PWM1_OUT TXRXN_D SPI3_SCLK GND 27 SPI3_CS RGMII_LED_ACT SPI3_CS RGMII_LED_10_100_ SPI3_MOSI SPI3_CS SPI3_MISO SPI3_CS GND 36 GND 37 UART1_CTS SD2_CLK UART1_RTS GND 41 UART1_TXD_C SD2_CD_B UART1_RXD_C SD2_DATA UART2_RTS SD2_CMD UART2_CTS SD2_DATA Page 56 APC Proprietary Information June 2, 2017

57 Trace Length (Unit: mil) Trace Length (Unit: mil) 49 UART2_RXD SD2_DATA UART2_TXD SD2_DATA GND 54 GND 55 USB_HOST_OC PWM4_OUT_SD1_CMD USBHUB_nRST GPIO03_SD1_DATA USB_HOST_PWR_EN PWM3_OUT_SD1_DATA USB_HOST_VBUS 62 GPIO04_SD1_DATA GND 64 GPIO05_SD1_DATA BOOT_SEL GPIO01_SD1_CD_B BOOT_SEL GND 69 CCM_CLKO2_GPIO GPIO02_SD1_CLK USB_OTG_OC GND 73 USB_OTG_VBUS 74 USB_OTG_PWR_EN USB_OTG_ID CPUPWRON GND GND 78 PMIC_REST USB_HOST_DN SOM_3V3 81 USB_HOST_DP SOM_3V3 83 GND 84 SOM_3V3 85 USB_OTG_DP SOM_3V3 87 USB_OTG_DN SOM_3V3 89 GND GND 90 SOM_3V3 91 SATA_RXP SOM_3V3 AUD3_TXC SATA_RXN SOM_3V3 AUD3_RXD GND GND 96 SOM_3V3 97 SATA_TXP GND AUD3_TXD SATA_TXN CSI_D1P AUD3_TXFS GND 102 CSI_D1M JTAG_TDO CSI_D2P JTAG_TDI CSI_D2M JTAG_TCK GND Page 57 APC Proprietary Information June 2, 2017

58 Trace Length (Unit: mil) Trace Length (Unit: mil) 109 JTAG_TMS CSI_D0P JTAG_nTRST CSI_D0M GND 114 CSI_D3M PCIE_TXP CSI_D3P PCIE_TXM GND 119 GND 120 CSI_CLK0P PCIE_RXP CSI_CLK0M PCIE_RXM GND 125 GND 126 CSI0_DAT CLK1_N CSI0_DAT CLK1_P CSI0_DAT GND 132 CSI0_DAT GPIO7_HDMI_TX_CEC_LINE CSI0_DAT HDMI_HPD CSI0_DAT GPIO CSI0_DAT GND 140 CSI0_DAT HDMI_CLKM CSI0_DAT DSI_CLK0M HDMI_CLKP CSI0_DAT DSI_CLK0P GND 146 CSI0_DAT8_I2C1_SDA HDMI_D0M CSI0_DAT9_I2C1_SCL HDMI_D0P CSI0_VSYNCH GND 152 CSI0_STROBE HDMI_D1M CSI0_HSYNCH DSI_D0M HDMI_D1P GND DSI_D0P HDMI_D2M CSI0_PIXCLK DSI_D1M HDMI_D2P GND DSI_D1P GND 162 I2C3_SCL GPIO6_SPDIF_IN I2C3_SDA Page 58 APC Proprietary Information June 2, 2017

59 Trace Length (Unit: mil) Trace Length (Unit: mil) 165 GPIO19_SPDIF_OUT_CCM_CL K I2C2_SDA CAN1_RX_SPDIF_SR_CLK I2C2_SCL CAN1_TX_SPDIF_LOCK UART4_RXD CAN2_TX UART4_TXD CAN2_RX UART5_RXD GND 176 UART5_TXD LVDS0_TX1_P GND 179 LVDS0_TX1_N LVDS1_TX0_N LVDS0_TX0_P LVDS1_TX0_P LVDS0_TX0_N LVDS1_TX1_P GND 186 LVDS1_TX1_N LVDS0_CLK_P GND 189 LVDS0_CLK_N LVDS1_CLK_P GND 192 LVDS1_CLK_N LVDS0_TX2_P GND 195 LVDS0_TX2_N LVDS1_TX3_N LVDS0_TX3_P LVDS1_TX3_P LVDS0_TX3_N LVDS1_TX2_N GND 202 LVDS1_TX2_P PWR_GOOD 204 GND Table 6-1: Trace Length of SO-DIMM s 6.2 PCI EXPRESS INTERFACE RECOMMENDATIONS Use the following recommendations for PCI Express interface: PCIe differential pairs should have a differential impedance of 85Ω +/- 10%. Each differential pair should be length matched to +/- 5 mils Match the signals with respect to PCIE_CLK (clock signal) +/- 50mils 6.3 LVDS RECOMMENDATIONS Use the following recommendations for the LVDS: LVDS differential pairs should have a differential impedance of 100Ω +/- 10%. Each differential pair should be length matched to +/- 5 mils Match the signals with respect to LVDS_CLK (clock signal) +/- 50mils Page 59 APC Proprietary Information June 2, 2017

60 6.4 USB RECOMMENDATIONS Use the following recommendations for the USB: The differential pairs should have a differential impedance of 90Ω +/- 10%. Each differential pair should be length matched to +/- 5 mils 6.5 MIPI CSI RECOMMENDATIONS Use the following recommendations for the MIPI CSI: The differential pairs should have a differential impedance of 100Ω +/- 10%. Each differential pair should be length matched to +/- 5 mils Match the signals with respect to CSI_CLK (clock signal) +/- 25mils 6.6 MIPI DSI RECOMMENDATIONS Use the following recommendations for the MIPI DSI: The differential pairs should have a differential impedance of 100Ω +/- 10%. Each differential pair should be length matched to +/- 5 mils Match the signals with respect to CSI_CLK (clock signal) +/- 25mils 6.7 SD INTERFACE RECOMMENDATIONS Use the following recommendations for the SD interface: Trace impedance for all signals is 50 ohm +/- 10% Match the signals with respect to SDx_CLK (clock signal) +/- 50mils. 6.8 CSI PARALLEL RECOMMENDATIONS Use the following recommendations for the CSI parallel interface: Trace impedance for all signals is 50 ohm +/- 10% Match the signals with respect to CSI0_PIXCLK (clock signal) +/- 50mils. 6.9 I2S RECOMMENDATIONS Use the following recommendations for the I2S interface: Trace impedance for all signals is 50 ohm +/- 10% Match the signals with respect to AUD3_TXC (clock signal) +/- 100mils SPI INTERFACE RECOMMENDATIONS Use the following recommendations for the SPI interface: Trace impedance for all signals is 50 ohm +/- 10% Match the signals with respect to SPI_CLK (clock signal) +/- 50mils ENET INTERFACE RECOMMENDATIONS Use the following recommendations for the ENET interface: Page 60 APC Proprietary Information June 2, 2017

61 Trace impedance for each differential pair is 100 ohm +/- 10% Within the differential signals, match the signals +/- 5mils Same pair P/N skew should be less than 20 mils Match the signals with respect to ENET_REF_CLK_50M (clock signal) +/- 100mils. The length for each differential pair should be within to 4 inch 6.12 HDMI RECOMMENDATIONS Use the following recommendations for the HDMI interface: Trace impedance for each differential pair is 100 ohm +/- 10% Within the differential signals, match the signals +/- 5mils Match the signals with respect to HDMI_CLK (clock signal) +/- 50mils SATA RECOMMENDATIONS Use the following recommendations for the SATA interface: Trace impedance for each differential pair is 100 ohm +/- 10% Within the differential signals, match the signals +/- 5mils Match the signals +/- 100mils. Page 61 APC Proprietary Information June 2, 2017

62 7 ENVIRONMENT SPECIFICATION 7.1 TEMPERATURE SPECIFICATION The VS8300 SOM has multiple variants with some configurations available in an option of multiple operating temperature specifications. For detail, please refer to Section 9 Board Options. Note: The VS8300 SOM comes in different operating temperature grade of the SOM components. Nevertheless, customer should consider specific thermal design for the final product upon the specific operating environment and operational conditions for it while also taking into account the expected operational life of the product. Please refer to i.mx 6 product lifetime usage estimates documents mentioned in the Section 1.5 specific to the SoC variant for more information. 7.2 HUMIDITY Operating: 10% to 90% (Non-condensing) Non-operating: 5% to 95% (Non-condensing) Page 62 APC Proprietary Information June 2, 2017

63 8 MECHANICAL SPECIFICATIONS 8.1 MODULE DIMENSION 68mm x 42mm 8.2 HEIGHT ON TOP Maximum 3.0mm (without printed circuit board) 8.3 HEIGHT ON BOTTOM Maximum approximately 1.3mm (without printed circuit board) 8.4 MECHANICAL DRAWING Contact pin Figure 8-1: Top View Figure 8-2: Bottom View Unit: INCH [MM], Tolerance: +/- 0.1mm Page 63 APC Proprietary Information June 2, 2017