STM32F730x8. Arm Cortex -M7 32b MCU+FPU, 462DMIPS, 64KB Flash / KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF. Features

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1 STM32F730x8 Arm Cortex M7 32b MCU+FPU, 462DMIPS, 64KB Flash / KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF Features Datasheet production data Core: Arm 32bit Cortex M7 CPU with FPU, adaptive realtime accelerator (ART Accelerator ) and L1cache: 8 Kbytes of data cache and 8 Kbytes of instruction cache, allowing 0wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1) and DSP instructions. Memories 64 Kbytes of Flash memory with protection mechanisms (read and write protections, proprietary code readout protection (PCROP)) 528 bytes of OTP memory SRAM: 256 Kbytes (including 64 Kbytes of data TCM RAM for critical realtime data) + 16 Kbytes of instruction TCM RAM (for critical realtime routines) + 4 Kbytes of backup SRAM (available in the lowest power modes) Flexible external memory controller with up to 32bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories Dual mode QuadSPI Clock, reset and supply management 1.7 V to 3.6 V application supply and I/Os POR, PDR, PVD and BOR Dedicated USB power 4to26 MHz crystal oscillator Internal 16 MHz factorytrimmed RC (1% accuracy) 32 khz oscillator for RTC with calibration Internal 32 khz RC with calibration Lowpower Sleep, Stop and Standby modes LQFP64 (10 10 mm) LQFP100 (14 14 mm) LQFP144 (20 20 mm) FBGA UFBGA176 (10 x 10 mm) V BAT supply for RTC, bit backup registers + 4 Kbytes of backup SRAM 3 12bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode 2 12bit D/A converters Up to 18 timers: up to thirteen 16bit (1x lowpower 16bit timer available in Stop mode) and two 32bit timers, each with up to 4 IC/OC/PWMs or pulse counter and quadrature (incremental) encoder inputs. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer Generalpurpose DMA: 16stream DMA controller with FIFOs and burst support Debug mode SWD & JTAG interfaces Cortex M7 Trace Macrocell Up to 138 I/O ports with interrupt capability Up to 136 fast I/Os up to 108 MHz Up to Vtolerant I/Os Up to 21 communication interfaces Up to 3 I 2 C interfaces (SMBus/PMBus) Up to 4 USARTs/4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) Up to 5 SPIs (up to 54 Mbit/s), 3 with muxed simplex I 2 Ss for audio class accuracy via internal audio PLL or external clock 2 x SAIs (serial audio interface) June 2018 DS12536 Rev 1 1/201 This is information on a product in full production.

2 STM32F730x8 1 x CAN (2.0B active) 2 x SDMMCs Advanced connectivity USB 2.0 fullspeed device/host/otg controller with onchip PHY USB 2.0 highspeed/fullspeed device/host/otg controller with dedicated DMA, onchip fullspeed PHY and onchip Hispeed PHY or ULPI depending on the part number AES: 128/256bit key encryption hardware accelerator True random number generator CRC calculation unit RTC: subsecond accuracy, hardware calendar 96bit unique ID Table 1. Device summary Reference STM32F730x8 Part number STM32F730R8, STM32F730V8, STM32F730Z8, STM32F730I8 2/201 DS12536 Rev 1

3 STM32F730x8 Contents Contents 1 Introduction Description Full compatibility throughout the family STM32F730x8 LQFP144 packages: Functional overview Arm Cortex M7 with FPU Memory protection unit Embedded Flash memory CRC (cyclic redundancy check) calculation unit Embedded SRAM AXIAHB bus matrix DMA controller (DMA) Flexible memory controller (FMC) QuadSPI memory interface (QUADSPI) Nested vectored interrupt controller (NVIC) External interrupt/event controller (EXTI) Clocks and startup Boot modes Power supply schemes Power supply supervisor Internal reset ON Internal reset OFF Voltage regulator Regulator ON Regulator OFF Regulator ON/OFF and internal reset ON/OFF availability Realtime clock (RTC), backup SRAM and backup registers Lowpower modes V BAT operation Timers and watchdogs DS12536 Rev 1 3/201 6

4 Contents STM32F730x Advancedcontrol timers (TIM1, TIM8) Generalpurpose timers (TIMx) Basic timers TIM6 and TIM Lowpower timer (LPTIM1) Independent watchdog Window watchdog SysTick timer Interintegrated circuit interface (I 2 C) Universal synchronous/asynchronous receiver transmitters (USART) Serial peripheral interface (SPI)/inter integrated sound interfaces (I2S) Serial audio interface (SAI) Audio PLL (PLLI2S) Audio PLL (PLLSAI) SD/SDIO/MMC card host interface (SDMMC) Controller area network (bxcan) Universal serial bus onthego fullspeed (OTG_FS) Universal serial bus onthego highspeed (OTG_HS) Random number generator (RNG) Advanced encryption standard hardware accelerator (AES) Generalpurpose input/outputs (GPIOs) Analogtodigital converters (ADCs) Temperature sensor Digitaltoanalog converter (DAC) Serial wire JTAG debug port (SWJDP) Embedded Trace Macrocell Pinouts and pin description Memory mapping Electrical characteristics Parameter conditions Minimum and maximum values Typical values Typical curves /201 DS12536 Rev 1

5 STM32F730x8 Contents Loading capacitor Pin input voltage Power supply scheme Current consumption measurement Absolute maximum ratings Operating conditions General operating conditions VCAP1/VCAP2 external capacitor Operating conditions at powerup / powerdown (regulator ON) Operating conditions at powerup / powerdown (regulator OFF) Reset and power control block characteristics Overdrive switching characteristics Supply current characteristics Wakeup time from lowpower modes External clock source characteristics Internal clock source characteristics PLL characteristics PLL spread spectrum clock generation (SSCG) characteristics USB OTG HS PHY PLLs characteristics USB OTG HS PHY regulator characteristics USB HS PHY external resistor characteristics Memory characteristics EMC characteristics Absolute maximum ratings (electrical sensitivity) I/O current injection characteristics I/O port characteristics NRST pin characteristics TIM timer characteristics RTC characteristics bit ADC characteristics Temperature sensor characteristics V BAT monitoring characteristics Reference voltage DAC electrical characteristics Communications interfaces FMC characteristics QuadSPI interface characteristics DS12536 Rev 1 5/201 6

6 Contents STM32F730x SD/SDIO MMC card host interface (SDMMC) characteristics Package information LQFP64 10 x 10 mm, lowprofile quad flat package information LQFP100, 14 x 14 mm lowprofile quad flat package information LQFP144, 20 x 20 mm lowprofile quad flat package information UFBGA176+25, 10 x 10, 0.65 mm ultra thinpitch ball grid array package information Thermal characteristics Ordering information Appendix A Recommendations when using internal reset OFF A.1 Operating conditions Revision history /201 DS12536 Rev 1

7 STM32F730x8 List of tables List of tables Table 1. Device summary Table 2. STM32F730x8 features and peripheral counts Table 3. Voltage regulator configuration mode versus device operating mode Table 4. Regulator ON/OFF and internal reset ON/OFF availability Table 5. Voltage regulator modes in stop mode Table 6. Timer feature comparison Table 7. I2C implementation Table 8. USART implementation Table 9. Legend/abbreviations used in the pinout table Table 10. STM32F730x8 pin and ball definition Table 11. FMC pin definition Table 12. STM32F730x8 alternate function mapping Table 13. Voltage characteristics Table 14. Current characteristics Table 15. Thermal characteristics Table 16. General operating conditions Table 17. Limitations depending on the operating power supply range Table 18. VCAP1/VCAP2 operating conditions Table 19. VCAP1 operating conditions in the LQFP64 package Table 20. Operating conditions at powerup / powerdown (regulator ON) Table 21. Operating conditions at powerup / powerdown (regulator OFF) Table 22. reset and power control block characteristics Table 23. Overdrive switching characteristics Table 24. Typical and maximum current consumption in Run mode, code with data processing running from ITCM RAM, regulator ON Table 25. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART ON except prefetch / L1cache ON) or SRAM on AXI (L1cache ON), regulator ON Table 26. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory or SRAM on AXI (L1cache disabled), regulator ON Table 27. Typical and maximum current consumption in Run mode, code with data processing Table 28. running from Flash memory on ITCM interface (ART disabled), regulator ON Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART ON except prefetch / L1cache ON) or SRAM on AXI (L1cache ON), regulator OFF Table 29. Typical and maximum current consumption in Sleep mode, regulator ON Table 30. Typical and maximum current consumption in Sleep mode, regulator OFF Table 31. Typical and maximum current consumptions in Stop mode Table 32. Typical and maximum current consumptions in Standby mode Table 33. Typical and maximum current consumptions in V BAT mode Table 34. Switching output I/O current consumption Table 35. Peripheral current consumption Table 36. USB OTG HS and USB OTG PHY HS current consumption Table 37. Lowpower mode wakeup timings Table 38. Highspeed external user clock characteristics Table 39. Lowspeed external user clock characteristics Table 40. HSE 426 MHz oscillator characteristics Table 41. LSE oscillator characteristics (f LSE = khz) DS12536 Rev 1 7/201 9

8 List of tables STM32F730x8 Table 42. HSI oscillator characteristics Table 43. LSI oscillator characteristics Table 44. Main PLL characteristics Table 45. PLLI2S characteristics Table 46. PLLISAI characteristics Table 47. SSCG parameters constraint Table 48. USB OTG HS PLL1 characteristics Table 49. USB OTG HS PLL2 characteristics Table 50. USB OTG HS PHY regulator characteristics Table 51. USB HS PHY external resistor characteristics Table 52. Flash memory characteristics Table 53. Flash memory programming Table 54. Flash memory programming with VPP Table 55. Flash memory endurance and data retention Table 56. EMS characteristics Table 57. EMI characteristics Table 58. ESD absolute maximum ratings Table 59. Electrical sensitivities Table 60. I/O current injection susceptibility Table 61. I/O static characteristics Table 62. Output voltage characteristics Table 63. I/O AC characteristics Table 64. NRST pin characteristics Table 65. TIMx characteristics Table 66. RTC characteristics Table 67. ADC characteristics Table 68. ADC static accuracy at f ADC = 18 MHz Table 69. ADC static accuracy at f ADC = 30 MHz Table 70. ADC static accuracy at f ADC = 36 MHz Table 71. ADC dynamic accuracy at f ADC = 18 MHz limited test conditions Table 72. ADC dynamic accuracy at f ADC = 36 MHz limited test conditions Table 73. Temperature sensor characteristics Table 74. Temperature sensor calibration values Table 75. V BAT monitoring characteristics Table 76. internal reference voltage Table 77. Internal reference voltage calibration values Table 78. DAC characteristics Table 79. Minimum I2CCLK frequency in all I2C modes Table 80. I2C analog filter characteristics Table 81. SPI dynamic characteristics Table 82. I 2 S dynamic characteristics Table 83. SAI characteristics Table 84. USB OTG full speed startup time Table 85. USB OTG full speed DC electrical characteristics Table 86. USB OTG full speed electrical characteristics Table 87. USB HS DC electrical characteristics Table 88. USB HS clock timing parameters Table 89. Dynamic characteristics: USB ULPI Table 90. USB OTG high speed DC electrical characteristics Table 91. USB OTG high speed electrical characteristics Table 92. USB FS PHY BCD electrical characteristics Table 93. Asynchronous nonmultiplexed SRAM/PSRAM/NOR read timings /201 DS12536 Rev 1

9 STM32F730x8 List of tables Table 94. Asynchronous nonmultiplexed SRAM/PSRAM/NOR read NWAIT timings Table 95. Asynchronous nonmultiplexed SRAM/PSRAM/NOR write timings Table 96. Asynchronous nonmultiplexed SRAM/PSRAM/NOR write NWAIT timings Table 97. Asynchronous multiplexed PSRAM/NOR read timings Table 98. Asynchronous multiplexed PSRAM/NOR readnwait timings Table 99. Asynchronous multiplexed PSRAM/NOR write timings Table 100. Asynchronous multiplexed PSRAM/NOR writenwait timings Table 101. Synchronous multiplexed NOR/PSRAM read timings Table 102. Synchronous multiplexed PSRAM write timings Table 103. Synchronous nonmultiplexed NOR/PSRAM read timings Table 104. Synchronous nonmultiplexed PSRAM write timings Table 105. Switching characteristics for NAND Flash read cycles Table 106. Switching characteristics for NAND Flash write cycles Table 107. SDRAM read timings Table 108. LPSDR SDRAM read timings Table 109. SDRAM write timings Table 110. LPSDR SDRAM write timings Table 111. QuadSPI characteristics in SDR mode Table 112. QuadSPI characteristics in DDR mode Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V Table 114. Dynamic characteristics: emmc characteristics, VDD=1.71V to 1.9V Table 115. LQFP64 10 x 10 mm, lowprofile quad flat package mechanical data Table 116. LQPF100, 14 x 14 mm 100pin lowprofile quad flat package mechanical data Table 117. LQFP144, 20 x 20 mm, 144pin lowprofile quad flat package Table 118. mechanical data UFBGA176+25, mm ultra thin finepitch ball grid array package mechanical data Table 119. UFBGA recommended PCB design rules (0.65 mm pitch BGA) Table 120. Package thermal characteristics Table 121. Ordering information scheme Table 122. Limitations depending on the operating power supply range Table 123. Document revision history DS12536 Rev 1 9/201 9

10 List of figures STM32F730x8 List of figures Figure 1. Compatible board design for LQFP100 package Figure 2. Compatible board design for LQFP64 package Figure 3. Compatible board design for LQFP144 package Figure 4. STM32F730x8 block diagram Figure 5. STM32F730x8 AXIAHB bus matrix architecture (1) Figure 6. VDDUSB connected to VDD power supply Figure 7. VDDUSB connected to external power supply Figure 8. Power supply supervisor interconnection with internal reset OFF Figure 9. PDR_ON control with internal reset OFF Figure 10. Regulator OFF Figure 11. Startup in regulator OFF: slow V DD slope Figure 12. powerdown reset risen after V CAP_1 /V CAP_2 stabilization Startup in regulator OFF mode: fast V DD slope powerdown reset risen before V CAP_1 /V CAP_2 stabilization Figure 13. STM32F730R8 LQFP64 pinout Figure 14. STM32F730V8 LQFP100 pinout Figure 15. STM32F730Z8 LQFP144 pinout Figure 16. STM32F730I8 UFBGA176 ballout (with OTG PHY HS) Figure 17. Pin loading conditions Figure 18. Pin input voltage Figure 19. STM32F730x8 power supply scheme Figure 20. STM32F730x8 power supply scheme Figure 21. Current consumption measurement scheme Figure 22. External capacitor C EXT Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Typical V BAT current consumption (RTC ON/BKP SRAM OFF and LSE in low drive mode) Typical V BAT current consumption (RTC ON/BKP SRAM OFF and LSE in medium low drive mode) Typical V BAT current consumption (RTC ON/BKP SRAM OFF and LSE in medium high drive mode) Typical V BAT current consumption (RTC ON/BKP SRAM OFF and LSE in high drive mode) Typical V BAT current consumption (RTC ON/BKP SRAM OFF and LSE in high medium drive mode) Figure 28. Highspeed external clock source AC timing diagram Figure 29. Lowspeed external clock source AC timing diagram Figure 30. Typical application with an 8 MHz crystal Figure 31. Typical application with a khz crystal Figure 32. ACCHSI versus temperature Figure 33. LSI deviation versus temperature Figure 34. PLL output clock waveforms in center spread mode Figure 35. PLL output clock waveforms in down spread mode Figure 36. FT I/O input characteristics Figure 37. I/O AC characteristics definition Figure 38. Recommended NRST pin protection Figure 39. ADC accuracy characteristics Figure 40. Typical connection diagram using the ADC Figure 41. Power supply and reference decoupling (V REF+ not connected to V DDA ) /201 DS12536 Rev 1

11 STM32F730x8 List of figures Figure 42. Power supply and reference decoupling (V REF+ connected to V DDA ) Figure bit buffered /nonbuffered DAC Figure 44. SPI timing diagram slave mode and CPHA = Figure 45. SPI timing diagram slave mode and CPHA = Figure 46. SPI timing diagram master mode Figure 47. I 2 S slave timing diagram (Philips protocol) (1) Figure 48. I 2 S master timing diagram (Philips protocol) (1) Figure 49. SAI master timing waveforms Figure 50. SAI slave timing waveforms Figure 51. USB OTG full speed timings: definition of data signal rise and fall time Figure 52. ULPI timing diagram Figure 53. Asynchronous nonmultiplexed SRAM/PSRAM/NOR read waveforms Figure 54. Asynchronous nonmultiplexed SRAM/PSRAM/NOR write waveforms Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms Figure 57. Synchronous multiplexed NOR/PSRAM read timings Figure 58. Synchronous multiplexed PSRAM write timings Figure 59. Synchronous nonmultiplexed NOR/PSRAM read timings Figure 60. Synchronous nonmultiplexed PSRAM write timings Figure 61. NAND controller waveforms for read access Figure 62. NAND controller waveforms for write access Figure 63. NAND controller waveforms for common memory read access Figure 64. NAND controller waveforms for common memory write access Figure 65. SDRAM read access waveforms (CL = 1) Figure 66. SDRAM write access waveforms Figure 67. QuadSPI timing diagram SDR mode Figure 68. QuadSPI timing diagram DDR mode Figure 69. SDIO highspeed mode Figure 70. SD default mode Figure 71. LQFP64 10 x 10 mm, lowprofile quad flat package outline Figure 72. LQFP64 10 x 10 mm, lowprofile quad flat package recommended footprint Figure 73. LQFP64 10 x 10 mm, lowprofile quad flat package top view example Figure 74. LQFP100, 14 x 14 mm 100pin lowprofile quad flat package outline Figure 75. LQFP100, 14 x 14 mm, 100pin lowprofile quad flat package recommended footprint Figure 76. LQFP100, 14 x 14 mm, 100pin lowprofile quad flat package top view example Figure 77. LQFP144, 20 x 20 mm, 144pin lowprofile quad flat package outline Figure 78. LQFP144, 20 x 20 mm, 144pin lowprofile quad flat package recommended footprint Figure 79. LQFP144, 20 x 20mm, 144pin lowprofile quad flat package top view example Figure 80. UFBGA176+25, mm ultra thin finepitch ball grid array package outline Figure 81. UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra finepitch ball grid array package recommended footprint Figure 82. UFBGA176+25, mm ultra thin finepitch ball grid array package top view example DS12536 Rev 1 11/201 11

12 Introduction STM32F730x8 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F730x8 microcontrollers. This document should be ready in conjunction with the STM32F72xxx and STM32F73xxx advanced Arm based 32bit MCUs reference manual (RM0431). The reference manual is available from the STMicroelectronics website For information on the Arm (a) Cortex M7 core, refer to the Cortex M7 technical reference manual available from the website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 12/201 DS12536 Rev 1

13 STM32F730x8 Description 2 Description The STM32F730x8 devices are based on the highperformance Arm Cortex M7 32bit RISC core operating at up to 216 MHz frequency. The Cortex M7 core features a single floating point unit (SFPU) precision which supports Arm singleprecision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security. The STM32F730x8 devices incorporate highspeed embedded memories with a Flash memory of 64 Kbytes, 256 Kbytes of SRAM (including 64 Kbytes of data TCM RAM for critical realtime data), 16 Kbytes of instruction TCM RAM (for critical realtime routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32bit multi AHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access. All the devices offer three 12bit ADCs, two DACs, a lowpower RTC, thirteen generalpurpose 16bit timers including two PWM timers for motor control, two generalpurpose 32 bit timers, a true random number generator (RNG). They also feature standard and advanced communication interfaces. Up to three I 2 Cs Five SPIs, three I 2 Ss in half duplex mode. To achieve the audio class accuracy, the I 2 S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. Four USARTs plus four UARTs An USB OTG fullspeed and a USB OTG highspeed with fullspeed capability (with the ULPI only for the LQFP64 and LQFP100 packages and with the integrated HS PHY for the LQFP144 and UFBGA176 packages) One CAN Two SAI serial audio interfaces Two SDMMC host interfaces Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a QuadSPI Flash memory interface. The STM32F730x8 devices operate in the 40 to +105 C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for the USB (OTG_FS and OTG_HS) and the SDMMC2 (clock, command and 4bit data) are available on all the packages except LQFP100 and LQFP64 for a greater power supply choice. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A comprehensive set of powersaving mode allows the design of lowpower applications. The STM32F730x8 devices offer devices in 4 packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen. DS12536 Rev 1 13/201 49

14 Description STM32F730x8 These features make the STM32F730x8 microcontrollers suitable for a wide range of applications: Motor drive and application control, Medical equipment, Industrial applications: PLC, inverters, circuit breakers, Printers, and scanners, Alarm systems, video intercom, and HVAC, Home audio appliances, Mobile applications, Internet of Things, Wearable devices: smartwatches. The following table lists the peripherals available on each part number. 14/201 DS12536 Rev 1

15 STM32F730x8 Description Table 2. STM32F730x8 features and peripheral counts Peripherals STM32F730R8 STM32F730V8 STM32F730Z8 STM32F730I8 Flash memory in Kbytes 64 SRAM in Kbytes System 256( ) Instruction 16 Backup 4 FMC memory controller No Yes (1) QuadSPI Timers Random number generator Communication interfaces AES Yes Generalpurpose 10 (2) Advancedcontrol 2 Basic 2 Lowpower No 1 SPI / I 2 S 3/3 (simplex) (3) 4/3 (simplex) (3) 5/3 (simplex) (3) I 2 C 3 Yes USART/UART 4/2 4/4 USB OTG FS USB OTG HS USB OTG PHY HS No controller (USBPHYC) CAN 1 SAI 2 SDMMC1 Yes SDMMC2 No Yes (4)(5) GPIOs bit ADC Yes Yes Yes 3 Yes Number of channels bit DAC Number of channels Maximum CPU frequency 216 MHz (6) Operating voltage 1.7 to 3.6 V (7) Operating temperatures Yes 2 Ambient temperatures: 40 to +85 C / 40 to +105 C Junction temperature: 40 to C Package LQFP64 LQFP100 LQFP144 UFBGA For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. DS12536 Rev 1 15/201 49

16 Description STM32F730x8 2. On the STM32F730x8 device packages, except the 176pin ones, the TIM12 is not available, so there are 9 generalpurpose timers. 3. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 4. The SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package. 5. The SDMMC2 is not available on the STM32F730Vx devices MHz maximum frequency for 40 C to + 85 C ambient temperature range (200 MHz maximum frequency for 40 C to C ambient temperature range). 7. V DD /V DDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section : Internal reset OFF). 16/201 DS12536 Rev 1

17 STM32F730x8 Description 2.1 Full compatibility throughout the family The STM32F730x8 devices with LQFP64 and LQFP100 packages are fully pintopin, compatible with the STM32F7x5xx, STM32F7x6xx, STM32F7x7xx devices. The STM32F730x8 devices with LQFP64 and LQFP100 packages are fully pintopin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. Figure 1 and Figure 2 give compatible board designs between the STM32F730x8, with LQFP64 and LQFP100 packages, and STM32F4xx families. Figure 1. Compatible board design for LQFP100 package PC3 VDD VSSA VREF+ VDDA PA0WKUP PA1 PA STM32F427xx / STM32F437xx STM32F429xx / STM32F439xx STM32F415xx / STM32F417xx STM32F405xx / STM32F407xx PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP1 VDD PC3 VSSA VREF+ VDDA PA0WKUP PA1 PA2 PA Pins 19 to 49 are not compatible STM32F73xxx VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP1 VSS VDD MSv41002V2 DS12536 Rev 1 17/201 49

18 Description STM32F730x8 Figure 2. Compatible board design for LQFP64 package PC12 PC11 PC10 PA15 PA14 STM32F405/ STM32F415 line STM32F4x PB11 not available anymore 36 Replaced by V CAP_ VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PB2 PB10 VCAP_1 VSS VDD PC12 PC11 PC10 PA15 PA VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 VSS VDD VSS VDD PB2 PB10 PB11 VCAP_1 VDD V CAP increased to 4.7 μf ESR 1 ohm or below 1 ohm VSS VDD VSS VDD PB5 PB4 PB3 PD2 PC12 PC 11 PC10 P A15 P A STM32F730x PC5 not available anymore 36 Replaced by V CAP_ VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 VSS VDD PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PB0 PB1 PB2 PB10 PB11 VCAP_1 VSS VDD V CAP increased to 4.7 μf ESR between 0.1 ohm and 0.2 ohm Not compatible STM32F732xx pins with either STM32F4x1 or STM32F405/F415 or both VSS VDD MSv50786V1 18/201 DS12536 Rev 1

19 STM32F730x8 Description 2.2 STM32F730x8 LQFP144 packages: Figure 3. Compatible board design for LQFP144 package STM32F4xxx STM32F7x5xx, STM32F7x6xx, STM32F7x7xx 93 PG8 92 PG7 91 PG6 90 PG5 89 PG VDD PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 STM32F730x8 93 PG8 92 PG5 91 PG4 90 PG3 89 PG VDD PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 VDD12OTGHS OTG_HS_REXT PB13 PB12 PG6, PG7 removed on the STM32F730x8 Not compatible pins MSv50787V1 Figure 4 shows the general block diagram of the device family. DS12536 Rev 1 19/201 49

20 Description STM32F730x8 Figure 4. STM32F730x8 block diagram JTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO TRACECK TRACED[3:0] DP, DM ULPI:CK, D[7:0], DIR, STP, NXT SCL/SDA, INT, ID, VBUS PA[15:0] PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] PH[15:0] PI[11:0] 168 AF JTAG & SW ETM FS PHY Arm CPU CortexM7 ICache 8KB 216MHz DCache 8KB USB HS PHY PLL GPDMA2 GPDMA1 LDO BGR USB OTG HS LDO GPIO PORT A GPIO PORT B GPIO PORT C GPIO PORT D GPIO PORT E GPIO PORT F GPIO PORT G GPIO PORT H GPIO PORT I EXT IT. WKUP MPU FPU NVIC DTCM ICTM AXIM AHBP AHBS PLL1 PLL2 DMA/ FIFO 8 Streams FIFO 8 Streams FIFO AHB2AXI AHB BUSMATRIX AHB busmatrix 11S8M 8S7M DTCM RAM 64KB ITCM RAM 16KB ACCEL/ CACHE AHB1 216 MHz SRAM1 176KB SRAM2 16KB AHB2 216 MHz QuadSPI FLASH 64KB EXT MEM CTL (FMC) SRAM, SDRAM, NORFlash, NANDFlash, SDRAM RCC Reset M & control GT FCLK HCLK APBP2CLK APBP1CLK AHB2PCLK AHB1PCLK RC HS RC LS PLL1+PLL2+PLL3 POR reset Int VDD12 LS LS FIFO FIFO PWRCTRL SUPPLY SUPERVISION POR/PDR BOR BBgen + POWER MNGT VOLT. REG 3.3V TO 1.2V Standby interface RNG USB OTG FS XTAL OSC 4 16MHz XTAL 32 khz RTC AWU Backup register 4 KB BKPRAM DP DM SCL, SDA, INT, ID, VBUS CLK, NE [3:0], A[23:0], D[31:0], NOEN, NWEN, NBL[3:0], SDCLKE[1:0] SDNE[1:0], SDNWE, NL NRAS, NCAS, NADV NWAIT, INTN CLK, CS,D[7:0] VDDA, VSSA NRESET WKUP[4:0] VDDMMC33 = 3.0 to 3.6V VDDUSB33 = 3.0 to 3.6 V VDD = 1.8 to 3.6 V VSS VCAP1 OSC_IN OSC_OUT VBAT = 1.8 to 3.6 V OSC32_IN OSC32_OUT RTC_TS RTC_TAMPx RTC_OUT D[7:0] CMD, CK as AF D[7:0] CMD, CK as AF 4 compl. chan. (TIM1_CH1[1:4]N), 4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF 4 compl. chan.(tim8_ch1[1:4]n), 4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF 2 channels as AF 1 channel as AF SDMMC1 SDMMC2 TIM1 / PWM TIM8 / PWM TIM9 TIM10 FIFO FIFO 16b 16b 16b 16b GPDMA2 AHB/APB2 AHB/ APB1 GPDMA1 TIM2 TIM3 TIM4 TIM5 TIM12 TIM13 32b 16b 16b 32b 16b 16b 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF 4 channels 2 channels as AF 1 channel as AF 1 channel as AF RX, TX, SCK, CTS, RTS as AF RX, TX, SCK, CTS, RTS as AF MOSI, MISO, SCK, NSS as AF MOSI, MISO, SCK, NSS as AF MOSI, MISO, SCK, NSS as AF SD, SCK, FS, MCLK as AF SD, SCK, FS, MCLK as AF ULPI:CK, D[7:0], DIR, STP, NXT SCL, SDA, INT, ID, VBUS TIM11 smcard irda USART1 smcard irda USART6 SPI1/I2S1 SPI4 SPI5 SAI1 SAI2 OTG HS PHY 16b FIFO FIFO APB2 108 MHz (max) SYSCFG WWDG LPTIM1 TIM6 TIM7 16b 16b 16b APB1 54 MHz APB1 (max) 0MHz 3 TIM14 USART2 USART3 UART4 UART5 UART7 UART8 SPI2/I2S2 SPI3/I2S3 I2C1/SMBUS I2C2/SMBUS I2C3/SMBUS 16b smcard irda smcard irda Digital filter 1 channel as AF RX, TX, SCK CTS, RTS as AF RX, TX, SCK CTS, RTS as AF RX, TX as AF RX, TX as AF RX, TX as AF RX, TX as AF MOSI, MISO, SCK NSS as AF MOSI, MISO, SCK NSS as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF VDDREF_ADC 8 analog inputs common to the 3 ADCs 8 analog inputs common to the ADC1 & 2 8 analog inputs for ADC3 USAR T 2 M B p s Temperature sensor ADC1 ADC2 ADC3 DAC1 DAC2 ITF bxcan1 FIFO TX, RX DAC1 as AF DAC2 as AF MSv50788V1 1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 20/201 DS12536 Rev 1

21 STM32F730x8 Functional overview 3 Functional overview 3.1 Arm Cortex M7 with FPU The Arm Cortex M7 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a lowcost platform that meets the needs of MCU implementation, with a reduced pin count and lowpower consumption, while delivering outstanding computational performance and low interrupt latency. Note: The Cortex M7 processor is a highly efficient highperformance featuring: Sixstage dualissue pipeline Dynamic branch prediction Harvard caches (8 Kbytes of Icache and 8 Kbytes of Dcache) 64bit AXI4 interface 64bit ITCM interface 2x32bit DTCM interfaces The processor supports the following memory interfaces: Tightly Coupled Memory (TCM) interface. Harvard instruction and data caches and AXI master (AXIM) interface. Dedicated lowlatency AHBLite peripheral (AHBP) interface. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. It supports single precision FPU (floating point unit), speeds up software development by using metalanguage development tools, while avoiding saturation. Figure 4 shows the general block diagram of the STM32F730x8 family. Cortex M7 with FPU core is binary compatible with the Cortex M4 core. 3.2 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DS12536 Rev 1 21/201 49

22 Functional overview STM32F730x8 3.3 Embedded Flash memory The STM32F730x8 devices embed a Flash memory of 64 Kbytes available for storing programs and data. The flexible protections can be configured thanks to option bytes: Readout protection (RDP) to protect the whole memory. Three levels are available: Level 0: no readout protection Level 1: No access (read, erase, program) to the Flash memory or backup SRAM can be performed while the debug feature is connected or while booting from RAM or system memory bootloader Level 2: debug/chip read protection disabled. Write protection (WRP): the protected area is protected against erasing and programming. Proprietary code readout protection (PCROP): Flash memory user sectors (0 to 1) can be protected against Dbus read accesses by using the proprietary readout protection (PCROP). The protected area is executeonly. 3.4 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRCbased techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.5 Embedded SRAM All the devices feature: System SRAM up to 256 Kbytes: SRAM1 on AHB bus Matrix: 176 Kbytes SRAM2 on AHB bus Matrix: 16 Kbytes DTCMRAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for critical realtime data. Instruction RAM (ITCMRAM) 16 Kbytes: It is mapped on TCM interface and reserved only for CPU Execution/Instruction useful for critical realtime routines. The Data TCM RAM is accessible by the GPDMAs and peripheral DMAs through the specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at CPU clock speed with 0 wait states. 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 22/201 DS12536 Rev 1

23 STM32F730x8 Functional overview 3.6 AXIAHB bus matrix The STM32F730x8 system architecture is based on 2 subsystems: An AXI to multi AHB bridge converting AXI4 protocol to AHBLite protocol: 3x AXI to 32bit AHB bridges connected to AHB bus matrix 1x AXI to 64bit AHB bridge connected to the embedded Flash memory A multiahb BusMatrix The 32bit multiahb bus matrix interconnects all the masters (CPU, DMAs, USB HS) and the slaves (Flash memory, RAM, FMC, QuadSPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several highspeed peripherals work simultaneously. Figure 5. STM32F730x8 AXIAHB bus matrix architecture (1) DTCM ITCM AHBS Arm CortexM7 GP DMA1 GP DMA2 USB OTG HS 8KB I/D Cache AXIM AHBP DMA_PI DMA_MEM1 DMA_MEM2 DMA_P2 USB_HS_M DTCM RAM 64KB ITCM RAM 16KB AXI to multiahb ITCM 64bit AHB ART FLASH 64KB 64bit BuS Matrix SRAM1 176KB SRAM2 16KB AHB Periph1 AHB periph2 FMC external MemCtl QuadSPI APB1 APB2 32bit Bus Matrix S MSv50789V1 1. The above figure has large wires for 64bits bus and thin wires for 32bits bus. DS12536 Rev 1 23/201 49

24 Functional overview STM32F730x8 3.7 DMA controller (DMA) The devices feature two generalpurpose dualport DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memorytomemory, peripheraltomemory and memorytoperipheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support a circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. The configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI and I 2 S I 2 C USART Generalpurpose, basic and advancedcontrol timers TIMx DAC SDMMC ADC SAI QuadSPI 24/201 DS12536 Rev 1

25 STM32F730x8 Functional overview 3.8 Flexible memory controller (FMC) The Flexible memory controller (FMC) includes three memory controllers: The NOR/PSRAM memory controller The NAND/memory controller The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller The main features of the FMC controller are the following: Interface with staticmemory mapped devices including: Static random access memory (SRAM) NOR Flash memory/onenand Flash memory PSRAM (4 memory banks) NAND Flash memory with ECC hardware to check up to 8 Kbytes of data Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories 8, 16, 32bit data bus width Independent Chip Select control for each memory bank Independent configuration for each memory bank Write FIFO Read FIFO for SDRAM controller The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is HCLK/2 LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.9 QuadSPI memory interface (QUADSPI) All the devices embed a QuadSPI memory interface, which is a specialized communication interface targetting Single, Dual or QuadSPI Flash memories. It can work in: Direct mode through registers External Flash status register polling mode Memory mapped mode. Up to 256 Mbytes of external Flash are memory mapped, supporting 8, 16 and 32bit access. The code execution is supported. The opcode and the frame format are fully programmable. The communication can be either in Single Data Rate or Dual Data Rate. DS12536 Rev 1 25/201 49