Embedded Power Supply Controller

Transcription

1 Embedded Power Supply Controller Amrish Singh 1, Prof. A. P. Mankodia 2 1 PG EC Student: U.V. Patel College of Engineering, Mehsana, Gujarat, India 2 Assistant professor, EC: U.V. Patel College of Engineering, Mehsana, Gujarat, India Abstract Small level of power supply controller (PSC) using an embedded system is planned that will control the parameters, monitor their status and protect the power supply under the fault conditions during the operation. Field Programmable Gate Array (FPGA) with soft processor will be used to develop the PSC. FPGA allows the fast signal manipulation and decision making (Protection) and the soft processor that is developed on the FPGA allows the control and acquisition through communication protocol. Discrete components (ADC, DAC, Comparators) are used to allow the analog signals to interface to digital circuits and vice versa. Basically the GUI running on the PC will send the control command to FPGA through processor and FPGA will than control the power supply and send the status of the signals back to the PC through processor. For the fast protection the FPGA monitor the signals against the safe limit and stop the power supply under fault. Keywords- Field programmable gate arrays (FPGA), Power supply controller (PSC)), Analog to digital converter (ADC), Digital to analog converter (DAC), Graphical user interface (GUI), Personnel computer (PC). I. INTRODUCTION Embedded systems are designed for the specific function within the larger system. It has the processing circuit like Microprocessor, DSP and FPGA that allows the data communication very easily. The characteristic of the embedded system to handle the particular task allows the design engineer to reduce the size and cost of the system and at the same time also make the system more reliable. Here the custom make engineering design of the Power supply embedded controller is planned as shown in the figure. Embedded controller will be specific to the single power supply that will locally perform the control, monitor and protection of the power supply. A. Block diagram of power supply controller The controller is modular having following modules: Figure.1 Block diagram for control, monitor and protection of power supply parameters. Power supply module derives the DC supply required by the modules and controller from 230V A.C.Input module monitor the power supply parameters (voltage, current) and send the information in the digital to the controller module. Output module receives the digital information of the Control parameter from the controller and that controls the power supply parameters (voltage, current). Controller Module communicate the power supply parameter from input and output module to the remote GUI through communication protocols (Ethernet, RS- 232).So the engineering design of the various modules, application development of remote graphical user interface and integrated functional testing is the task of the project. B. Project execution Since the concept is new and custom make the figure shows how the project is been executed step-by step. Figure.2 Methods for project execution 223

2 The first step is to prove the concept with prototype design. So the whole concept is designed using the Spartan-3an FPGA starter kit [6] and it is tested with dummy signal. Also application program for remote operation is developed in Lab View software. In parallel to prototype design the circuit design for industrial system is carried out. The whole system is then developed considering the industrial method and then tested with actual power supply of ECH&CD system. II. PROTOTYPE DESIGN OF INPUT MODULE USING SPARTAN 3 AN KIT Spartan-3an starter kit is used to perform prototype design. As shown below the kit has 14-bit ADC (analog to digital converter) that will act as input module for power supply parameters monitoring. Figure.5 SPI Timing When Communicating with preamplifier [6] B. SPI Communication Interface for ADC (analog to digital converter) When the AD_CONV signal goes high, the ADC simultaneously samples both analog channels. The results of this conversion are not presented until the next time AD_CONV is asserted, a latency of one sample. The maximum sample rate is approximately 1.5MHz. The ADC presents the digital representation of the sampled analog values as a 14-bit, two s complement binary value. Figure.3 input module on SPARTAN 3AN kit [6] A. SPI(serial to peripheral interface) Communication Interface for preamplifier The gain for each amplifier is sent as an eight-bit command word, consisting of two four-bit fields. The most-significant bit, B3, is sent first. Figure.4 SPI Control Interface for preamplifier [6] The SPI bus communication with the amplifier is shown in fig.4. Which starts on the falling edge of AMP_CS and the data is actually read on SPI_MOSI signal on the rising edge of the serial clock SPI_SCK signal just after 30 ns, after the data is read then then actual data is write on AMP_MOSI signal on the falling edge of the SPI_SCK signal. 224 C. Equations Figure.6 SPI Timing When Communicating with preamplifier [6] The analog representation of the output is given by: D [13:0] = 8192XGAINX (VIN 1.65)/1.25 (1) D [13:0]: 14 bit representation of analog input. GAIN: Gain of preamplifier. 1.65V: Reference voltage for each ADC. III. PROTOTYPE DESIGN OF OUTPUT MODULE USING SPARTAN 3AN KIT The DAC device is a Linear Technology LTC2624 quad DAC with 12-bit unsigned resolution. The four outputs from the DAC shown in Figure 7

3 The LTC2624 DAC transmits its data on the DAC_OUT signal on the falling edge of SPI_SCK. The FPGA captures this data on the next rising SPI_SCK edge. The High-going edge starts the actual digital-toanalog conversion process within the DAC. C. Equations VOUT= VEREFERNCEX D[11:0]/4096 (2) VOUT=12 bit analog output voltage representation Figure.7 SPI Timing When Communicating with preamplifier [6] A. SPI (serial to peripherel interface) for DAC(digital to analog converter) FPGA uses a Serial Peripheral Interface (SPI) to communicate digital values to each of the four DAC channels. A bus master the FPGA in this example drives the bus clock signal (SPI_SCK) and transmits serial data (SPI_MOSI) to the selected bus slave the DAC in this example. At the same time, the bus slave provides serial data (SPI_MISO) back to the bus master. VREFERNCE: Reference voltage available for each DAC. IV. EXPERIMENTAL RESULTS Figure.10 Test bench result of preamplifier and I complete clock cycle is 400ns Figure.8 Digital-to-Analog Connection Schematics [6] B. SPI Communication Details After driving the DAC_CS slave select signal Low, the FPGA transmits data on the SPI_MOSI signal, MSB first. Figure.9 SPI Communication Details [6] The LTC2624 captures input data (SPI_MOSI) on the rising edge of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge. Figure.11 result of preamplifier on CRO and the one clock cycle is also 400ns 225

4 Figure.12 ADC SPI Control timing with timing between the 2 rising edges of clock is 480 ns on Xilinx software Figure.14 Test bench waveform of DAC Figure.15 DAC SPI Control timing on CRO Figure.13 ADC SPI Control timing on CRO 226

5 V. CONCLUSION Since embedded power supply controller is used as a localized solution for individual power supply so it provide the customized approach to control number of power supply by designing specific controller as per the power supplies. Embedded power supply controller also reduces number of cables and connection required for controlling the power supplies and also reduction in size and cost of the system by improving the reliability and performance. Hence we came to conclude that as an option by following the above features merits and desired results from the embedded power supply controller which are same by using COTS(commercially available off the shelf system) systems using PLC and PXI we can use embedded power supply controller. Acknowledgement I would like to thank all who have been instrumental in my growth as engineering professional.my great obligations remain towards Prof. Anand.P.Mankodia, for being a constant source of inspiration, and acting as a guide, helping me throughout my stint in the college, participating actively in the report development process, providing me with all the facilities, and who has done much beyond expectations to bring out the best in me. REFERENCES Journal Paper References: [1] Amine Mezghani and Josef A. Nossek. How to choose the ADC resolution for short range low power communication, publication year 2010 by IEEE conference publication [2] IEEE, IEEE Standard VHDL Language Reference Manual (IEEE Srd ), Institute of Electrical and Electronics Engineers, Book References: [3] J. Bhasker, A VHDL Primer, 3rd Edition, Pearson Prentice Hall, New Delhi, 2006 [4] P. J. Ashen den, The Designer s Guide to VHDL, 2nd ed., Morgan Kaufmann, 2001 [5] J. 0. Hamblen et al., Rapid Prototyping of Digital Systems: Quartus@ II Edition, Springer, Datasheet Reference [6] Spartan-3A/3AN FPGA Starter Kit Board User Guide/UG334 (v1.1) June 19, 2008 [7] Complete, Quad, 12-/14-/16-Bit, Serial Input, nipolar/bipolar Voltage Output DACs 5754R [8] Ultra low Distortion, Ultra low Noise Op Amp 2.5 V/3.0 V High Precision Reference AD780 AR [9] 5V to 3.3 V voltage converter IC [10] 2-Channel, Software-Selectable, True Bipolar Input,1 MSPS, 12- Bit Plus Sign ADC