FPGA Algorithm Development Using a Graphical Environment

Transcription

1 FPGA Algorithm Development Using a Graphical Environment GRETINA Electronics Working Group July 25, 2004 RIS Corp. R. Todd S. Pauly* ORNL Physics Division J. Pavan D. C. Radford July

2 Overview Motivation Process Design Environment Graphical Design Methodology Evaluation Platform Dual MCA Real-Time Demonstration July

3 Motivation Reduce extensive VHDL coding requirements Produce immediate feedback with simulation Desktop (high-level) development environment vs. hardware-level testing Create re-usable library components Applicable to all FPGA programming in system July

4 Process Matlab and Simulink from The Mathworks System Generator from Xilinx Block diagram approach for algorithm and system design Generates VHDL code optimized for Xilinx FPGAs. Tested on several platforms Evaluation boards Dual MCA LBNL GRETA 8-channel digitizer July

5 Design Environment FPGA functions provided by System Generator counter, relational, memory, shift, multiply, delay, Simulink blocks along with Xilinx In/Out blocks FPGA pinout, simulation input data System Generator outputs VHDL targets specific Xilinx FPGA, sets global clock Fixed point functions Can use a specified precision (e.g. 14-bit), or determines precision from driving blocks Black box function provided to allow user VHDL functions July

6 Design Environment July

7 Graphical Design Methodology Draw block diagram Simulate design Modify diagram Generate VHDL Implement into FPGA Create bit file Program FPGA July

8 First Evaluation Platform ADC Evaluation Board Analog Devices AD bits, 105 MSPS 14 ADC 12 FPGA 14 DAC DAC Evaluation Board Texas Instruments DAC bits, 125 MSPS Dual DAC FPGA Evaluation Board Xilinx Spartan IIE 100 MHz clock July

9 Results Trapezoidal Simulation Waveforms July

10 Results Evaluation Platform Waveforms July

11 Results VHDL Comparison Same FPGA resource usage for System Generator vs. Hand-coded VHDL Module Hand Coded VHDL System Generator VHDL Name Frequency Period (ns) (MHz) Slices RAMB 16 IOB Frequency Period (ns) (MHz) Slice s RAMB1 6 IOB GauFilt GauFilt TapDela y TrapzFil July

12 Graphical Approach Benefits Simulation provides immediate feedback scope view of signals A variety of Matlab and Simulink functions can be used to analyze results or provide stimulus to the algorithm Extensive knowledge of VHDL not required System Generator will produce VHDL for the targeted Xilinx FPGA Makes extensive use of Xilinx cores including Virtex hardware multipliers Makes use of synchronous design with one system clock Subsystems and custom libraries permit design re-use Drag and drop of Xilinx library functions Drag and drop of User library functions Drag and drop of Simulink functions for creation of stimulus (model a detector with noise for example) July

13 Evaluation Platform: LBNL GRETA 8-channel Board July

14 Evaluation Platform: LBNL GRETA 8-channel Board Uses VHDL wrapper Re-use I/O Pads from LBNL code Structure instantiating one channel multiple times Filter LE Discriminator PZ correction CFD Programmable Parameters for each channel PZ, rise, dwell, noise threshold, CFD Packetizer to gather data and send to FIFO VME Interface July

15 GRETA ADC Filter July

16 Simulation Scope Traces LE Discriminator CFD Output CFD1 for time interpolation Trapezoidal Output July

17 Event Detector July

18 Trapezoidal Shaper July

19 PZ Corrector July

20 Local Decoder Sets: Rise Time Apex Time Pole Zero Threshold CFD July

21 Shaping Filters Cusp Cusp_FIR Polynomial Cusp Quad Cusp Differentiator Gaussian Fast Gaussian Gaussian_BRAM Gaussian_FIR Gaussian_FSR Gaussian_SR Trapezoid Trapezoid_BRAM Trapezoid_BRAM_fixed Trapezoid_FIR Trapezoid_SR Triangle_FIR July

22 Dual MCA July

23 Dual MCA Scope Photo of Input Pulse with Shaped Output July

24 Co-60 Spectra using Dual MCA RIS Digitizer 5 minutes Co Counts Channel Number All Shaping and Histogram implemented inside FPGA MATLAB & Simulink Tools used exclusively July

25 Real-Time Demonstration July

26 Summary Graphical Environment Tools developed under DOE STTR contract for GRETA VHDL expertise not required Immediate feedback from simulation Useful Library developed: drag & drop Widely applicable beyond GRETA digitizer e.g. trigger system, BaF 2 detectors, Working Dual MCA July