MicroBench MB-500A. Live Logic Logic source pattern generator Logic analyzer Arbitrary waveform generator Protocol interactive test

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1 Providing tools for Embedded Engineers Digital Designers MicroBench MB-500A a complete digital tool set Technical Data Five test tools in one compact, affordable instrument: Live Logic Logic source pattern generator Logic analyzer Arbitrary waveform generator Protocol interactive test (PC and mouse not included) Anewin, MicroBench, and Live Logic are trademarks of Anewin, LLC. Anewin reserves the right to change any product offering or specification at any time without notice.

2 MB-500: a complete digital tool set 2 of 5 System Specifications System Event Inputs and Outputs PC Integration System Configuration Live Logic, Logic Analyzer, Logic Source, Waveform Source, Protocol A, Protocol B, System button USB interface, PC Application and front panel control Save/Restore current configuration and data User Scripts (Option) System control language,.net interface Power Data File Formats Timebase Accuracy Input Over Voltage Protection Output Protection Physical dimensions without stand Physical dimensions with stand Weight, MB-500 with stand 1A, 7.5W Human readable text files, CSV spreadsheet compatible format or plain text ±100 ppm ±15V max on logic and protocol inputs, ±30V max on Live Logic 10X probe tip, Protected against short to ground or short to 0-5V power supply 13cm x 17cm x 6cm (5.1in x 6.7in x 2.4in) 15cm x 17cm x 16cm (5.9in x 6.7in x 6.3in) 1.2kg (2.6lb) System Requirements Operating System Windows 10, 8.1, 7 Processor Memory Free disk space 3GHz 1GB RAM 10MB Live Logic Specifications Channels 2 Input Range Input Impedance Sample Rate Threshold Range and 0-16V (10X probe tip) 10MΩ 400MS/s 2.5ns Max Event Samples 2048 Max Capture Time Probe Protocol Decode Acquisition Modes 0-10V, 50mV resolution >90 minutes 10x passive probe, BNC instrument connection I2C, SPI, RS-232, LIN Single, Continuous Live Logic Voltmeter Specifications Inputs 2 Input Range 0-16V (10X probe tip) 100mV Accuracy ±5 % Probe Live Logic 10X probes

3 MB-500: a complete digital tool set 3 of 5 Logic Analyzer Specifications Channels 9 Input Range 0-5V Input Impedance Sample Rate >1MΩ 100MS/s 10ns Threshold Range 0-5V Threshold Max Event Samples 2048 Max Capture Time Acquisition Modes Protocol Decode Trigger 10 bits (4.88mV) >45 minutes Single, Continuous I2C, SPI, RS level sequence, including pattern match, stable duration, or System Event Logic Source Specifications Channels 9 Logic Low Level (V OL) 0-4.5V (V OL < V OH ) Logic High Level (V OH) 0-4.5V (V OH > V OL ) Output Output Accuracy Data Rate 4.88mV 50mV typical 100MS/s 10ns Max Vectors 1020 Vector Duration Max Non-repeating Waveform Generation Modes Waveform Sequence Control Commands 30ns-40ms >40 seconds Single, On Event, Continuous Goto, loop, wait for event, jump if event, jump if not event, stop, generate output event

4 MB-500: a complete digital tool set 4 of 5 Waveform Source Specifications Channels Output Range 0-5V Data Rate Max Vectors 1020 Single Vector Duration Output Generation Modes Max Non-repeating Waveform Duration Custom Waveform Sequence Control commands Slew Rate Generated Waveforms Battery Emulation Types Max Output Current Capacitive Load Single output on red binding post, ground reference on black binding post 250kS/s, or 1MS/s in fast mode 4µs, or 200ns in fast mode 8µs-16s, or 1µs-0.8s in fast mode 10 bits (4.88mV) Single, On Event, Continuous >4 hours Goto, loop, wait for event, jump if event, jump if not event, stop, generate output event 1V/µs typical Sine, Triangle, Pulse, RC (exponential), battery discharge, DC (power supply) Alkaline, Ni-Cd, Li-ion, Ni-MH 100mA, full output range into 50Ω load Output stable into large capacitive loads with reduced slew rate Protocol Device Specifications Devices Signal Range 0-5V I2C, SPI, or Trigger I/O, each with specific protocol probe I2C Protocol Master/Slave Device Modes Signals Max Transactions 64 Bytes per transaction SDA Input Logic Threshold Master Commands Master Clock Rate Master functions Slave Capture Modes Slave Address Slave Read Data Slave Functions Master or Slave SCK, SDA (open collector, bidirectional), GND 1-8 Start, stop, read, write, wait, wait for event, send event, goto, exit 100KHz, 400KHz Stop on NACK, stop on timeout Continuous, Single (stop when memory full), Until Event X (respond to all addresses or respond to selected address User settable 1-8 bytes for all reads Stop on timeout, show/hide start-stop

5 MB-500: a complete digital tool set 5 of 5 SPI Protocol Master/Slave Device Modes Signals Max Transactions 128 Message Length commands, show/hide restart commands Master Single-Step, Master On Event, Slave SDI, SDO, master SCK & SEL, slave SCK & SEL 8, 16, 24, 32 bits SDO Logic Low Level 0-4.4V (V OL < V OH ) SDO Logic High Level V SDO Output 4.88mV SDO Output Accuracy 50mV typical SDI Logic Threshold Trigger Master Clock Rates Single level with don't care bits (X) 10KHz-25MHz Sequence Commands Goto 0, jump to sequence, stop, generate event Master Functions Slave Functions Max Slave Clock Rate 25MHz MSB/LSB first, clock polarity, SEL polarity, skip jump on trigger MSB/LSB first, clock polarity, SEL enable, SEL polarity, skip jump on trigger Trigger I/O Protocol Outputs 3, each from any of 7 System Events Output Logic Levels Event Output Functions Inputs Input Threshold Event A Functions Event B Functions Settable Logic High and Low levels, 0-4.5V Positive logic or Invert 3, each can source Protocol A or B System Events Select input signal Logical combination of 3 event input signals