CS61C : Machine Structures

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Randall Fitzgerald
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1 CS 61C L24 VM II (1) ist.eecs.berkele.edu/~cs61c/su5 CS61C : Machie Structures Lecture #24: VM II Address Mappig: Virtual Address: VPN offset Ad Carle idex ito page table located i phsical memor CS 61C L24 VM II (2) V A.R. P. P. A. Val Access Phsical -id Rights Address. PPN offset Phsical Memor Address A page table: mappig fuctio There are several differet was, all up to the operatig sstem, to keep this data aroud. Each process ruig i the operatig sstem has its ow page table - Historicall, OS chages page tables b chagig cotets of Base Register Requiremets revisited Remember the motivatio for VM: Sharig memor with protectio Differet phsical pages ca be allocated to differet processes (sharig) A process ca ol touch pages i its ow page table (protectio) Separate address spaces Sice programs work ol with virtual addresses, differet programs ca have differet data/code at the same address! CS 61C L24 VM II (3) CS 61C L24 VM II (4) Etr (PTE) Format Cotais either Phsical Number or idicatio ot i Mai Memor OS maps to disk if Not Valid (V = ) V A.R. P. P.N. Val Access Phsical -id Rights P.T.E. Number V A.R. P. P. N. If valid, also check if have permissio to use page: Access Rights (A.R.) ma be Read Ol, Read/Write, Executable CS 61C L24 VM II (5) Pagig/Virtual Memor Multiple Processes User A: Virtual Memor CS 61C L24 VM II (6) 64 MB A Phsical Memor B User B: Virtual Memor

2 CS 61C L24 VM II (7) Comparig the 2 levels of hierarch Cache Versio Virtual Memor vers. or Lie Miss Fault Size: 32-64B Size: 4K-8KB Placemet: Full Associative Direct Mapped, N-wa Set Associative Replacemet: LRU or Radom Least Recetl Used (LRU) Write Thru or Back Write Back Notes o OS must reserve Swap Space o disk for each process To grow a process, ask Operatig Sstem If uused pages, OS uses them first If ot, OS swaps some old pages to disk (Least Recetl Used to pick pages to swap) Will add details, but is essece of Virtual Memor CS 61C L24 VM II (8) VM Problems ad Solutios TLB d s Virtual Memor Problem #1 Map ever address 1 idirectio via i memor per virtual address 1 virtual memor accesses = 2 phsical memor accesses SLOW! Observatio: sice localit i pages of data, there must be localit i virtual address traslatios of those pages Sice small is fast, wh ot use a small cache of virtual to phsical address traslatios to make traslatio fast? For historical reasos, cache is called a Traslatio Lookaside Buffer, or TLB CS 61C L24 VM II (9) CS 61C L24 VM II (1) Traslatio Look-Aside Buffers (TLBs) TLBs usuall small, tpicall etries Like a other cache, the TLB ca be direct mapped, set associative, or full associative Processor CS 61C L24 VM II (11) VA hit PA miss TLB Mai Cache Lookup Memor miss hit Traslatio data O TLB miss, get page table etr from mai memor Tpical TLB Format Virtual Phsical Dirt Ref Valid Access Address Address Rights TLB just a cache o the page table mappigs TLB access time comparable to cache (much less tha mai memor access time) Dirt: sice use write back, eed to kow whether or ot to write page to disk whe replaced Ref: Used to help calculate LRU o replacemet Cleared b OS periodicall, the checked to see if page was refereced CS 61C L24 VM II (12)

3 CS 61C L24 VM II (13) What if ot i TLB? Optio 1: Hardware checks page table ad loads ew Etr ito TLB Optio 2: Hardware traps to OS, up to OS to decide what to do MIPS follows Optio 2: Hardware kows othig about page table What if the data is o disk? We load the page off the disk ito a free block of memor, usig a DMA (Direct Memor Access ver fast!) trasfer Meatime we switch to some other process waitig to be ru Whe the DMA is complete, we get a iterrupt ad update the process's page table So whe we switch back to the task, the desired data will be i memor CS 61C L24 VM II (14) What if we do't have eough memor? Questio We choose some other page belogig to a program ad trasfer it oto the disk if it is dirt If clea (disk cop is up-to-date), just overwrite that data i memor We chose the page to evict based o replacemet polic (e.g., LRU) Ad update that program's page table to reflect the fact that its memor moved somewhere else If cotiuousl swap betwee disk ad memor, called Thrashig CS 61C L24 VM II (15) Wh is the TLB so small et so effective? Because each etr correspods to pagesize # of addresses Wh does the TLB tpicall have high associativit? What is the associativit of VA PA mappigs? Because the miss pealt domiates the AMAT for VM. High associativit lower miss rates. CS 61C L24 VM II (16) - VPN PPN mappigs are full associative Virtual Memor Problem #1 Recap Slow: Ever memor access requires: - 1 access to PT to get VPN->PPN traslatio - 1 access to MEM to get data at PA Solutio: Cache the - Make commo case fast - PT cache called TLB block size is just 1 VPN->PN mappig TLB associativit Virtual Memor Problem #2 too big! 4GB Virtual Memor 1 KB page ~ 4 millio Etries 16 MB just for for 1 process, 8 processes 256 MB for s! Spatial Localit to the rescue Each page is 4 KB, lots of earb refereces But large page size wastes resources s i program s workig set will exhibit temporal ad spatial localit. So CS 61C L24 VM II (17) CS 61C L24 VM II (18)

4 CS 61C L24 VM II (19) Solutios the itself! Works, but must be careful with everedig page faults Pi some PT pages to memor 2-level page table Solutios tradeoff i-memor PT size for slower TLB miss Make TLB large eough, highl associative so rarel miss o address traslatio CS 162 will go over more optios ad i greater depth Shrik : Sigle Number Offset 2 bits 12 bits Multilevel Super No. Number Offset 1 bits 1 bits 12 bits Ol have secod level page table for valid etries of super level page table Book Exercises explore exact space savigs CS 61C L24 VM II (2) Admiistrivia Proj 3 Due Frida Proj 4 Out Soo 2-level 2d Level s Super Virtual Memor 64 MB Phsical Memor HW 8? Probabl, but it will be short CS 61C L24 VM II (21) CS 61C L24 VM II (22) Three Advatages of Virtual Memor 1) Traslatio: Program ca be give cosistet view of memor, eve though phsical memor is scrambled (illusio of cotiguous memor) All programs startig at same set address Illusio of ~ ifiite memor (2 32 or 2 64 btes) Makes multiple processes reasoable Ol the most importat part of program ( Workig Set ) must be i phsical memor Cotiguous structures (like stacks) use ol as much phsical memor as ecessar et still grow later CS 61C L24 VM II (23) Cache, Proc ad VM i IF (A Fie Slide) Fetch PC EXE; PC PC+4 tlb hit? VPN->PPN Map Cache hit? Load ito IR Trap os Mem hit? pt hit? XXX Free mem? Cache full? Write polic? Victim to disk wb wt WB if dirt Load ew page Update PT Evict victim Load block CS 61C L24 VM II (24)

5 CS 61C L24 VM II (25) Cache, Proc ad VM i IF (A Fie Slide) Fetch PC EXE; PC PC+4 tlb hit? VPN->PPN Map Cache hit? Load ito IR Trap os Mem hit? pt hit? XXX Free mem? Cache full? Write polic? Victim to disk wb wt WB if dirt Load ew page Update PT Evict victim Load block Where is the page fault? $&VM Review: 4 Qs for a Mem. Hierarch Q1: Where ca a block be placed i the upper level? ( placemet) Q2: How is a block foud if it is i the upper level? ( idetificatio) Q3: Which block should be replaced o a miss? ( replacemet) Q4: What happes o a write? (Write strateg) CS 61C L24 VM II (26) Q1: Where block placed i upper level? 12 placed i 8 block cache: Full associative, direct mapped, 2-wa set associative S.A. Mappig = Number Mod Number Sets o Full associative: block 12 ca go awhere o. CS 61C L24 VM II (27) o Direct mapped: block 12 ca go ol ito block 4 (12 mod 8) -frame address o Set Set Set Set Set associative: block 12 ca go awhere i set (12 mod 4) Q2: How is a block foud i upper level? Direct idexig (usig idex ad block offset), tag compares, or combiatio Icreasig associativit shriks idex, expads tag CS 61C L24 VM II (28) Tag Address Idex Set Select offset Data Select Q3: Which block replaced o a miss? Eas for Direct Mapped Set Associative or Full Associative: Radom LRU (Least Recetl Used) Miss Rates Associativit:2-wa 4-wa 8-wa Size LRU Ra LRU Ra LRU Ra 16 KB 5.2% 5.7% 4.7% 5.3% 4.4% 5.% 64 KB 1.9% 2.% 1.5% 1.7% 1.4% 1.5% 256 KB 1.15% 1.17% 1.13% 1.13% 1.12% 1.12% CS 61C L24 VM II (29) Q4: What to do o a write hit? Write-through update the word i cache block ad correspodig word i memor Write-back update word i cache block allow memor word to be stale => add dirt bit to each lie idicatig that memor be updated whe block is replaced => OS flushes cache before I/O!!! Performace trade-offs? WT: read misses caot result i writes WB: o writes of repeated writes CS 61C L24 VM II (3)

CMSC Computer Architecture Lecture 12: Virtual Memory. Prof. Yanjing Li University of Chicago

CMSC Computer Architecture Lecture 12: Virtual Memory. Prof. Yanjing Li University of Chicago CMSC 22200 Computer Architecture Lecture 12: Virtual Memory Prof. Yajig Li Uiversity of Chicago A System with Physical Memory Oly Examples: most Cray machies early PCs Memory early all embedded systems