73S1120F EMV Smart-Card Terminal Controller With Built-in Dual ISO-7816 Interface DATA SHEET NOVEMBER 2005 DESCRIPTION APPLICATIONS ADVANTAGES

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1 With Built-in Dual ISO-786 Interface NOVEMBER 00 DESCRIPTION The TERIDIAN Semiconductor Corporation 73S0F is a CMOS single chip dual ISO-786 smart-card terminal micro-controller that implements all the functions required to build a low-cost dual smart-card terminal, suitable for various applications including EMVCo compliant payment terminals. Its enhanced set of features supports several configurations allowing low component count and a fast design cycle. Based on an 80C core, it incorporates communication and man-machine interfaces. The TERIDIAN 73S0F device is applicable to either portable or host-connected applications. Embedded Flash memory makes the TERIDIAN 73S0F a complete system-on-chip suitable for both development and production phases. This data sheet presents the package and pin description, as well as the electrical features that are unique to the TERIDIAN 73S0F. It also presents a brief description of the architecture and of its embedded functions. Refer to the 73SxxF Hardware User s Guide for more detailed information about the microcontroller architecture, description of the registers, description of the different blocks that are common to the TERIDIAN 73SxxF smart card terminal controller family. APPLICATIONS Multiple smart card reader modules Point of sales & transaction terminals ADVANTAGES True System-on-Chip solution, with built-in communication interfaces and peripherals Compact solution, that requires only a few external components Embedded 64kB Flash and kb RAM are the largest memory size among 8-bit smart card reader controllers in the industry Software API (Application Programming Interface) includes the ready-to-use protocol layers for asynchronous cards Faster development time Time-to-Market Optional ready to use EMV-ready application Also refer to the TERIDIAN 73SxxF Software User s Guide for a complete description of the Application Programming Interface (API). Page: of 8 00 TERIDIAN Semiconductor Corporation Rev.0

2 FEATURES 80C core: clock-cycle / instruction CPU clocked up to 4MHz (with a MHz crystal) Memory: 64kB internal Flash (Program Memory) 8 Bytes Flash Info Memory Block Flash memory guaranteed for 0,000 erase-write cycles kb IRAM (internal RAM for registers) + 4kB internal XRAM (User Data Memory) Interface for external program / data memory Boot-ROM loader program allows both In-System- Programming and In-Application-Programming of the embedded flash (ISP and IAP modes) Flash PROM-programming mode ISP programming mode can be permanently disabled by protection fuses Oscillators: Single low-cost MHz crystal An Internal PLL provides all the necessary clocks to each block of the system Interrupts: Standard 80C -priority level structure 8 different sources of interrupt Power Down Modes: standard 80C Power Down and IDLE modes Timers: (3) Standard 80C timers T0, T and T () Built-in ISO-786 card interfaces: () Independent step-up converters generate VCC for the card (3V or V) Compliant with EMV 4.0 (EMV000) Activation/Deactivation sequencers Auxiliary I/O lines (C4-C8 signals) 4.kV ESD protection on all interface pins Communication with smart cards: ISO-786 UART 9600 to kbps (with MHz crystal) for protocols T=0, T= -Byte FIFO for transmit and receive Hardware support to manage additional external card interfaces Communication interfaces: Full-duplex serial interface (00 to kbps UART) I/Os: (7) Dedicated LCD I/Os (Control of any external HD44780 standard LCD driver) Can be also used as standard I/Os (8) User I/Os Operating Voltage:.7V to 3.6V Operating Temperature: 0 C to 8 C Package: 64 pin LQFP Software: Two-level Application Programming Interface (ANSI C-language libraries) T=0 T= and EMV-compliant smart card protocol layers Page: of 8 00 TERIDIAN Semiconductor Corporation Rev.0

3 FUNCTIONAL DIAGRAM SEC ISP_Program INT0 INT RESET VPC VNC VCC VCC 4kB XRAM + kb IRAM 8B IFB (Flash) 64kB Flash ROM Boot-Loader Access Control Ext. Memory Interface DC-to-DC Converters CCP CCN CCP CCN VCCIN VCCIN GND_RTN LCD_DAT(3:0) LCD_En LCD_RW LCD_RS 4 LCD I/Os 80 Core ISO-786 Driver and Sequencer ICC# VCC CLK RST IO DET_CARD USR(7:0) 8 I/Os Timer T0 Timer T Timer T ISO-786 UART PLL & Clock Circuitry ISO-786 Driver and Sequencer ICC# Interface for Ext. ICCs MHz Main Oscillator VCC CLK RST IO C4 C8 DET_CARD SCLK SIO SC4 SC8 OSCIN OSCOUT Serial UART 4 VPA VNA RX TX Page: 3 of 8 00 TERIDIAN Semiconductor Corporation Rev.0

4 Microcontroller The 73S0F core is an 8-bit 80C micro-controller, with embedded kb of RAM (data memory) and 64kB of flash (program memory). An additional Information Block Flash cell (8B IFB) is available for storage of device ID, serial number, firmware version etc. An embedded ROM boot-loader allows downloading of the flash memory (either program or IFB) through the serial port. This programming mode can be forced externally (In-System-Programming = ISP mode) or also can be called by the application (In-Application-Programming = IAP mode) through the Application Programming Interface. Security fuses allows the user to permanently disable the ISP mode. It allows the 73S0F, once programmed with an application, to run independently without possibility from the external world to re-download a non-authorized application. Other features include: The 73S0F has a main oscillator that requires a MHz crystal. Internal clock circuitry generates clock signals to the different blocks and to the CPU (that can be clocked at 6, or 4MHz). The 73S0F has the standard 80 -priority level interrupt structure, with 8 different interrupt sources: external interrupt (pin INT), 3 timer interrupts and smart-card interrupt. The 73S0F incorporates 3 timers, T0, T and T that can be clocked internally or externally by the respective input signals on the pins USR0, USR and USR. Standard 80 Power Down mode and IDLE mode are supported for power saving modes. The clock for each block and the DC-to-DC converter (VCC generator for the card) can be independently enabled or disabled by firmware to optimize power consumption. Management of the embedded card interface, peripherals and communication capabilities are controlled by means of dedicated registers in RAM. Management of the interrupts, of the power saving modes and of the clock circuitry is also controlled through registers. Page: 4 of 8 00 TERIDIAN Semiconductor Corporation Rev.0

5 ISO-786 Interfaces and UART The feature set of the TERIDIAN 73S0F includes two built-in smart-card interfaces, controlled by an ISO-786 compliant sequencer. Each built-in smart card interface has its own DC-DC converter, able to generate the card power supply, VCC=3V or V. The sequencer handles the activation / deactivation of the card signals. Each card interface includes an input for the card presence switch (programmable polarity) and auxiliary I/O lines for C4 / C8 signals. A hardware ISO-786 UART with a dedicated FIFO allows easy implementation of asynchronous card protocols T=0 and T=. This UART can be bypassed to allow a firmware UART to handle other protocols such as synchronous card protocols. Control and use of the ISO-786 UART is widely and easily configurable with dedicated registers located in XRAM. A 4-line interface enables the 73S0F to control additional external smart card (ICC) interfaces, typically for multiple-sam configurations. The ISO-786 UART can be shared between all the smart card interfaces (internal and external). Communication, Man-Machine Interface and I/Os The 73S0F has a standard 80 serial UART allows the 73S0F to communicate with any host or peripheral on a serial link, at a data transmission rate from 00 to kbps. Communication with a computer through RS3 can be easily implemented only using an external level shifter. 7 I/O lines are dedicated to control an external standard LCD driver, allowing a wide choice of LCDs to be controlled by the 73S0F, such as 7-wire, Hitachi-type HD Additional input/outputs feature 8 user I/Os. Page: of 8 00 TERIDIAN Semiconductor Corporation Rev.0

6 PIN DESCRIPTION Pin Name 64 LQFP # Pins Type Description Pin #, 8,, GND Digital ground 3, 4, 9,, 34 4 Supply VNA 3 GND Analog ground VPA Supply VPC,7 Supply Digital power..7v - 3.6V Must be greater than 3V when using the interface. \Each pin to be decoupled to with a 0.µF capacitor. Analog power..7v - 3.6V To be decoupled to VNA with a 0.µF capacitor. DC/DC Step-up Converter power (.7-3.6V). Each pin to be decoupled to VNC with one 0.µF and one 0µFcapacitor. VNC 44, 4 GND DC/DC Step-up Converter ground OSCIN 6 I MHz crystal input. Can drive clock in and leave OSCOUT unconnected OSCOUT 7 O MHz crystal output. Leave unconnected if not using a crystal CLK 6 O ICC Clock signal for interface CLK 43 O ICC Clock Signal for interface I/O 6 I/O ICC I/O Signal for interface I/O 4 I/O ICC I/O Signal for interface RST 60 O ICC RST Signal for interface RST 48 O ICC RST Signal for interface CCP 8 I/O Step-up Converter Capacitor Positive Node (0.68µF Low ESR) CCN 6 I/O Step-up Converter Capacitor Negative Node CCP 0 I/O Step-up Converter Capacitor Positive Node (0.68µF Low ESR) CCN I/O Step-up Converter Capacitor Negative Node VCCIN I VCC 9 O VCCIN 3 I VCC 49 O C4 47 I/O ICC C4 Signal for interface C8 46 I/O ICC C8 Signal for interface Card interface voltage supply for interface circuits take from VCC filter capacitor ICC VCC Signal for interface Must be decoupled to GND with a 6.8µF low-esr capacitor. Card interface voltage supply for interface circuits take from VCC filter capacitor ICC VCC Signal for interface Must be decoupled to GND with a 6.8µF low-esr capacitor. DET_CARD 36 I ICC presence contact input pin for interface. Programmable polarity (to be connected accordingly to the card presence switch with a pull-up / pull-down) DET_CARD 37 I ICC presence contact input pin for interface. Programmable polarity (to be connected accordingly to the card presence switch with a pull-up / pull-down) Digital security input that controls the internal protection fuse. SEC 4 I Active High. Internal pull-down allows NC for normal operation. When set, permanently deactivates the ISP programming mode. RESET 4 I 73S0F Reset. Active high Page: 6 of 8 00 TERIDIAN Semiconductor Corporation Rev.0

7 Pin Name 64 LQFP Pin # # Pins Type Description ISP_Program 3 I Forces internal Flash programming in ISP mode at reset. Active High. 0 = Indicates the user does not want to program the flash if checksum passes. Internal pull-down allows NC for normal operation TXD 7 O Transmit data - Serial output port from the 73SF serial UART RXD 8 I Receive data - Serial input port to the 73SF serial UART USR (7) 6 USR (6) 7 USR () 8 USR (4) 9 USR (3) 30 USR () 3 USR () 33 USR (0) 3 8 I/O User programmable I/O port. INT0 63 I External interrupt input pin INT I External interrupt input pin Reserved 64 I Set to ground NC 9,0 -- No connect pins. SIO 40 I/O Digital I/O line for external card interfaces. Open drain with internal pull-up configuration no external pull-up required SCLK 4 O Digital I/O line for external card interfaces. SC4 38 I/O SC8 39 I/O LCD_Enable 4 I/O LCD_RW I/O LCD_RS 6 I/O Digital auxiliary I/O line for external card interfaces (C4 I/O). Open drain with internal pull-up configuration no external pull-up required Digital auxiliary I/O line for external card interfaces (C8 I/O). Open drain with internal pull-up configuration no external pull-up required LCD driver dedicated I/O line: LCD Enable. Can be used as standard I/O LCD driver dedicated I/O line: LCD Read/Write. Can be used as standard I/O LCD driver dedicated I/O line: LCD Register Select. Can be used as standard I/O LCDDAT (3) 3 LCDDAT () 4 I/O LCDDAT () LCDDAT (0) 0 TOTAL 64 LCD driver dedicated I/O lines - Data pins. Can be used as standard I/Os Page: 7 of 8 00 TERIDIAN Semiconductor Corporation Rev.0

8 S0F TYPICAL APPLICATION SCHEMATIC U DMC604 GND VDD VO RS R/W* DB0 DB DB DB3 DB4 DB DB6 DB7 NC E Decoupling capacitors should be located close to U. VPA C + C 0uF 0.uF to VPA, VPC, C3 C4 C C6 C7 + C + C 0uF 0uF0.uF 0.uF 0.uF 0.uF 0.uF INT0 SC_CLK SC_IO SC_RST CCP CCN CCN CCP SC_RST SC_C4 SC_C8 SC_IO VPC Charge Pump Capacitors (C to C4) to be placed on bottom side of board and within mm of U pins. They sould be away from Smartcard signal lines. VCC tracks should be wider than 0.mm. SCx_CLK track should be routed away from other Smartcard signals. SC_RST SC_IO SC_RST SC_C4 SC_IO SC_C8 R8 0 SMARTCARD SLOT # J3 VCC 3 RST 4 CLK C4 6 GND 7 VPP 8 I/O C8 9 0 SW- SW- Smart Card Connector CARD DETECT POLARITY SELECT 3.3V ACTIVE HIGH JP7 JP8 DET_POL 3 3 ACTIVE 3.3V LOW J6 VCC RST CLK C4 GND VPP I/O C8 SMARTCARD SLOT # U DET 9 0 SW- SW DET DET R6.4k DET_POL R7.4k LCD DISPLAY SYSTEM 6 CHARACTER BY LINES Smart Card Connector 73S C4 and C4 to be placed within cm of U4 U4 3.3V.0V V_OUT V_IN C4 + GND 4.7uF 3 ON/OFF 4 + C4 BYPASS.uF LP98 C43 + LDO 0.uF C 0uF C6 0.uF C 0.uF C 6.8uF C9 6.8uF C0 0.uF C7 0.uF C8 0uF VPC CCP CCP C3 C4 CCN 0.68uF 0.68uF CCN + R 0 DET VPA 3 VPA 4 VNA SEC OSC_IN_ 6 OSC_OUT_ 7 OSCIN 8 OSCOUT 9 LCDDAT0 0 LCDDAT LCDAT0 LCDDAT LCDAT LCDDAT3 3 LCDAT LCD_EN 4 LCDAT3 LCD_RW LCD_Enable LCD_RS 6 LCD_RW LCD_RS Reserved INT0 CLK IO RST VCC CCP VPC CCN VCCIN VNC VCCIN CCN VPC CCP VCC TXD RXD NC NC INT ISP_Program RESET USR7 USR6 USR USR4 USR3 USR RST C4 C8 IO VNC CLK SCLK SIO SC8 SC4 DET_CARD DET_CARD USR0 USR 3.3V 3.3V J C33 R8 ISP 0.uF 0k U3 3.3V NO_ISP 3 MAX337CAI ISP SELECT C3 7 8 C36 0.uF V+ C+ 0.uF + C34 C- 0uF OSC_IN_ DB9_RS3 C37 4 C38 R3 0.uF V- C+ 0.uF 0k P 3 C- C TOUT TIN 3 pf 8 7 TOUT TIN 3 0 T3OUT T3IN 9 7 T4OUT T4IN 7 TOUT TIN ROUTBF 9 RIN ROUT 0 RIN ROUT 8 R3IN R3OUT SERIAL 3.3V 3 4 ENB PORT SHDNB 6 RXD 3.3V INT Y OSC_OUT_.000MHz C30 pf C39 + uf C40 0.uF V 3 CW LCD_RS RV 0K LCD BRIGHTNESS ADJUST LCD_RW LCD_EN LCDDAT0 LCDDAT LCDDAT LCDDAT3 VCC MBAUD GND TXD Page: 8 of 8 00 TERIDIAN Semiconductor Corporation Rev.0

9 ELECTRICAL SPECIFICATION ABSOLUTE MAXIMUM RATINGS Operation outside these rating limits may cause permanent damage to the device. PARAMETER RATING Supply Voltage (V PD, V PA, V PC, V PDPLL ) -0.V to 4.0V Supply Voltage (V PG ) -0.V to 6.0V Pin Input Voltage (except OSCIN, OSCIN3) -0.V to 6.0V Pin Input Voltage (OSCIN, OSCIN3) -0.V to + 0.V Storage Temperature -60 to 0 C Pin Current ±7mA Maximum continuous Total Power Dissipation (at T A = 8 C).W Maximum Operating Junction Temperature C ESD Tolerance Card interface pins ESD Tolerance Other pins Note*: ESD testing on Card pins is HBM condition, 3 pulses, each polarity referenced to ground. +/- 4.kV +/- 00 V RECOMMENDED OPERATING CONDITIONS PARAMETER RATING Supply Voltage V PA /V PD /V PC with respect to V NA /V ND /V NC.7V to 3.6V Supply Voltage V PD with respect to V ND for RAM data retention.0v to 3.6V Supply Voltage (V PG ) with respect to V NG.7V to.v MHz Oscillator Frequency.000 MHz ±00ppm Operating Temperature 0 C to +8 C THERMAL RESISTANCE PARAMETER R th (J-A) Thermal Resistance Junction to Ambient RATING 47º C/W Page: 9 of 8 00 TERIDIAN Semiconductor Corporation Rev.0

10 DC CHARACTERISTICS: DIGITAL I/OS SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Digital I/O except for OSC I/O V IL V IH V OL V OH I IL I IH I IL3 I IH3 Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Leakage Current Input High Leakage Current Input Low Leakage Current Input High Leakage Current V 0.7*V PD. V I OL = ma 0.4 V I OH = -ma V PD V V SS < V in < V IL Pull-ups Disabled µa V IH < V in < V DD Pull-downs Disabled 3 µa V SS < V in < V IL Pull-ups Enabled 3 µa V IH < V in <.V Pull-downs Enabled 0 µa DC CHARACTERISTICS: OSCILLATOR I/OS SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Oscillator (OSC) I/O Parameters V IL V IH V OLOSC V OHOSC I IL I IH t OSCMStart Input Low Voltage - OSCIN Input High Voltage - OSCIN Output Low Voltage - OSCOUT Output High Voltage - OSCOUT Input Leakage Current - OSCIN Input High Leakage Current - OSCIN MHz Oscillator start up time * V PD V 0.7*V PD V PD + 0. V I OL = 3.0mA 0.7 V I OH =-3.0mA V PD V V SS < V in < V IL 30 µa V IH < V in < V DD 30 µa Osc V PP = 90% stable V V PC = 3.3V, ºC 00 µs Pull-ups on USR (7:0) Pull-downs on ISP_Program Page: 0 of 8 00 TERIDIAN Semiconductor Corporation Rev.0

11 DC CHARACTERISTICS: ICC INTERFACE - CLK AND RST SIGNALS 73S0F SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Clock Lines CLK and /CLK (VCC = VCC for CLK and VCC = VCC for CLK) 0 < I V OHC High Level Output Voltage OH < 0µA, V CC = Min V CC - 0. V CC V -0µA < I V OLC Low Level Output Voltage OL < 0, V CC = Min V t r-clk, t f-clk Rise / Fall time C load = 30pf max - 8% of clock period P ERTLC Signal perturbation low Signal low V P ERTHC Signal perturbation high Signal high V CC - 0. V CC + 0. V δ Duty Cycle Clocks in stable operation 4 % Reset Lines RST and RST (VCC = VCC for RST and VCC = VCC for RST) V OHR V OLR t r-rst, t f- RST High Level Output Voltage Low Level Output Voltage 0 < I OH < 0µA, V CC = Min -0µA < I OL < 0, V CC = Min Rise / Fall time C load = 30pf Max - V CC - 0. V CC V V P ERTLR Signal perturbation low Signal low V P ERTHR Signal perturbation high Signal high V CC - 0. V CC + 0. V 0.8 µs DC CHARACTERISTICS: ICC INTERFACE I/O SIGNALS SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Data Lines IO/IO, C4/C8 (VCC = VCC or VCC as appropriate) V OHSC V OLSC High Level Output Voltage Low Level Output Voltage 0 < I OH < 0µA, V CC = Min -ma < I OL < 0, V CC = Min t r-sc, t f-sc Rise / Fall time (Output) Cload = 30pf Max * V CC V CC V V P ERTLSC Signal perturbation low Signal low V P ERTHSC Signal perturbation high Signal high 0.8 * V CC V CC + 0. V I OLS C (Inactive) Current from I/O when inactive and pin grounded 0.8 µs -00 V V ILSC High Level Input Voltage 0.6 * V CC V CC V V ILSC Low Level Input Voltage 0 0. µs I IHSC High Level Input Current V in = V IHSC range µa I ILSC Low Level Input Current V in = V ILSC range µa I SCSC Short Circuit Current 33Ω to opp. supply - ma I RTFTSC Rise / Fall time (Input) -. µs R PUSC Pull-up to VCC Static 0. 7 kω Page: of 8 00 TERIDIAN Semiconductor Corporation Rev.0

12 DC CHARACTERISTICS: ICC INTERFACE VCC SIGNALS (DC-DC CONVERTER) SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Card Power Supply (V CC ) (V CC = V CC or V CC as appropriate) V CC V CC V NOISE I CC I CC I OC I CC Output Voltages to ICC and ICC (with 40nAs dynamic loads and VNOISE included).9v < VPC < 3.6V Peak to peak ripple and noise on VCC V output V 3V output V Deactivated V C L = 6.8 µf and C cp = 0.68 µf 0 00 Maximum Output Currents to V output 6 00 ma ICC and ICC 3V output 6 00 ma Each output ICC over-current ma measured separately Combined Current V output 6 ma ICC+ICC VPC 3.0V to 3.6V 3V output 6 ma I STARTUP * V CC Startup current Assertion of See Curve ma CMDVCC Note: The following diagram shows the maximum start up and maximum operating current for V CC. If the load placed on V CC draws more current than line indicated by Maximum Static ICC at startup when V CC is asserted, the DC-DC converter may not be able to achieve the minimum voltage levels as specified for V CC above. Once the startup load condition has been met, the load can be increased to draw up to the current limit indicated by the line labeled I CC max after starting. This type of load increase is expected as the clock signal to the card is asserted and data transfer takes place. The diagram shows the worst case condition, which is at 8 C. mv pp 70mA Icc max after starting 60mA 0mA Icc 40mA 30mA Maximum Static ICC at startup 0mA VPC Page: of 8 00 TERIDIAN Semiconductor Corporation Rev.0

13 DC CHARACTERISTICS: VOLTAGE REFERENCE SYMBOL PARAMETER Condition MIN Typ. MAX UNIT V lvdet V PD Low Voltage Flash Erase/Write Protect Analog enabled (Disable_Analog = 0) V DC CHARACTERISTICS: POWER CONSUMPTION ON V PA SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Analog (V PA ) Current I DDA-off Supply current on V PA when Analog Disable_Analog = µa Page: 3 of 8 00 TERIDIAN Semiconductor Corporation Rev.0

14 DC CHARACTERISTICS: POWER CONSUMPTION ON V PD 73S0F SYMBOL PARAMETER Condition MIN Typ. MAX UNIT Digital (V PD ) Current I DDPD Digital supply current on V PD, PD Mode, oscillators and clocks Off OSCIN Off, CPU in PD mode, All other clocks Off 0 µa I DDIDLEM Digital supply current on V PD, IDLE Mode MHz oscillator and clock circuitry (PLL) On OSCIN On, CPU in IDLE mode, Disable_PLL=0, All other clocks Off, CPU clock=6mhz CPU clock=mhz CPU clock=4mhz ma I DDRun V DDDR Digital supply current on V PD, Normal Mode MHz oscillator and clock circuitry (PLL) On RAM data retention supply voltage OSCIN On, All other clocks Off, CPU clock=6mhz CPU clock=mhz CPU clock=4mhz ma.0 V Page: 4 of 8 00 TERIDIAN Semiconductor Corporation Rev.0

15 DC CHARACTERISTICS: POWER CONSUMPTION ON V PC 73S0F SYMBOL PARAMETER Condition MIN Typ. MAX UNIT DC-to-DC converter Current (V PC ) I DDon6 I DDon36 I DDon7 I DDon37 I DDon0 I DDon30 I DDSCStdby I DDSCStdby3 I DDSCOff Supply current on V PC when V CC =V and 6mA load Supply current on V PC when V CC =3V and 6mA load Supply current on V PC when V CC =V and 7mA load Supply current on V PC when V CC =3V and 7mA load Supply current on V PC when V CC =V and ma load Supply Current on V PC when V CC =3V and ma load Supply current on VPC when V CC =V and cards are in power down mode Supply current on V PC when V CC =3V and cards are in power down mode Supply current on V PC when DC-DC converter is Off VCC = VCC = V. ICC=ICC = 6mA, ICC IO, C4, C8 = high VCC = VCC = 3V. ICC=ICC = 6mA, ICC IO, C4, C8 = high VCC = VCC = V. ICC=ICC = 7mA, ICC IO, C4, C8 = high VCC = VCC = 3V. ICC=ICC = 7mA, ICC IO, C4, C8 = high VCC = VCC = V. ICC=ICC = ma, ICC IO, C4, C8 = high VCC = VCC = 3V, ICC=ICC = ma, ICC IO, C4, C8 = high VCC = VCC = V, ICC=ICC = 0mA, ICC IO, C4, C8 = high Card clock stopped VCC = VCC = 3V, ICC=ICC = 0mA, ICC IO, C4, C8 = high Card clock stopped V CC = V CC = 0V, MHz dc/dc clock Off, Analog circuitry Off ma ma 0 ma 0 ma 0 3 ma 0 3 ma. 3 ma. 3 ma µa Page: of 8 00 TERIDIAN Semiconductor Corporation Rev.0

16 MECHANICAL DRAWINGS CAUTION: Use handling procedures necessary for a static sensitive component The following figure shows the package outline of the 73S0F in its LQFP 64-pin packaged form. It is available in both tray and tape-reel conditioning PIN No. Indicator Typ. 0.0 Typ LQFP 64 Package Outline Controlling dimensions in mm Page: 6 of 8 00 TERIDIAN Semiconductor Corporation Rev.0

17 PACKAGE PIN DESIGNATIONS (Top View) VPA VNA SEC OSCIN OSCOUT LCDAT0 LCDAT LCDAT LCDAT3 LCD_Enable LCD_RW LCD_RS TERIDIAN 73S0F RST C4 C8 IO VNC CLK SLCK SIO SC8 SC4 DET_CARD DET_CARD USR0 USR TXD RXD NC NC INT ISP_Program RESET USR7 USR6 64 USR 63 USR4 USR3 USR Reserved INT0 CLK IO RST VCC CCP VPC CCN VCCIN VNC VCCIN CCN VPC CCP VCC LQFP64 Pin Assignment (Top View) Page: 7 of 8 00 TERIDIAN Semiconductor Corporation Rev.0

18 ORDERING INFORMATION PART DESCRIPTION ORDER NO. PACKAGING MARK 73S0F - 64 pin LQFP 73S0F-CGT 73S0F-CGT 73S0F - 64 pin LQFP Tape / Reel 73S0F-CGTR 73S0F-CGT 73S0F - 64 pin LQFP Lead-Free 73S0F-CGT / F 73S0F-CGT 73S0F - 64 pin LQFP Lead-Free Tape / Reel 73S0F-CGTR / F 73S0F-CGT No responsibility is assumed by TERIDIAN Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TERIDIAN Semiconductor Corporation. TERIDIAN semiconductor Corporation reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. Data Sheet This data sheet is proprietary to TERIDIAN Semiconductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. TERIDIAN Semiconductor Corp Oak Canyon Rd. Irvine, CA TEL (74) FAX (74) //0 Rev..0 Page: 8 of 8 00 TERIDIAN Semiconductor Corporation Rev.0