Technology & Manufacturing

Transcription

1 Technology & Manufacturing Kevin Ritchie Senior Vice President Technology and Manufacturing Group

2 Development & Manufacturing Strategy Process Technology Leadership Flexible Development Options Internal + External + = Manufacturing Capability Flexible Manufacturing Infrastructure Maximize: Customer Responsiveness Revenue Growth ROIC Internal + External

3 Year in Review Improved financial performance through the downturn Ramped 65nm Expanded manufacturing capacity to meet demand 2mm analog Assembly & test Began to restructure silicon process development

4 Advanced Digital CMOS Foundries 13nm 9nm 65nm 45nm Chartered 2Q7* 2mm 3mm SMIC TSMC 2Q8* UMC 2Q8* Total Fabs TBD * Estimated qualification Foundries continuing to expand capacity on all technologies Partner with UMC, TSMC and at least one more foundry on advanced nodes

5 Foundries Enhance Manufacturing Responsiveness 13nm/9nm Wafers Foundries TI Advanced Logic Fabs 1Q3 2Q3 3Q3 4Q3 1Q4 2Q4 3Q4 4Q4 1Q5 2Q5 3Q5 4Q5 1Q6 2Q6 3Q6 4Q6 1Q7 Goal is to maintain high utilization of most expensive assets Advanced logic fabs account for >3% of TI depreciation in 26 TI advanced logic factories remain highly utilized throughout cycle

6 Manufacturing Strategy Delivers Better Financial Results* Return on Invested Capital** Depreciation % Revenue % 1 % * 21 and forward, continuing operations only ** ROIC = Net Operating Profit After Tax / (Assets - Non-Debt Liabilities)

7 Improved Performance through the Cycle 4 3 Revenue Inventory Gross Margin % Last large correction High internal production dependence Inventory down, Revenue down, Margin stable $B 2 3 %

8 TI Process Development Model What Has Not Changed: What Has Changed: TI s commitment to deliver leading-edge products and technology to our customers Analog process development in-house Package and test development in-house TI CMOS productization in partnership with foundry Analog development team increased by 5% Modeling team increased by 5% Production strategy, including advanced digital CMOS manufacturing

9 New Process Development Model Key Points Why: We believe the foundry industry has closed the technology timing gap and will meet TI s requirements. Financial impact: Eliminating redundant technology development will save TI ~$15M / year. Partnership: More than 2 people will be collaborating on advanced CMOS development (modeling, process definition, working with foundries). Timing: Development wafers will be processed in foundries after nm (transition node) developed separately at TI and foundries 32nm developed jointly at foundries Future production: Licensing agreements with our key foundry partners will allow ongoing internal manufacturing.

10 Past Method TI Process Development TI FAB Process Definition Short Flows Baseline Flow Qual TI Production Parallel effort until transfer Requires 3 R&D activities Foundry Product Needs Baseline Qual TI Production Process Modification Foundry Process Definition Short Flows Baseline Flow Qual Foundry Production Future Method Jointly Develop at Foundry Process Definition Short Flows Baseline Flow Qual TI Production F O U N D R Y B A S E L I N E Joint process definition Joint models One R&D activity Fan out of mature flow = quicker time to qual and production RFAB DMOS 6 Copy Exact Qual TI Production

11 Analog Manufacturing Strategy Extending Asset Life/Smart Buys mm Analog Capacity (K-Wafer starts/quarter) TI fab life cycle analog growth with minimal capital investment Advanced logic (CMOS) Mature logic Advanced analog Mature, long-life analog DMOS5 conversion to advanced analog continues to add analog capacity, increases flexibility 1 5 1Q3 1Q4 1Q5 1Q6 1Q7 Strategic purchase of used tools steps up 2mm capacity Agere equipment purchase 2H5 DFAB capacity added 2Q6 KFAB tools available in 28

12 Accelerating Analog Process Technology Research Development priorities include: Significantly smaller power transistors Higher precision thin-film resistors Higher density capacitors High-density non-volatile embedded memories Increased digital density for analog SoCs 3D interconnect and thick top metal

13 Mu (cum) Analog Technology Leadership Mu (cum) Portable Power Products LBC7 Wireless Power Management & RFID A35 1Q6 2Q6 3Q6 4Q6 1Q7 Mu (cum) Low-Noise, High-Frequency Amplifiers & Data Converters BiCom3 1Q6 2Q6 3Q6 4Q6 1Q7 1Q6 2Q6 3Q6 4Q6 1Q7

14 Summary Manufacturing strategy works Responsive Lower, more stable CapEx Consistently high advanced-logic asset utilization through cycle Extended asset life Higher, more stable profitability $9M CapEx in 27 focused on assembly & test Transition advanced CMOS development to TI-Foundry joint model Accelerating lead in analog performance and technology