Technology & Manufacturing. Kevin Ritchie Senior vice president, Technology & Manufacturing

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1 Technology & Manufacturing Kevin Ritchie Senior vice president, Technology & Manufacturing

2 27 in review Manufacturing strategy continues to deliver financial results Accelerating analog leadership Increased process technology R&D team by 5% Added assembly/test capacity for improved customer service Expanded 2mm wafer capacity at low cost Began construction of new assembly/test site CMOS process leadership continues Prototyped first 45nm device Taped out 32nm test chip Transitioned advanced logic to joint foundry development model

3 Higher, more-stable profitability 4 TI Revenue GPM% 6 3 High internal production dependence 4 $B 2 %

4 Lower expenditures, higher returns Depreciation % Revenue Return on Invested Capital (ROIC) % % * ROIC = (net operating profit after tax) divided by (assets minus non-debt liabilities) * 21 and forward, continuing operations only

5 Accelerating leadership in analog process technology Extensions Refresh Differentiate Cost New Platforms Performance Density Cost Research Disruptive Unique Opens markets Extensions Add new components and reduce cost on existing process technologies New platforms Develop new processes to drive next-generation performance, power, precision, density and cost Research Create unique, disruptive process and modeling innovations in analog, power devices, capacitors, resistors, 3-D interconnect, nonvolatile embedded memories, etc.

6 Optimized analog process platforms... High-power BiCMOS (LBC) Bipolar and dual-gate CMOS LDMOS & thick copper enablers Multi-voltage capability 2V, 6V, and 1V+ branches Voltage-scaled DECMOS Non-volatile memory options High-speed BiCMOS (BiCOM3) Complementary bipolar CMOS Low parasitics High-quality passives (thin film resistor) SOI & SiGe High-density analog CMOS (C5, A35, E35) Logic & analog CMOS Low V t CMOS Density Passives Low-leakage transistors FRAM High-precision analog CMOS (HPA7) Low transistor noise High-quality passives (thin film resistor) 3 / 5V CMOS, high voltage Linear capacitance Low parasitics

7 ... differentiated analog products Wireless Power Management Mu (cum) A35 1Q7 2Q7 3Q7 4Q7 1Q8 Portable Power Products Low-Noise, High-Frequency Amplifiers & Data Converters 2 LBC7 1 BiCom3 Mu (cum) 15 1 Mu (cum) Q7 2Q7 3Q7 4Q7 1Q8 1Q7 2Q7 3Q7 4Q7 1Q8

8 Breakthrough analog process research Completing next-generation LBC and BiCOM process technology qualifications Areas of research: Ultra-low power analog technologies Smaller form factor power transistors High-speed SOI and bulk bipolar transistors Precision thin-film resistors and capacitors High-density, low-power, non-volatile, embedded memories 3-D interconnect and thick top metal SPICE models for power devices and memories

9 Low-cost analog capacity expansion # Tools CapEx Additional capacity* 28 KFAB Equipment Redeployment Miho Japan 76 $135M 43 Freising Germany 35 $6M 2 DMOS5 Dallas 46 $34M 18 Total 157 $229M *K-wafer starts/quarter 2mm Analog Capacity (K-wafer starts/quarter) 1Q5 1Q6 1Q7 1Q8 1Q9 Redeployment supports ~$1B/yr additional analog revenue

10 Analog package support for the future New TI Clark assembly/test facility (Philippines) Wafer scale chip package QFN package 12B unit annual production capacity 8K sq. ft. 2H8 production start

11 CMOS process technology: 45/4nm Initial 45nm products sampled in 27 completed first phone call 2H8 production start at two foundries; third foundry, 29 Initial 4nm products tape out 2H8 for high-performance DSP and RISC microprocessors 45nm 3.5G Baseband/OMAP Apps Processor Process Logic Gates Memory Voltage Package Multi- ARM11 Media C55x DSP CPU Image DSP DBB 3.5G Modem MHz scaling Power scaling 45nm 1M 16Mb V Flip chip 84MHz 48MHz 24MHz 155% 37% Supports: HSUPA/HSDPA, WCDMA, EDGE/GPRS/GSM

12 CMOS process technology: 32/28nm Initial test chip released on plan.12µm 2 SRAM bit ~1Mb of SRAM Digital, analog, RF components Supports leadership performance speed and power through SmartReflex 2 technology Superior density achieved through full immersion lithography Initial high-k/metal-gate technology supports highest performance products

13 Looking ahead Accelerate leadership in analog process technology development Expand analog capacity ahead of customer demand 2mm wafers Assembly/test capacity Begin 45nm production ramp 28 CapEx: $9M

14 Summary Manufacturing strategy: Contributing to TI s improved financial performance Extending analog process capability for highly differentiated products Adding analog capacity at low cost Continuing CMOS process leadership by collaborating with best-in-class foundries