Programmable Logic Design Grzegorz Budzyń Lecture. 6: Combinational & sequential circuits
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1 Programmable Logic Design Grzegorz Budzyń Lecture 6: Combinational & sequential circuits
2 Plan Complex types and types conversion Resolution functions Combinational circuits Statements examples Simple sequential circuits Regular sequential circuits
3 Complex types and types conversion
4 Types and subtypes NumberoftypesavailableinVHDL isverylimited Itispossibleandcommonto constructusabledata subtypes Therearea fewmethodsofdoingso: 1) limitingtherangeofthebasicdata type
5 Types and subtypes 2) makinga newdata typewithlimitedrangeofthe basic data type
6 Types and subtypes 3a) construct a composit types: arrays or records
7 Types and subtypes -3a) constructa composittypes: arraysorrecords array init
8 Types and subtypes 3b) construct a composit types: arrays or records
9 Type conversion VHDL is a strongly typed language std-logic-vector, unsigned, and signedare treated as different data types even when all of them are defined as an array with elements of the std-logic data type A conversion functionor type castingis needed to convert signals of different data types
10 Data conversion table
11 Data conversion - example
12 Data conversion user function
13 Resolution functions
14 Resolution function VHDL does not allow multiple concurrent signal assignments to an unresolved signal Resoltuion functions are used to determine the assigned value when there are multiple signal drivers to the same signal Resolution functions can be user defined or called from a package
15 Resolution function The specification of a resolution function is the same as for ordinary functions with one requirement: the resolution function must be pure The value returned by an impurefunction can depend on items other than just its input parameters (e.g.shared variables)
16 Syntax: Resolution function
17 Resolution function Resolution functions are associated with signals that require resolution by including the name of the resolution function in the declaration of signals or in the declaration of the signal subtype. Standard types (BIT and BIT_VECTOR) are not resolved and it is not possible to specify multiplesource buses with these types. This is quite restrictive for typical applications, which use buses. Because Std_Logicand Std_Logic_Vectorare resolved and can handle buses, they became the de facto industrial standard types.
18 Resolution function
19 Combinational circuits
20 Combinational circuits Combinational Circuits: Circuits whose outputs depend only on the current inputs; hence they appear to combine the inputs in some way to produce the outputs Combinational circuits are composed of intermediate-sized components, such as adders, comparators, and multiplexers.
21 Combinational circuits A combinational circuit can be thought of as an implementation of a Boolean function It takes some inputs A, B, C, etc., and produces a unique output f(a,b,c, ). The circuititself is just a network of the basic gates, where the information flows in one direction only (generally from left to right)
22 Combinational circuits
23 Building blocks
24 Building blocks Sequenatialcircuits are composed of simple basic blocks like simple gates: Source: [1]
25 Building blocks Multiple input gates: Q <= x1 AND x2 AND x3 AND x4 Source: [1]
26 Building blocks Multiple input gates: Q <= x1 OR x2 OR x3 OR x4 Source: [1]
27 Multiplexers: Building blocks Source: [1]
28 Decoders: Building blocks Source: [1]
29 Building blocks Arithmetic comparators: Process(input1, input2) begin if ( input1 >= input2 ) then output <= '1'; else output <= '0'; end if; end process; Source: [1]
30 Statement examples
31 when else example
32 when else example
33 with select example
34 with select example
35 if else example
36 generic example VHDL provides a construct, known as a generic, to pass information into an entity and component. Since a generic cannot be modified inside the architecture, it functions somewhat like a constant.
37 generic example
38 generic example
39 Barrel shifter example
40 Simple sequential circuits
41 Sequential circuits A sequential circuit is a circuit with memory, which forms the internal state of the circuit. Unlike a combinational circuit, in which the output is a function of input only, the outputof a sequential circuit is a function of the input and the internal state
42 Sequential circuits The present state of a sequential circuit depends on a previous state and on the values of input signals. In the case of synchronous sequential circuits, the changeofstateiscontrolledby a clocksignal. With asynchronous circuits, the change of state maybe causedby therandom changeintimeof an input signal.
43 Sequential circuits Sequentialcircuitsarecircuitsthat perform a computation in multiple steps (clock cycles) Theycomposeof: Memory registers Combinational circuits Intermediate results are held in registers and transferred from register-to-register using combinational circuits
44 Synchronous System - Block Diagram
45 Synchronous System - Blocks State register: a collection of D FFscontrolled by the same clock signal Next-state logic: combinational logic that uses the external input and internal state(i.e., the output of register) to determine the new value of the register Output logic: combinational logic that generates the output signal
46 Building blocks
47 Building blocks The most basic storage component in a sequential circuit is a D-type flip-flop (D FF): Stores n-bits of data Rising (or falling) clock latches the input Output always maintains the value of stored bit May have asynchronous reset A collection of D FFscan be grouped together to storemultiple bits and is known as a register.
48 Building blocks simple DFF
49 Building blocks DFF with reset
50 Building blocks full DFF
51 Building blocks D-latch
52 Building blocks Register
53 Building blocks 3-bit counter
54 Synchronous vs asynchronous reset Synchronous Asynchronous
55 DFF - parameters The three main timing parameters of a D FF are: T cq ( clock-to-q delay), T setup (setuptime), T hold (hold time). T cq is the time required to propagate the value of d to q atthe rising edge of the clock signal. The d signal must be stable around the sampling edgeto prevent the FF from entering the metastablestate. T setup und T hold specify the timeintervals before or after the sampling edge.
56 DFF - parameters
57 Maximal operating frequency Itisveryimportantanddifficultto estimatethe maximal operating frequency of the sequential circuit As allstoragecomponentsaregroupedtogether, sotheycanbe treatedas single register this simplifies the analysis
58 Maximal operating frequency Where: T cq -clock-to-q delay, T setup -setuptime, T comb -the maximal propagation delay of next-state logic
59 Sequential circuits - categories Based on the characteristics of the next-state logic, sequential circuits can be divided into three categories: Regular sequential circuit FSM(finite state machine) FSMD(FSM withdata path).
60 Sequential circuits - categories Regular sequential circuit. The state transitions in the circuit exhibit a regular pattern, as in a counter or shift register. The next-state logic is constructed primarilyby a predesigned, regular component, such as an incrementoror shifter. s0 s3 s1 s2
61 Sequential circuits - categories FSM(finitestatemachine). The state transitions in the circuit do not exhibit a simple, repetitive pattern.the next-state logic is constructed by random logic and synthesized from scratch. s0 s3 s1 s2
62 Sequential circuits - categories FSMD(FSM withdata path). The circuit consists of a regular sequential circuit and an FSM. The two partsare known as a data path and a control path, and the complete circuit is known as anfsmd. This type of circuit is used to implement an algorithm represented by register-transfer (RT) methodology, which describes system operationby a sequence of data transfers and manipulations among registers.
63 Sequential circuits - categories FSMD(FSM withdata path). The job of the finite state machine is to sequence operations on a datapath
64 Thank you for your attention
65 References [1] Combinational Circuits, [2] [3] d ata_types_and_operators/understanding_vhdl_attributes.htm [4] [5] [6] [7] [8]
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