FPGA Implementation of Normalization block of Fingerprint Recognition Process

Transcription

1 Proc. of Int. Conf. on Recent Trends in Signal Processing, Image Processing and VLSI, ICrtSIV FPGA Implementation of Normalization block of Fingerprint Recognition Process S. Gayathri 1 and V Sridhar 2 1 Dept of E & C, SJCE, Mysore, Karnataka, India sgmurthy_65@yahoo.com 2 Dept of E&C, PESCE, Mandya, Karnataka, India venusridhar@yahoo.com Abstract The reliability of Fingerprint recognition process in turn the Fingerprint Recognition system depends on the minutiae. Accurate minutiae depend on the quality of the fingerprint image. Most of the images are of poor quality. This leads to distorted levels of variation in grey-level values along the ridges and valleys. These variations are minimized by adapting normalization process, which has pre-specified mean and variance. As well, normalization facilitates the subsequent Fingerprint recognition process. Implementation of normalization block of Fingerprint recognition process on Virtex-II Pro FPGA development board is proposed. As well, the comparison of FPGA results with Matlab is carried out. Index Terms reliability, minutiae, preprocessing, recognition, normalization, implementation. I. INTRODUCTION The demand for using biometric recognition system in many applications is growing rapidly. This has triggered many researches to carry out innovative ideas in recognition system with biometrics. The main requirement of the fingerprint recognition system is to reduce the processing time, which is achieved by Field Programmable Gate Arrays (FPGAs). Fingerprint based identity verification, is one of the most widely used biometric system [1] due to its ease of acquisition, high distinctiveness, persistence, and acceptance by the public. FPGA is a good choice for implementing fingerprint recognition application because it has a large logic capacity and memory resources [2]. The performance of the fingerprint recognition system heavily depends on the extraction of minutiae from the fingerprint image [3]. Implementation of fingerprint feature extraction and matching algorithms as a part of fingerprint recognition system is being focused in [3]. The algorithm is based on the crossing number method, which is implemented on FPGA device. Most of the automatic fingerprints recognition systems rely on minutiae pattern matching [4]. Fingerprint Recognition using Minutiae Score Matching method (FRMSM) with block filter has better false minutiae ratio compared to the existing algorithm. Minutiae are the local discontinuities in the fingerprint pattern, which represent terminations and bifurcations [5]. To obtain the minutiae, ridge structure must be of good quality. In most of the fingerprint images, the ridge structures are not well defined. Hence pre-processing of Fingerprint image is essential to DOI: 03.AETS Association of Computer Electronics and Electrical Engineers, 2014

2 extract features that are more reliable. Many kinds of enhancement methods [6] for fingerprint image are proposed. Most of them are based on image binarization, and others enhance images directly from gray scale. Fingerprint image may exhibit distorted levels of variation in gray level values along the ridges and valleys. Normalization process is adapted to reduce the effect of these variations, which facilitates the subsequent image enhancement steps [6]. Normalization has a pre-specified mean and variance, which enhances the quality of fingerprint image. A critical step in fingerprint recognition [7] is to skeletonize the fingerprint image for minutiae extraction, which is recognized as thinning. The recognition process [2] and [7] involves a series of image enhancement and minutiae extraction steps that can be classified as follows: Fingerprint normalization, Orientation and filed frequency image estimation, Filtering, Binarization, Thinning, Minutiae extraction, and False minutiae elimination. The quality of fingerprint image and extraction of minutiae has an important role in the performance of automatic identification and verification. The minutiae extraction algorithm starts with the preprocessing of fingerprint image for improving the quality of images without changing the local and global properties of the image [8]. Hardware implementation [9] of the fingerprint recognition system provides real time application and low power consumption. In addition, portable, and has embedded architecture. Several choices in hardware implementation of the system are Microcontrollers, DSP processors, Application Specific Integrated Circuit (ASIC), FPGAs etc. Biometric identification has made tremendous impact in technology development. Small volume, lower power consuming, lower cost, safety, reliability, good practicality, easy to install and maintain are the key features of intelligent authentication system [10] using 32 bit microcontroller. FPGAs also support a wide range of interconnection standards, such as double data rate (DDR) SRAM memory, PCI and high-speed serial protocols, soft and hard processors capability. FPGAs support partitioning of the system design. The complexity of systems is reduced by partitioning FPGA devices [9] and [11]. To heighten the biometrics security level, the biometric feature extraction and verification need to be performed within smart cards. Implementation of minutiae extraction using modified ridge-following algorithm is integrated onto the resource-constrained System on Chip (SoC) [12]. Reconfigurable computing adds to the traditional hardware/software design flow, a new degree of freedom in the development of electronic systems [13]. This leads to automatic fingerprint authentication system oriented in real time embedded application. However, the physical implementation of automatic fingerprint authentication system is still a challenging task. Until now, only initial stages of biometric recognition system are tested. Fingerprint image enhancement through reconfigurable hardware accelerators using hardware time multiplexing saves silicon area as compared to the existing general-purpose microcontroller system [14]. Fingerprint image processing through reconfigurable hardware [15] implemented on Virtex-4 by means of hardware-software co-design techniques, is faster in terms of execution time as compared to the existing techniques. In recent times, biometrics based on brain (EEG) and heart (ECG) signals [16] have emerged. The proposed technology is fraud resistant compared to conventional biometrics like fingerprints. However it is more cumbersome and still has issues such as lower accuracy and poor reproducibility over time. The proposed work is carried out at three stages, namely in stage 1, it has been proposed to implement Normalization block of fingerprint recognition process using MatLab. In stage 2, it has been proposed to implement Normalization block on FPGA. In stage 3, comparing the results of MatLab and FPGA implementation. The proposed methodology exhibits improved processing time as compared with MatLab. The software tools involved in this proposed work are Xilinx ISE design suite, and Matlab, while the hardware tool is Virtex-II Pro FPGA development kit. II. METHODOLOGY Fingerprints are chosen because of the following reasons: (a) No two individual have same features includes identical twins,(b) As hands and feet grow, details of friction ridges stay constant, and (c) Fingerprints last for a lifetime and grow back if they become worn out. Advantages of fingerprints are that they are cheapest, 31

3 the fastest, most convenient, and most reliable. Moreover 2/3 of the biometric world market uses fingerprints, and they are highly trusted by the public sector usage. The three approaches for fingerprint recognition are image-based approach, texture-based approach, and minutiae- based approach [7]. Minutiae-based approach is most widely used for matching of two fingerprints. It is invariant to translation, rotation, and scale changes, but error prone in low quality images. Generally fingerprint images are degraded by noise. This reduces the accuracy of Fingerprint recognition system. By incorporating preprocessing technique, noise effects can be minimized. This improves the Fingerprint image clarity. The first step in preprocessing technique is the normalization process. The normalization process based on blocking process is proposed. Fingerprint recognition process consists of image enhancement technique followed by minutiae extraction and false minutiae elimination. The image enhancement technique consists of the five stages. They are normalization, orientation and field frequency estimation, filtering, binarization, and thinning. This is followed by a minutiae extraction algorithm, to extracts the main minutiae features required for matching of two fingerprint images. Normalization is a process of changing the dynamic range of the Fingerprint image under consideration. This is referred as contrast stretching or histogram stretching. The purpose of changing the range is to eliminate any redundant pixels without compromising the quality of the fingerprint image. In fact the normalization process enhances the clarity of the image under consideration. Let the pixel intensity range of the input fingerprint image is 65 to 190. Assume 8- bit representation (0-255 range) of fingerprint image. Subtracting 65 from each of pixel intensity, brings the range 0 to 125. To get 0 to 255 ranges, multiply intensity of each pixel by 255/125. This operation virtually enhances the clarity of the ridges in the fingerprint image. Divide the original image [17] into sub-blocks with the size W x W and obtain the region of interest of the fingerprint image. The desired mean and variance for the image normalization are determined according to property such as mean and variance of each block. The proposed algorithm is verified for fingerprint images taken from the database generated using Hamster DX model HFDU06 NFD scanner. III. DESIGN The poor quality of the fingerprint images are the result of imperfections or non-uniformity of ink or nonuniform contact of finger during the acquisition. To enhance the quality of the Fingerprint image, an adaptive normalization algorithm based on the local property of the given fingerprint image is proposed. The input fingerprint image is represented by I(x,y) which is defined as an N x M matrix and I (i, j) represents the intensity of the pixel at the i th row and j th column. Hong and Jain [17], have employed the equation 3.1 for normalization process. The normalized image is represented by G(i,j) as follows: where M 0 and VAR 0 are the desired mean and variance values. M and VAR are the computed mean and variance of the input fingerprint image. The estimated initial mean and the variance are represented as and respectively [6]. The estimated mean and variance are varied to adapt for the local properties of the current block. Let and be the desired parameters for normalization of the i th block in the fingerprint image [6], the updated equations are as follows: Where and are the weighting factors which represent the degree of contribution of the variation term. and are the computed mean and variance of the i th block, respectively.the second terms in the right side of the above equations (3.2) and (3.3) are the variations, considered as the local properties of the i th block. As these terms contribute to the desired parameters, the desired parameters change according to local properties of the current block [6]. 32

4 Tools used: Xilinx ISE simulator is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. The Xilinx design flow is as shown in Figure 1. Figure 1. Xilinx design flow The XUP Virtex-II Pro Development System provides an advanced hardware platform that consists of a high performance Virtex-II Pro Platform FPGA surrounded by a comprehensive collection of peripheral components that can be used to create a complex system and to demonstrate the capability of the Virtex-II Pro Platform FPGA. The block diagram of XUP virtex-ii Pro Development System is as shown in Figure 2. The algorithm of normalization block is verified using MatLab. The Normalization block is designed using the Xilinx simulator with verilog coding and implemented on Vertex-II Pro FPGA development board. Comparison of Matlab and FPGA results are carried out for performance evaluation. Figure 2. Virtex-II Pro FPGA development system 33

5 IV. IMPLEMENTATION OF NORMALIZATION BLOCK A. Matlab Implementation The flow chart of the normalization block is as shown in Figure 3. The gray levels of the fingerprint input image are compared with that of standard values. Figure 3. Flow chart of Normalization block The normalized image is obtained if the gray levels are within the specified standard range, else normalize the gray levels of the input fingerprint image so that it lies in the range of specified standard value. Selection of the standard value is adaptive and depends on the quality of the input fingerprint image. Figure 4 shows the input Fingerprint image and the Matlab simulation of normalization block. The normalized image is of better clarity than that of input fingerprint image. The ridges are more distinct in the normalized image than that of input fingerprint image. The output image gray scale values are adjusted to a specified standard value. a) Input image b) Normalized image Figure 4. Fingerprint image B. FPGA implementation The normalization block consists of memory blocks, arithmetic unit, counter, comparator and address splitter module. All these modules are coded using Verilog HDL and simulated using Xilinx Modelsim simulator. 34

6 Then all these modules are integrated and implemented on Virtex-II Pro FPGA development board. Figure 5 shows the RTL schematic of the Normalisation block. Figure 5. RTL schematic of normalization block The Fingerprint image pixels are converted into text file and stored in a ROM. These values are copied into the RAM from ROM for processing. The mean of these image pixels is calculated using Accumulator and divider blocks. The difference between each pixel values with that of the mean of the block is obtained using subtractor. These values are squared and accumulated and stored as variance in RAM unit. The mean and variance outputs of the image are applied to the Comparator and Adder/ Subtractor block to get the Normalized fingerprint image. V. EXPERIMENTAL RESULTS The simulation waveforms of Normalization block using Xilinx ISE simuator is as shown in Figure 6. The simulation waveforms shows the response of the memory blocks, arithmetic unit, counter, comparator and address splitter and the final normalization block of the proposed normalization algorithm. The outputs of each module are synchronized with the 100 MHz clock input. The waveforms depict the values obtained for the input image pixels and various modules of the normalization block. The mean and variance are calculated and compared with the standard value to Normalize the image. The outputs are in signed decimal values. The input fingerprint image is stored in the ROM initially. The outputs from the individual modules of normalization block are at a high impedance state until the image is copied to the RAM block. At the rising edge of the clock, the image is copied into RAM from ROM for processing. Results obtained from simulation and implementations are discussed in three different sections considering different aspects: firstly hardware resources used, followed by processing time and finally the performance. 35

7 Figure 6. Simulation waveform of normalization block (contd ) Figure 6. Simulation waveform of normalization block (contd ) Figure 6. Simulation waveform of normalization block (contd ) (i) Hardware resources used: The Normalization block is implemented on Vertex-II Pro FPGA development board. The hardware occupied on the FPGA board are as follows: Slice Registers : 1936 out of % Slice LUTs : 1048 out of % 36

8 Figure 6. Simulation waveform of normalization block Logic : 982 out of % Memory : 66 out of % RAM : 16 SRL : 50 LUT-FF pairs : 734 out of % IOBs: 15 out of 640 2% Block RAM: 1 out of 148 0% BUFG/BUFGCTRLs : 1 out of 32 3% DSP48Es : 2 out of 64 3% RAMs : 1 Multipliers : 2 Adders/Subtractors : 2 Counters : 2 Accumulators : 2 Registers : 1 Latches : 3 Comparators : 1 (ii) Processing time: The processing time for the Normalization block implemented on Virtex-II Pro FPGA development board is in nanoseconds (7.25ns) whereas the same is in terms of few microsecs using Matlab. (iii) Performance: For the purpose of the performance evaluation, the database containing the fingerprint image of individuals (irrespective of age and gender) is generated. The database comprises the images acquired using NFD scanner. (a) Input Image (b) Normalized image Figure 7. Images on FPGA The input fingerprint on FPGA is as shown in Figure 7 (a) and the output normalized fingerprint image of FPGA is as shown in Figure 7 (b). Both the images are displayed on monitor using VGA controller. 37

9 VI. CONCLUSION AND FUTURE SCOPE The Fingerprint recognition process involves a series of image enhancement and minutiae extraction steps like Normalization, Orientation and field frequency estimation, Filtering, binarization, thinning, Minutiae extraction, and False minutiae elimination. Only the Normalization block is implemented on MatLab as well as on Virtex-II pro FPGA development board with verilog HDL. The simulation results obtained are satisfactory to carry out the further blocks of the fingerprint recognition process. The processing time will be in the order of nanoseconds in FPGA where as it is in terms of microseconds in Matlab. The result shows that the simulation of the normalization block is faster on FPGA. The hardware solution significantly reduces the processing time by almost 1000 time and the reduction in silicon area prompt to carry out remaining blocks of fingerprint recognition process. Further, it is suggested to integrate all the blocks of the Fingerprint recognition process on higher version of FPGA board to achieve better processing speed with reduced hardware resources. REFERENCES [1] Fingerprint Verification Competition 2004 (FVC2004). Available [2] Amira M saleh, Ayman M Bahaa Eldin, Abdel-moneim A Wahdam, A modified thinning algorithm for fingerprint identification systems, International conference on computer engineering and systems, 2009, pp [3] Sunny Arief Sudiro and Rudi Trisno Yuwono, Adaptable fingerprint minutiae extraction algorithm based-on crossing number method for hardware implementation using FPGA device.international Journal of Computer Science, Engineering and Information Technology (IJCSEIT), June 2012, Vol.2, No.3, pp [4] Ravi.J, Raja B K, and Venugopal K R Fingerprint recognition using minutia score matching, International Journal of Engineering Science and Technology,Vol.1(2), 2009, pp [5] Raymond Thai, Fingerprint image enhancement and minutiae extraction,- A report on fingerprint image restoration. [6] Byung-Gyu Kim, Han-Ju Kim and Dong-Jo Park, New Enhancement Algorithm for Fingerprint Images, IEEE, 2002, pp [7] Hui Xu, Yifan Qu, Yan Zhang, Feng Zhao, FPGA Based Parallel Thinning for Binary Fingerprint Image, chinese conference on pattern recognition, 2009, pp 1-4. [8] Krishna Kumar, Basant Kumar, Dharmendra Kuamr and Rachna Shah, Fingerprint Recognition using Minutiae Extraction, International Conference on ICT-Initiatives, Policies & Governance, Dehradun, India, Nov, 2011, pp 1-5. [9] Garcia.M.L and et al, FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor, FPL '06. international Conference on Field programmable logic and applications, Aug. 2006, pp 1 5. [10] Fengling wang and yuanyi Zhang, Study and Design of Intelligent Authentication System based on Fingerprint Identification, Second international Symposium on Knowledge acquisition and modeling, 2009, Vol.3, pp [11] Stephan Huckemann, Thomas Hotz, and Axel Munk, Global models for the orientation field of fingerprints: An approach based on quadratic differentials, IEEE transactions on pattern analysis and machine intelligence, September 2008, vol. 30, Issue no. 9, pp [12] Sung Bum pan, Daesung Moon, Kichul Kim, Yongwha Chung, A VLSI Implementation of Minutiae Extraction for Secure Fingerprint Authentication, International conference on computational Intelligence and security, 2006, Vol.2, pp [13] Mariano Fons, Francisco Fons, Enrique canto, Mariano Lopez, Flexible Hardware for Fingerprint Image Processing, 3 rd Conference on microelectronics and electronics, July 2-5, 2007, pp [14] Mariano Fons, Francisco Fons, Enrique canto, Approaching Fingerprint image Enhancement through Reconfigurable Hardware Accelerators, IEEE International symposium on Intelligent signal processing, 2007, pp 1-6. [15] Mariano Fons, Francisco Fons, Enrique canto, Fingerprint Image Processing Acceleration through run-time Reconfigurable Hardware, IEEE Transactions on circuits and systems II Express Briefs, December 2010, Vol.57, N0.12, pp [16] Ramaswamy Palaniappan, Dept of Engineering, School of Technology,University of Wolverhampton Telford. [17] Hong, Y.Wan, and A.K.Jain, Fingerprint image enhancement: Algorithm and performance evaluation, IEEE transactions, Machine intelligence, 1998, vol.20(8), pp