Experiences from the first step in designing an Architecture executing Executable UML semantics in Programmable Logic using VHDL
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1 Experiences from the first step in designing an Architecture executing Executable UML semantics in Programmable Logic using VHDL 1 SAAB BOFORS DYNAMICS Anders Eriksson Senior Software Systems Engineer Saab Bofors Dynamics, Linköping, Sweden
2 Contents Background FMV Funded Study VHDL Design The First Step Experiences 2 SAAB BOFORS DYNAMICS
3 Experiences from the Software Development with xuml presented in earlier presentation Software/Hardware co-design good and bad experiences Electronic and Software Engineers are working (reasonably) close together in projects Background Engineers should have an interest in both disciplines to a certain level System-wide perspective Experiences from System IV Communication handling timing requirements, Digital and analog decoding complex algorithms, timing, complex software design and processor loading When the above functionality is moved, the processor is free to concentrate on the calculation of the algorithms Difficult when no direct translation rules from xuml model to a VHDL implementation exists 3 SAAB BOFORS DYNAMICS
4 FMV Funded Study Technical studies can be funded by FMV to stimulate usage of new techniques in products from the defence industries in Sweden The department Centre of Expertise Sensors & Telecom within FMV where interested in finding a way of expressing the system without knowing the realisation. They were looking for Software Hardware Co-Design. During a visit at FMV, a presentation was held regarding our work with the Ada95 model compiler and how we can specify the system regarding software without thinking of the realisation A proposal for a study regarding Open code translation from Executable UML models to VHDL was then put together FMV = Swedish Defence Materiel Administration 4 SAAB BOFORS DYNAMICS
5 FMV Funded Study The primary goal was to investigate how to use the VHDL as a language to build an architecture that can take the xuml model to construction and not only to the simulation level First step Design the mechanisms necessary to fulfil the xuml model semantics Identify implementation patterns used when hand coding an xuml example model Investigate which constructs that are synthesisable in VHDL concerning the VHDL Language xuml model semantic How to partition the architecture Access Execution Libraries 5 SAAB BOFORS DYNAMICS
6 Example Model 6 SAAB BOFORS DYNAMICS
7 Example Model 7 SAAB BOFORS DYNAMICS
8 VHDL History VHDL can be used to describe a digital system at many levels of abstraction ranging from the algorithmic level to the gate level Can be seen as a super-set of Ada and with an extension called signals VHDL is an acronym for VHSIC Hardware Description Language. VHSIC is an acronym for Very High-Speed Integrated Circuits The main focus was to be able to write executable specifications for simulation and not for construction The construction was made by manually converting the models into schematics using gates and building blocks from a target library In the beginning of the 1990 s, VHDL synthesis tools that could convert VHDL models directly to a technology netlist started to emerge Synthesis can be compared to a compiler that generates machine code out of Ada95 code 8 SAAB BOFORS DYNAMICS
9 VHDL FPGA Implementation Flow VHDL Technology Library (Primitives) Constraints -Timing -Area Design Synthesis Netlist File Logical connection of primitives Constraints -Timing -Pin mapping -Floor plan Design Implementation Programming File Physical placement Routing of primitives Device Programming FPGA FPGA Field Programmable Gate Array 9 SAAB BOFORS DYNAMICS
10 VHDL The Language Design units in VHDL Entity Architecture Package Header Package Body Configuration (Simulation) Design partitioning with VHDL Block Package, Header + Body (optional) Component, Entity + Architecture Library Configuration (Simulation) Design modularity with VHDL Procedure Function Data types in VHDL Scalar (Enumeration, Integer, Real, ) Composite (Record, Array) 10 SAAB BOFORS DYNAMICS
11 Design The First Step Architecture structure, partitioning with VHDL Execution Communication between mechanisms Run-time monitoring Implementation issues 11 SAAB BOFORS DYNAMICS
12 Design Architecture Structure Library <FPGA TOP> Run-Time Monitoring Clock and Reset <DOM TOP 1> <DOM TOP 2> IO Pads Library <DOM TOP 1> Library <DOM 1>_SS <DOM 1>_SS <DOM 1> <DOM 1>_EE Library <DOM 1>_EE Library <DOM 1> Library <DOM 1>_<RELATIONSHIPS> <REL 1> Library <DOM 1>_<CLASS 1> <CLASS 1> <CLASS 2> Library OOD <H MECH 3> <H MECH 4> <G MECH 2> <G MECH 1> <H MECH 1> <H MECH 2> & : Generated VHDL G MECH : Generated Mechanism H MECH : Hand coded Mechanism SS : Synchronous Service EE : External Entity 12 SAAB BOFORS DYNAMICS
13 Active Class In Class events (Fifo) In External instance events (Fifo) Internal instance events (Fifo) Existing Instances Attribute Current State STT Instance based FSM_Executor Read/Write attribute STT Class based FSM_Preloader FSM_Postloader Generate signal Out Class and Instance operations Event Data Attribute Data Relationship navigation Class procedures Instance procedures Procedure_C# Procedure_C# Procedure_I# Procedure_I# 13 SAAB BOFORS DYNAMICS
14 Passive Class Read/Write attribute Existing Instances Attribute Generate signal Out Class and Instance operations Relationship navigation 14 SAAB BOFORS DYNAMICS
15 Relationships Out Related Instances Relationship Selections 15 SAAB BOFORS DYNAMICS
16 Design Execution One Instance per Class is executing at a time Instances from different classes are executing concurrently All instances within a class share the same state Procedures The following steps is performed during execution 1. Check Internal, External and Class Event Queue 2. If creation event, create instance 3. If instance based, check if instance exists 3.1 Get current state and evaluate STT 3.2 If transition Update current state with the new state FSM_Preloader Run the procedure for the new state FSM_Postloader FSM_Preloader Event Data FSM_Executer FSM_Postloader Attribute Data ( self ) 16 SAAB BOFORS DYNAMICS
17 Design Communication Between Mechanisms Every mechanism will follow the handshaking rules as follows Start_<Command>, Done_<Command> Request, Grant when more than one resource-user is attached Instance Procedure State_1 Class A 1 4 Attribute Access Portal Inside the procedures and operations the data types from the xuml model are used 3 2 Every external communication goes through a Portal where the typed data will be converted to a general address and data bus Every Class has several subprograms to support the address and data conversions Class B Attribute Memory 17 SAAB BOFORS DYNAMICS
18 Design Run-Time Monitoring All mechanisms and implementation patterns are prepared for runtime monitoring Different kind of monitoring categories Protocol Error hand shaking between mechanisms, Sizing event queue, instance table,... Inconsistent model navigating an association that is unconditional and no instance is related, Logging class state transitions, The run-time monitoring is configurable 18 SAAB BOFORS DYNAMICS
19 Data type Real is not supported Design Implementation Issues Inspired by A Structured VHDL Design Method written by Jiri Gaisler Named two-process method Combinational Process, the algorithm D Q Q = f q (D, r) Prescribes how to use the VHDL language to construct/code on a higher level than the traditional dataflow style The method is used in LEON3 A synthesisable VHDL model of a 32-bit processor compliant with the SPARC* V8 architecture r rin = f r (D, r) Two Process Schema Combinational (asynchronous) logic Sequential logic (register) State Machines Moore, Mealy, Lean (mix of Mealy and Moore) Increases abstraction level Improves readability Improves simulation speed * SPARC is a registered trademark of SPARC International Clk r = rin rin Sequential Process, the state The figure origins from the document 19 SAAB BOFORS DYNAMICS
20 Design Class Manipulation Creation and Deletion of Instances can be done Synchronously Asynchronously Only a fixed number of instances are available The information about existing instances is always available as read-only data for other mechanisms e.g. Relationships, FSM, Instance_Id = 3 Existing Instances Bit position Data type Instance_Set is coded as One-Hot, i.e. bit position corresponds to Instance_Id Instance_Set Representing No_Instance Selecting Instances Select Many - already available Select Any - first bit position set to one Where clause - executed by the receiver Cardinality(Instance_Set) = 2 Instance Exists 20 SAAB BOFORS DYNAMICS
21 Design Class Manipulation The Attribute memory is pre-created and the size is dependent on Total number of instances Bit-width of the data type of each attribute Exported Accesses Interface Reading and Writing attributes can be done simultaneously if not to same Address Attribute Memory The Address is composed of Instance_Id and Attribute_Name Mathematically-dependent attributes are treated as ordinary instance-based operations at the moment Attribute Access Portal Read/Write attribute 21 SAAB BOFORS DYNAMICS
22 Design Association Creation and deletion of associations has been designed Selections are designed All instances related are visible as read-only data and used by the Instance_Table Navigation is handled by the classes via a Navigator_Portal 22 SAAB BOFORS DYNAMICS
23 Design Event and Signal All instances of the same class share the same Event Queues Creation events are handled as ordinary events with an extra bit indicating creation Event data is coded and decoded by subprograms converting to and from a general data bus In In Class events (Fifo) External instance events (Fifo) Internal instance events (Fifo) The bit-width of the data bus is worst-case Maximum size of event data combinations Generating signals can be done immediately or delayed Signalling to other classes is handled by a Signal_Portal and follows the same principles as for attribute access and relationship navigation Signal Portal Generate signal Out 23 SAAB BOFORS DYNAMICS
24 Design State Procedure 24 Each action i.e. attribute access, relationship navigation, is divided into one or several VHDL state machines State transitions between actions are also following the handshaking principles with Start and Done Example for an attribute read access 1. Wait for Start 2. Use the subprogram to produce the address from Instance_Id and Attribute_Name 3. Wait for Done_Read 4. Assign the variable with the result from the subprogram converting the general data into the specific attribute type 5. Signal Done When working on self a local copy is used with exactly the attributes the Procedure is using The scope for variables is managed by the Block construction in VHDL SAAB BOFORS DYNAMICS
25 Experiences Design principles and patterns are finished Some of them are also implemented and tested Execution principles are designed as presented The workload is more on structural parts in a VHDL architecture than compared to the Ada95 architecture The effort has been to keep the coding of the Procedures as simple as possible, this is achieved via the different kinds of Portals Accesses Relationship Navigation 25 SAAB BOFORS DYNAMICS
26 Experiences These Portals can then be generated directly from the Interaction metamodel created from the first pass in the model compiler The VHDL model compiler uses the same information as the Ada95 model compiler Two worlds meeting Software and Hardware Same logical view but very different implementation issues Hardware engineers must understand the xuml semantics There is no information regarding Timing and Area usage at the moment 26 SAAB BOFORS DYNAMICS
27 Questions & Answers? 27 SAAB BOFORS DYNAMICS
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