3 Designing Digital Systems with Algorithmic State Machine Charts

Transcription

1 3 Designing with Algorithmic State Machine Charts An ASM chart is a method of describing the sequential operations of a digital system which has to implement an algorithm. An algorithm is a well defined sequence of steps that produces a desired sequence of actions and/or calculation results in response to a given sequence of control and data inputs. ASM charts are similar in appearance to flowcharts used in the early days of computer programming. Unlike the traditional flowchart the ASM chart includes timing information because it implicitly specifies that the FSM steps from one state to another only after each active clock edge. ASM charts are constructed of three elements. B. Schwarz 3-1

2 3.1 Graphical ASM Chart-Notations State entry path Entry path Entry path State name State code Unconditional (Moore) output list 0 Input 1 condition Conditional (Mealy) output list Exit path Exit false path Exit true path Exit path State box: A rectangle describes one state of the synchronous sequential digital system. It is similar to a circle representing a state of a state diagram. The main difference is that it only has one output transition (exit path). The state block symbol contains a listing of all unconditional actions and (Moore) outputs associated with that state. The outputs are updated concurrently when the state is entered after an active clock edge. Asserted signals are written as: Z which means Z = 1 B. Schwarz 3-2

3 Registered mathematical operations: COUNT COUNT + 1 ; MULT A * B The activated state will assert the enable signal which causes the counter to increment and the multiplier to operate a multiplicand and a factor. Registered signal assignments: INT_REG INPUT_1 REG C(4:0) concatenation. Condition symbol: A diamond shape contains the input condition on which depends the branching from a given state. It has one entry point and two exit path. Condition symbols can be concatenated. X means that the input signal X has to be tested. X1 X2 indicates that X1 = X2 = 1 has to be true. Conditional output box: An oval or rectangular with rounded edges represents an action, i.e. signal assignment or calculation, that is taken if an input condition is fulfilled. Conditional output boxes are only used to depict Mealy-type outputs. The entry path to the symbol is always from a decision symbol, but its exit path can be either to a state box or to another decision symbol. B. Schwarz 3-3

4 ASM Chart Representation of a Simple Moore-Type FSM Transformation of a state diagram X=0 Reset A Z=0 X=1 X=0 B Z=0 X=0 X=1 C Z=1 X=1 B. Schwarz 3-4

5 Reset Associated ASM chart for a Moore-Type FSM Output signals Z = 0 are not depicted in order to support transparency! B. Schwarz 3-5

6 ASM Chart Representation of a simple Mealy-Type FSM State diagram Reset X=1 / Z=0 X=0 / Z=0 A X=0 / Z=0 B X=1 / Z=1 It has to be checked which state is of Mooretype or Mealy-Type before transformation can be performed. B. Schwarz 3-6

7 Associated ASM Chart B. Schwarz 3-7

8 3.2 FSM as a Server's Polling Circuit A polling circuit for a client-server system with 3 clients has to determine which client is to be serviced by a server of many clients. A client i requests service by asserting its service-request flag Ri to the client. In each clock cycle the polling circuit polls its inputs Ri to determine whether service is being requested and to identify the requesting client having the highest priority. In general the client having the highest priority is to be serviced. As long as a client requests for service it will be granted by the polling circuit independently of other client requests. After a request flag Ri is deasserted the polling circuit will enter the polling state at least for one clock cycle. No other client's concurrently asserted request will change this FSM behaviour. B. Schwarz 3-8

9 Each client has a polling priority level: client0 > client1 > client2. The request Ri with the highest priority is granted by the polling circuit with the corresponding grant bit Gi. Only one bit Gi a time can be asserted. The FSM states are called: IDLE, GNT0, GNT1,GNT2. In IDLE state no Gi is asserted. Start with a block diagram and decide which FSM type will be appropriate. B. Schwarz 3-9

10 State Diagram for the Polling Circuit State G 2 G 1 G 0 R2, R1, R0 000 Idle Reset 100 x10 xx1 GNT2 GNT1 GNT0 B. Schwarz 3-10

11 State Diagram with Transition Conditions R 2 R 1 R 0 IDLE Reset R 2 R 1 R 0 R 0 R 1 R 1 R 0 GNT2 R 2 GNT1 R 0 GNT0 G 2 G 1 G 0 R 1 R 2 R 3 B. Schwarz 3-11

12 ASM Chart for the Polling Circuit Idle 0 1 GNT GNT GNT2 1 0 B. Schwarz 3-12

13 VHDL Code for the Polling Circuit -- Polling circuit: client arbiter entity arbiter is port( CLK, RESET : in bit; R: in bit_vector(2 downto 0); -- device requests G: out bit_vector(2 downto 0)); -- device grants end ARBITER; architecture BEHAVIOUR of ARBITER is type STATE_TYPE is (IDLE, GNT0, GNT1, GNT2); -- signal STATE, NEXT_STATE: STATE_TYPE; begin REG: process(clk, RESET) begin if RESET = '1' then STATE <= IDLE after 10 ns; elsif CLK='1' and CLK'event then STATE <= NEXT_STATE after 10 ns; -- present state update end process REG; B. Schwarz 3-13

14 COMB_LOGIC: process(state, R) begin G <= (others=>'0'); -- default output signals case STATE is when IDLE => if R(0) ='1' then NEXT_STATE <= GNT0 after 10 ns; elsif R(1) ='1' then NEXT_STATE <= GNT1 after 10 ns; elsif R(2) ='1' then NEXT_STATE <= GNT2 after 10 ns; else NEXT_STATE <= IDLE after 10 ns; when GNT0 => G(0) <= '1' after 10 ns; if R(0) ='1' then NEXT_STATE <= GNT0 after 10 ns; else NEXT_STATE <= IDLE after 10 ns; when GNT1 => G(1) <= '1' after 10 ns; if R(1) ='1' then NEXT_STATE <= GNT1 after 10 ns; else NEXT_STATE <= IDLE after 10 ns; B. Schwarz 3-14

15 when GNT2 => G(2) <= '1' after 10 ns; if R(2) ='1' then NEXT_STATE <= GNT2 after 10 ns; else NEXT_STATE <= IDLE after 10 ns; end case; end process; end BEHAVIOUR; Remark: The polling circuit will always return to the IDLE state for one clock cycle. New requests will be served after one IDLE state cycle. Redesign: Now the server must not serve the same client on two successive clock cycles if another client is requesting service. That means that if client1 is being served, the highestpriority-requesting client of lower priority is served next, if there is one. For example if client2 requests service while client1 is being served, it will be served next regardless of client1's request. The grant output is coded with two bits. B. Schwarz 3-15

16 Simulation Result for the Polling Circuit B. Schwarz 3-16

17 CPLD Implementation of the Polling Circuit (Xilinx XC95108 PC84) State encoding default for CPLDs: binary and sequential 2 D-flip-flops "STATE<0>" := "R<0>" * /"STATE<1>".LFBK + "R<2>" * "STATE<1>".LFBK * "STATE<0>".LFBK + "R<2>" * /"R<1>" * /"STATE<1>".LFBK * /"STATE<0>".LFBK "STATE<0>".CLKF = CLK "STATE<0>".RSTF = RESET "STATE<0>".PRLD = GND "STATE<1>" := "R<2>" * "STATE<1>".LFBK * "STATE<0>".LFBK + "R<1>" * /"R<1>" * /"STATE<0>".LFBK + "R<1>" * "STATE<1>".LFBK * /"STATE<0>".LFBK + "R<2>" * /"R<0>" * /"STATE<1>".LFBK * /"STATE<0>".LFBK "STATE<1>".CLKF = CLK "STATE<1>".RSTF = RESET "STATE<1>".PRLD = GND Output forming logic: "G<2>" = "STATE<0>" * "STATE<1>" "G<1>" = /"STATE<0>" * "STATE<1>" "G<0>" = /"STATE<1>".LFBK * "STATE<0>".LFBK Association of state bits and output signals to function blocks: STATE<0>: FB1/17 STATE<1>: FB1/18 G0: FB1/2 G1: FB3/2 G2: FB2/2 "Signal".LFBK describes a generated signal which is feed back to the same function block. B. Schwarz 3-17

18 FPGA Implementation Xilinx XC4013XL PQ160 B. Schwarz 3-18

19 Configurable Logic Block (CLB) B. Schwarz 3-19

20 3.3 Shift and Add Multiplier; Data and Control Path A binary multiplier has to be designed that will compute the 16 bit product of two 8 bit unsigned binary numbers. Decimal: 13 Multiplicand *11 Multiplier Product Product P The multiplication algorithm is developed by first examining the "pencil and paper" algorithm. Consider the product of (1101) 2 and (1011) 2 : Multiplier bits are examined sequentially from right to left. If the multiplier bit is 1, the partial product is the multiplicand, and if the multiplier bit is 0, the partial product is simply Each new partial product is shifted one bit position to the left before adding it to the total. Binary: 1101 Multiplicand A *1011 Multiplier B B. Schwarz 3-20

21 Pseudo code to describe the binary multiplication: P=0; for i=0 to n-1 do if Bi=1 then P = P+A; Shift left A; end for; The binary multiplication is based on a shift left register which has to be filled with the multiplicand A and successive adding of partial products. The for loop will be realized with a shift right of B for each shift left of A. The multiplication procedure will be started by a signal S after two new operands A and B have been loaded to registers with the signals LA and LB. The shift and add procedure is finished if the B shift register is filled up with zeros. This will be indicated with the signal DONE. B. Schwarz 3-21

22 ASM Chart for the Multiplier S1 Description of the Operation! S2 1 S B. Schwarz 3-22

23 Device interfacing: Design of the Multiplier Circuit -- NxN serial Multiplier library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- unsigned number representation entity MULTIPLIER is generic( N:integer:=8; NN:integer:=16); -- input width, output width port( CLK, RESET : in bit; LA, LB, S: in bit; -- load and start signal A,B: in std_logic_vector(n-1 downto 0); -- N-bit operands P: out std_logic_vector(nn-1 downto 0); -- result with double width DONE: out bit); -- status signal end MULTIPLIER; B. Schwarz 3-23

24 Partitioning of Digital Circuits At the beginning a digital systems design flow the digital circuit will be partitioned into the control logic and the data path section. It is appropriate to separate both parts because to each part different design strategies and optimisation methods can be applied. Data Input Data Path ALU Steering - Memory Data Output Status Control Signals State Register Control Input Next State and Output Forming Logic Control Unit Control Output B. Schwarz 3-24

25 Partitioning a Systems belongs to Architectural Synthesis Architectural synthesis means constructing a macroscopic structure of a digital hardware. The process starts with behavioural models that are described by mathematical equations and ASM charts. The first outcome of architectural synthesis is the structural view of the hardware as a combination of two components: Data path section and the control logic section. The data path section is an interconnection of resources which implement arithmetic and logic functions such as adders, multipliers, comparators, registers and steering logic (multiplexers and busses) as well. The control logic section consists of all logic required to generate control signals for ALU functions. It receives status signals from the data path and sends back control signals to the data path. Synchronous finite state machines usually build up the control unit. B. Schwarz 3-25

26 The second outcome of architectural synthesis is the placing of data path operations in time and place. That means determining the time interval for their execution and their binding to resources. The interconnections of the data path to the sequence of control unit operations have also to be determined. The final result will be a so called register transfer level (RTL) description of components which consist of register models interconnected by combinational logic elements. Typical HDL syntax elements which are used for this description style will be logic expressions (and, or) and behavioural decisions with if-then-else and case-when expressions. B. Schwarz 3-26

27 LA 0 A B n LB n EA SRG left EB SRG right CLK 2n n B_INT A_INT P_INT SUM 2n 2n PSEL Z B 0 EP MX_P 2n Register 2n Data path for the multiplier P B. Schwarz 3-27

28 The components of the multipliers data path serve following functions: A shift left register that holds the multiplicand A has a width of 2n bit. The upper n bits will be initialised with '0's and a '0' is shifted in from the right (LSB) end (comp. the paper and pencil example). A synchronous load of the shift left register is controlled by the LA signal. Shifting will be enabled by the EA signal. A 2n bit register holds the product P (result register). Partial products are stored under control of a clock enable input EP In combination with an 2n bit adder the result register builds an partial product accumulator. The result register P has to be initialised with zero in order to start with a second addend equal to zero. This is realised with a multiplexer in the registers input path. A select signal PSEL performs the channel switching. B. Schwarz 3-28

29 The multiplier B is stored in a n bit shift right register. Synchronous load is controlled by LB and shifting is enabled with EB. The LSB B 0 is a status signal. The product will be computed by adding the multiplicand to the current total in register P when the tested multiplier bit B 0 is 1. Instead of adding a partial product zero ( 2n '0's) to the total P when the multiplier bit '0' the addition step will simply be omitted. The end of multiplication is indicated by B = '0' i.e. with NOR gate output Z. B. Schwarz 3-29

30 VHDL Model for the Data Path architecture BHAVIOUR of MULTIPLIER is type STATE_TYPE is (S1, S2, S3); -- enumeration state type signal STATE, NEXT_STATE: STATE_TYPE; -- signal P_INT, SUM, MX_P: std_logic_vector(nn-1 downto 0); -- data path signals signal PSEL, Z, EA, EB, EP: bit; -- control- and status signals signal ZEROS: std_logic_vector(n-1 downto 0); signal B_INT: std_logic_vector(n-1 downto 0); -- multiplier shift right register signal A_INT: std_logic_vector(nn-1 downto 0); -- multiplicand shift left reg. begin -- ======================== data path ========================== ZEROS <= (others =>'0'); SHL_REG: process(clk) -- shift left register begin if CLK='1'and CLK'event then if EA ='1' then if LA = '1' then -- synchronousload A_INT <= ZEROS & A after 10 ns; else A_INT <= A_INT(NN-2 downto 0) & '0' after 10 ns; -- shift end process SHL_REG; B. Schwarz 3-30

31 SHR_REG: process(clk) -- shift right register begin if CLK='1'and CLK'event then if EB ='1' then if LB = '1' then -- synchronous load B_INT <= B after 10 ns; else B_INT <= '0' & B_INT(N-1 downto 1) after 10 ns; -- shift end process SHR_REG; MUX: process(sum, PSEL) -- multiplexer begin if PSEL = '0' then -- initialisation of result register MX_P <= (others=>'0') after 10 ns; else MX_P <= SUM after 10 ns; end process MUX; B. Schwarz 3-31

32 P_REG: process(clk) -- result register begin if CLK='1' and CLK'event then if EP='1' then P_INT <= MX_P after 10 ns; end process P_REG; ZERO_IND: process(b_int, ZEROS) begin if B_INT = ZEROS then Z <= '1' after 10 ns; else Z <= '0' after 10 ns; end process ZERO_IND; --zero indication in B -- concurrent assignment : SUM <= A_INT + P_INT after 10 ns; -- adder P <= P_INT; -- avoid buffer port mode B. Schwarz 3-32

33 S1 RESET S2 1 S3 1 0 Control unit of the multiplier 1 B. Schwarz 3-33

34 Comments on the Controller FSM State S1: Initialisation of P with zeros: PSEL='0' (default) and EP='1'. Both shift register will be loaded if input signals LA and LB indicate a new multiplicand A and a new multiplier B and start bit S is '0': Enable with EA and EB. A transition to state S2 takes place if the start bit S is asserted. State S2: Shifting in both input registers is enabled by asserted signals EA and EB. An adder result SUM is connected to the output register with select bit PSEL equals '1'. No adder result will be registered if the LSB B 0 is '0'. A transition to state S3 is prepared by Z='1' if all bits in input register B are zero. State S3: Output status signal DONE is asserted. A return to the idle state S1 is controlled by start bit S='0'. -- ========== control unit architecture continued ====================== FSM_REG: process(clk, RESET) -- state register begin if RESET = '1' then STATE <= S1 after 10 ns; elsif CLK='1' and CLK'event then STATE<= NEXT_STATE after 10 ns; end process FSM_REG; B. Schwarz 3-34

35 COMB_LOGIC: process(state, S, Z, LA, LB, B_INT(0)) begin EA<='0' after 10 ns; --default outputs avoid latches EB<='0' after 10 ns; EP<='0' after 10 ns; DONE<='0' after 10 ns; PSEL<='0' after 10 ns; case STATE is when S1 => EP <='1' after 10 ns; --Moore output PSEL <= '0' after 10 ns; if S='0' then NEXT_STATE <= S1 after 10 ns; if LA='1' then EA <= '1' after 10 ns; --Mealy if LB='1' then EB <= '1' after 10 ns; --output else NEXT_STATE <= S2 after 10 ns; when S2 => EA <= '1' after 10 ns; -- unconditional shift enable EB <= '1' after 10 ns; PSEL <= '1' after 10 ns; -- adder connected to register B. Schwarz 3-35

36 if Z='0' then NEXT_STATE <= S2 after 10 ns; if B_INT(0) = '1' then EP <= '1' after 10 ns; else NEXT_STATE <= S3 after 10 ns; when S3 => DONE <= '1' after 10 ns; -- unconditional signal assignment if S='1' then NEXT_STATE <= S3 after 10 ns; else NEXT_STATE <= S1 after 10 ns; end case; end process COMB_LOGIC; end BEHAVIOUR; B. Schwarz 3-36

37 VHDL Simulation Results of the Shift and Add Multiplier (0x64*0x19 = 0x9C4) B. Schwarz 3-37