1 Design Process HOME CONTENTS INDEX. For further assistance, or call your local support center

Transcription

1 1 Design Process VHDL Compiler, a member of the Synopsys HDL Compiler family, translates and optimizes a VHDL description to an internal gate-level equivalent. This representation is then compiled with the Synopsys Design Compiler Family to produce an optimized gate-level design in a given ASIC technology. Conversely, an existing technology-dependent gate-level description (such as a netlist) can be read by Design Compiler, then written out as a technology-independent VHDL description by VHDL Compiler. This translation capability is called reverse synthesis; it provides a powerful means of leveraging existing designs.

2 To work with VHDL, familiarize yourself with the following concepts: Hardware Description Languages About VHDL About VHDL Compiler Using VHDL Compiler with Design Compiler A Model of the Design Process VHDL Examples Design Problem VHDL Design Description Synthesizing the Example VHDL Design The United States Department of Defense, as part of its Very- High-Speed Integrated Circuit (VHSIC) program, developed VHSIC HDL (VHDL) in VHDL describes the behavior, function, and inputs and outputs of a digital circuit design. VHDL is similar in style and syntax to modern programming languages, but includes many hardware-specific constructs. Appendix A contains sample VHDL designs, with schematics of their synthesized circuits. VHDL Compiler reads and parses the supported VHDL syntax. Appendix C lists all VHDL constructs with the level of Synopsys support for each.

3 Hardware Description Languages Hardware description languages (HDLs) are used to describe the architecture and behavior of discrete electronic systems. HDLs were developed to deal with increasingly complex designs. An analogy is often made to the history of what can be called software description languages, from machine code (transistors and solder), to assembly language (netlists), to high-level languages (HDLs). Top-down, HDL-based system design is most useful in large projects, where several designers or teams of designers are working concurrently. HDLs provide structured development. After major architectural decisions have been made, and major components and their connections have been identified, work can proceed independently on subprojects. Typical Uses for HDLs HDLs typically support a mixed-level description where structural or netlist constructs can be mixed with behavioral or algorithmic descriptions. With this mixed-level capability, you can describe system architectures at a high level of abstraction; then incrementally refine a design into a particular component-level or gate-level implementation. Alternatively, you can read an HDL design description into the Synopsys Design Compiler, then direct the compiler to synthesize a gate-level implementation automatically.

4 Advantages of HDLs A design methodology that uses HDLs has several fundamental advantages over a traditional gate-level design methodology. Among the advantages are the following: You can verify design functionality early in the design process, and immediately simulate a design written as an HDL description. Design simulation at this higher level, before implementation at the gate-level, allows you to test architectural and design decisions. By using VHDL Compiler with Synopsys logic synthesis, you can automatically convert a VHDL description to a gate-level implementation in a given technology. This methodology eliminates the former gate-level design bottleneck and reduces circuit design time and errors introduced when hand-translating a VHDL specification to gates. With Synopsys logic optimization, you can automatically transform a synthesized design to a smaller or faster circuit. You can apply information gained from the synthesized and optimized circuits back to the VHDL description, perhaps to fine-tune architectural decisions. Synopsys Design Compiler, which is described in the, provides logic synthesis and optimization. HDL descriptions provide technology-independent documentation of a design and its functionality. An HDL description is more easily read and understood than a netlist or schematic description. Since the initial HDL design description is technology-independent, you can later reuse it to generate the design in a different technology, without having to translate from the original technology.

5 VHDL, like most high-level software languages, provides strong type checking. A component that expects a four-bit-wide signal type cannot be connected to a three- or five-bit-wide signal; this mismatch causes an error when the HDL description is compiled. If a variable s range is defined as 1 to 15, an error results from assigning it a value of 0. Incorrect use of types has been shown to be a major source of errors in descriptions. Type checking catches this kind of error in the HDL description even before a design is generated. About VHDL VHDL is one of just a few HDLs in widespread use today. VHDL is recognized as a standard HDL by the IEEE (IEEE Standard 1076, ratified in 1987) and by the United States Department of Defense (MIL STD 454L). VHDL divides entities (components, circuits, or systems) between an external or visible part (entity name and connections) and an internal or hidden part (entity algorithm and implementation). After you define the external interface to an entity, other entities can use that entity when they all are being developed. This concept of internal and external views is central to a VHDL view of system design. An entity is defined, with respect to other entities, by its connections and behavior. You can explore alternate implementations (architectures) of an entity without changing the rest of the design. After you define an entity for one design, you can reuse it in other designs as needed. You can develop libraries of entities for use by many designs, or for a family of designs. The VHDL model of hardware is shown in Figure 1 1.

6 Figure 1 1 VHDL Hardware Model Entity (Architecture) Process Process Ports Sequential Process wait... ; if A then X else Y end if; red, blue (Signals) 0 to 15 Combinational Process X and (Y xor Z); Subprogram Component A VHDL entity (design) has one or more input, output, or input-output ports that are connected (wired) to neighboring systems. An entity is itself composed of interconnected entities, processes, and components, all which operate concurrently. Each entity is defined by a particular architecture, which is composed of VHDL constructs such as arithmetic, signal assignment, or component instantiation statements. In VHDL, independent processes model sequential (clocked) circuits, such as flip-flops, and combinational (unclocked) circuits, such as AND or XOR gates. Processes can define and call (instantiate) subprograms (subdesigns). Processes communicate with each other by signals (wires).

7 A signal has a source (driver), one or more destinations (readers), and a user-defined type, such as color or number between 0 and 15. VHDL provides a broad set of constructs. With VHDL you can describe discrete electronic systems of varying complexity (systems, boards, chips, modules) with varying levels of abstraction. VHDL language constructs are divided into three categories by their level of abstraction: behavioral, dataflow, and structural. These categories are described as follows: behavioral The functional or algorithmic aspects of a design, expressed in a sequential VHDL process. dataflow The view of data as flowing through a design, from input to output. An operation is defined in terms of a collection of data transformations, expressed as concurrent statements. structural The view closest to hardware; a model where the components of a design are interconnected. This view is expressed by component instantiations.

8 About VHDL Compiler VHDL Compiler converts VHDL source code to an internal format used by the Synopsys Design Compiler. VHDL Compiler is accessed in dc_shell or Design Analyzer by executing elaborate and analyze. VHDL Compiler performs two functions: translating VHDL to an internal format, and optimizing the block level representation through various optimization methods. Design Compiler reads the design in internal format from VHDL Compiler, then optimizes and maps the design s logical structure for a specific ASIC technology library, as shown in Figure 1 2. Figure 1 2 VHDL Compiler Used with VHDL System Simulator (VSS) and Design Compiler VHDL Description VHDL System Simulator (functionality verification) VHDL Compiler (translation, block level optimization) ASIC Technology Library Design Compiler (logical optimizations, technology specific netlist /schematic)

9 A VHDL description is first simulated to verify design functionality, by using a VHDL simulator such as the Synopsys VSS Family (VSS Expert or VSS Professional). When analyzing VHDL design files for simulation you can use vhdlan spc to verify Synopsys synthesis policy. For more information, refer to the chapter on the VHDL Analyzer in the or the. VHDL Compiler is called by Design Compiler when you read in or write out a VHDL design. VHDL Compiler synthesizes VHDL descriptions according to the VHDL synthesis policy defined in Chapter 2, Description Styles. The Synopsys VHDL synthesis policy has three parts: design methodology, design style, and language constructs. You use the VHDL synthesis policy to produce high quality VHDLbased designs. Using VHDL Compiler with Design Compiler When VHDL Compiler reads a VHDL design, the design is converted to Design Compiler s internal database format. When Design Compiler performs logic optimization on a design, Design Compiler can restructure part or all of the design. You control the degree of restructuring. You can keep a design hierarchy intact, move modules up or down the design hierarchy, combine modules, or compress the entire design into one module.

10 After you are in Design Compiler, you can write out any design in a variety of formats, including VHDL. Existing gatelevel netlists, sets of logic equations, or technology-specific circuits can be automatically converted to a VHDL description. The new VHDL description can serve as documentation of the original design, and you can use it as a starting point for reimplementation into a new technology. In addition, you can give the VHDL description to a VHDL simulator to provide circuit timing information. A Model of the Design Process An example of a VHDL design session is described below. Starting with a VHDL description (source file), the example shows how to execute Design Compiler, read in and optimize a design, view its schematic, and write out the optimized circuit description. Figure 1 3 illustrates a typical design flow that uses VHDL Compiler, Design Compiler, and your VHDL simulator.

11 Figure 1 3 Design Flow that Uses VHDL Compiler 1 VHDL Description 4 2 Synopsys VHDL Compiler VHDL Driver 5 Synopsys Design Compiler 6 VHDL Gate- Level Description 3 7 VHDL Simulator VHDL Simulator Simulation Output 8 Compare Output Simulation Output The steps in Figure 1 3 are explained below. 1. Write a design description in the VHDL language. This description can be a combination of structural and functional elements (as shown in Chapter 2, Description Styles ). This description is used with both the Synopsys VHDL Compiler and your VHDL simulator.

12 2. Provide VHDL-language test drivers for your VHDL simulator. These drivers supply test vectors for the simulation and gather output data. 3. Simulate the design by using your VHDL simulator to verify the accuracy of the description. 4. Synthesize the VHDL description with VHDL Compiler. VHDL Compiler performs architectural optimizations, then creates an internal representation of the design. 5. Use the Synopsys Design Compiler to produce an optimized gate-level description in the target ASIC library. You can optimize the generated circuits to meet the timing and area constraints you want. This optimization step must follow the translation step (step 4) to produce an efficient design. 6. Use the Synopsys Design Compiler to output a gate-level VHDL description. This netlist-style description uses ASIC components as the leaf-level cells of the design. The gate-level description has the same port and module definitions as the original high-level VHDL description. 7. Pass the gate-level VHDL description from step 6 through your VHDL simulator. You can use the VHDL simulation drivers from Step 2 because module and port definitions are preserved through the translation and optimization processes. 8. Compare the output of the gate-level simulation (step 7) against the output of the original VHDL description simulation (step 3) to verify that the implementation is correct.

13 VHDL Example The example that follows is called Count Zeros Sequential Version, and is taken from Appendix A. The next three sections contain A description of the design problem (count the number of zeros in a sequentially input eight-bit value). A listing of a VHDL design description. A step-by-step description of how to read in the VHDL design description, how to compile (synthesize) the circuit, how to view the resulting schematic, and how to write out the synthesized circuit description as a VHDL file. Design Problem The Count Zeros example illustrates a design problem where an eight-bit value is given and the circuit determines Exactly one sequence of 0s is in the value. The number of 0s in that sequence (if any). A valid value can have no more than one series of consecutive zeros. A value consisting entirely of 1s is defined as a valid value. If a value is invalid, the zero counter is reset to zero. For example, value is valid and has eight zeros; value is valid and has three zeros; value is not valid.

14 The circuit accepts the eight-bit data value serially, one bit per clock cycle, by using the DATA and CLK inputs. The other two inputs are RESET, which resets the circuit (synchronous reset). READ, which causes the circuit to begin accepting data bits and continue to accept data bits. The circuit s three outputs are IS_LEGAL, which is TRUE if the data was a valid value. COUNT_READY, which is TRUE at the first invalid bit or when all eight bits have been processed. COUNT, the number of zeros (if IS_LEGAL is TRUE). The output port COUNT is declared with mode BUFFER, so that it can be read inside the process. OUT ports can only be written to, not read. Note: The pathname of the VHDL source file for this example is /synopsys/doc/syn/examples/vhdl/cnt seq/cnt seq.vhd, where /synopsys is the name of your Synopsys root directory. VHDL Design Description Example 1 1 shows the VHDL source description for the Count Zeroes circuit. Example 1 1 VHDL Design Source File entity COUNT_SEQ_VHDL is port(data, CLK: in BIT; RESET, READ: in BOOLEAN; COUNT: buffer INTEGER range 0 to 8; IS_LEGAL: out BOOLEAN; COUNT_READY: out BOOLEAN); end;

15 architecture BEHAVIOR of COUNT_SEQ_VHDL is begin process variable SEEN_ZERO, SEEN_TRAILING: BOOLEAN; variable BITS_SEEN: INTEGER range 0 to 7; begin wait until CLK event and CLK = 1 ; if (RESET) then COUNT_READY <= FALSE; IS_LEGAL <= TRUE; Signal assignment SEEN_ZERO := FALSE; Variable assignment SEEN_TRAILING := FALSE; COUNT <= 0; BITS_SEEN := 0; else if (READ) then if (SEEN_TRAILING and DATA = 0 ) then IS_LEGAL <= FALSE; COUNT <= 0; COUNT_READY <= TRUE; elsif (SEEN_ZERO and DATA = 1 ) then SEEN_TRAILING := TRUE; elsif (DATA = 0 ) then SEEN_ZERO := TRUE; COUNT <= COUNT + 1; end if; if (BITS_SEEN = 7) then COUNT_READY <= TRUE; else BITS_SEEN := BITS_SEEN + 1; end if; end if; end if; end process; end BEHAVIOR; if (READ) if (RESET)

16 Synthesizing the VHDL Design To synthesize a circuit from the VHDL design example, use Design Analyzer and follow these steps: 1. Start Design Analyzer by entering the following command at your UNIX prompt (%): % design_analyzer & The main Design Analyzer window appears as shown in Figure 1 4. Figure 1 4 Initial Design Analyzer Window

17 2. Set your target library and the associated link and symbol libraries. For this example, use the generic Synopsys class library. Move the cursor to Setup, then click the left mouse button to bring up the Setup menu. Click on Defaults... to bring up the Setup/Defaults dialog. Add the Synopsys-supplied library directory name / synopsys/libraries/syn to the end of the Search Path field. Set the Link Library, Target Library, and Symbol Library fields as shown in Figure 1 5. Click on OK to set these default values. Figure 1 5 Setup/Defaults Window

18 Click on Cancel to remove the Variables dialog. 3. Analyze the VHDL source file; use the File/Analyze dialog.

19 Enter the directory name /synopsys/doc/syn/examples/ vhdl/cnt seq/ in the File Name field and click on OK. An Analyze window appears with a design_analyzer prompt. Click on CANCEL.

20 4. Elaborate the VHDL source file by using the File/Elaborate dialog. The Elaborate Design window appears. Enter the library name WORK in the Library field. Enter the design name COUNT_SEQ_VHDL (BEHAVIOR) in the Design field. Click OK.

21 An Elaborate window opens to show the status messages and inferred devices (see Register and Three- State Inference in Chapter 8) produced by VHDL Compiler. After you have reviewed the VHDL report, click on Cancel to remove the report window.

22 5. The design has now been read into memory and translated to an internal (equation-based) format, indicated by the symbol Y=A+B. The Design Analyzer window now shows the design s icon and name (COUNT_SEQ_VHDL).

23 6. Click on the design icon to select it, then click on the down-arrow button (left side of window) to generate and display the symbol view of the design.

24 7. Set a constraint for the design. Ask for the minimum area by using the Attributes/Optimization Constraints/Design Constraints selection.

25 The Design Constraints dialog box appears. Click Apply then Cancel.

26 8. Look at the initial (HDL-level) schematic. Click on the schematic view icon. 9. You can see the ports and gates produced by VHDL Compiler from the VHDL description by using HDL Advisor. For more information, see the HDL Advisor User Guide.

27 10.Compile the design by using the Tools/Design Optimization dialog. Use the default settings and click on OK to start the compilation. Delay

28 A Compile Log report window shows the compilation status. After you review the report, click on Cancel to remove the window.

29 11.Display the schematic for the design by clicking on the Schematic View button (small AND gate). At this point, you can explore the design by using Design Analyzer. You can see the critical path, get timing information, highlight all cells or references of a given type, change circuit constraints, group and ungroup subsets of the circuit, and get a variety of reports. See the for complete information.

30 12.Write out the design by using the File/Save As dialog. Enter the new filename in the File Name field, for example, example.vhdl. Choose the output format you want from the File Format list; in this case, VHDL netlist output format.

31 13.Quit Design Analyzer by using the File/Quit dialog. Click on OK to exit Design Analyzer, or Cancel to remove this dialog. The screen is locked when this dialog is displayed.