Outline. CPE/EE 422/522 Advanced Logic Design L05. Review: General Model of Moore Sequential Machine. Review: Mealy Sequential Networks.
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1 Outline CPE/EE 422/522 Advanced Logic Design L05 Electrical and Computer Engineering University of Alabama in Huntsville What we know Combinational Networks Sequential Networks: Basic Building Blocks, Mealy & Moore Machines, Max Frequency, Setup & Hold Times, Synchronous Design What we do not know Equivalent states and reduction of state tables Hardware Description Languages 11/06/200 UAH-CPE/EE 422/522 AM 2 Review: Mealy Sequential Networks General model of Mealy Sequential Network Review: General Model of Moore Sequential Machine s depend only on present state! Combinational Network s(z) s(x) Combinational Network Next State State Register State(Q) Clock (1) X inputs are changed to a new value (2) After a delay, the Z outputs and next state appear at the output of CM () The next state is clocked into the state register and the state changes X = x 1 x 2... x n + Q ( t ) = G ( X ( t ), Q ( t )) Q = Q 1 Q 2... Q k Z ( t ) = F( Q ( t )) Z = z 1 z 2... z m 11/06/200 UAH-CPE/EE 422/522 AM 11/06/200 UAH-CPE/EE 422/522 AM 4 Intro to VHDL Technology trends 1 billion transistor chip running at 20 GHz in 2007 Need for Hardware Description Languages Systems become more complex Design at the gate and flip-flop level becomes very tedious and time consuming HDLs allow Design and debugging at a higher level before conversion to the gate and flip-flop level Tools for synthesis do the conversion VHDL, Verilog VHDL VHSIC Hardware Description Language 11/06/200 UAH-CPE/EE 422/522 AM 5 Intro to VHDL Developed originally by DARPA for specifying digital systems International IEEE standard (IEEE ) Hardware Description, Simulation, Synthesis Provides a mechanism for digital design and reusable design documentation Support different description levels Structural (specifying interconnections of the gates), Dataflow (specifying logic equations), and Behavioral (specifying behavior) Top-down, Technology Dependent 11/06/200 UAH-CPE/EE 422/522 AM 6 1
2 VHDL Description of Combinational Networks Entity-Architecture Pair Full Adder Example 11/06/200 UAH-CPE/EE 422/522 AM 7 11/06/200 UAH-CPE/EE 422/522 AM 8 VHDL Program Structure 4-bit Adder 11/06/200 UAH-CPE/EE 422/522 AM 9 11/06/200 UAH-CPE/EE 422/522 AM 10 4-bit Adder (cont d) 4-bit Adder - Simulation 11/06/200 UAH-CPE/EE 422/522 AM 11 11/06/200 UAH-CPE/EE 422/522 AM 12 2
3 Modeling Flip-Flops Using VHDL Processes General form of process Concurrent Statements vs. Process A, B, C, D are integers A=1, B=2, C=, D=0 D changes to 4 at time 10 Whenever one of the signals in the sensitivity list changes, the sequential statements are executed in sequence one time time delta A B C D (stat. exe.) (stat. 2 exe.) (stat. 1 exe.) (no exec.) Simulation Results 11/06/200 UAH-CPE/EE 422/522 AM 1 11/06/200 UAH-CPE/EE 422/522 AM 14 D Flip-flop Model JK Flip-Flop Model Bit values are enclosed in single quotes 11/06/200 UAH-CPE/EE 422/522 AM 15 11/06/200 UAH-CPE/EE 422/522 AM 16 JK Flip-Flop Model Using Nested IFsand ELSEIFs 11/06/200 UAH-CPE/EE 422/522 AM 17 11/06/200 UAH-CPE/EE 422/522 AM 18
4 VHDL Models for a MUX MUX Models (1) If a MUX model is used inside a process, the MUX can be modeled using a CASE statement (cannot use a concurrent statement): Sel represents the integer equivalent of a 2-bit binary number with bits A and B library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( downto 0); Y : out std_logic); end SELECTOR; architecture RTL1 of SELECTOR is p0 : process (A, SEL) if (SEL = "0000") then Y <= A(0); elsif (SEL = "0001") then Y <= A(1); elsif (SEL = "0010") then Y <= A(2); elsif (SEL = "0011") then Y <= A(); elsif (SEL = "0100") then Y <= A(4); elsif (SEL = "0101") then Y <= A(5); elsif (SEL = "0110") then Y <= A(6); elsif (SEL = "0111") then Y <= A(7); elsif (SEL = "1000") then Y <= A(8); elsif (SEL = "1001") then Y <= A(9); elsif (SEL = "1010") then Y <= A(10); elsif (SEL = "1011") then Y <= A(11); elsif (SEL = "1100") then Y <= A(12); elsif (SEL = "1101") then Y <= A(1); elsif (SEL = "1110") then Y <= A(14); else Y <= A(15); end if; end process; end RTL1; 11/06/200 UAH-CPE/EE 422/522 AM 19 11/06/200 UAH-CPE/EE 422/522 AM 20 MUX Models (2) MUX Models () library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( downto 0); Y : out std_logic); end SELECTOR; architecture RTL of SELECTOR is with SEL select Y <= A(0) when "0000", A(1) when "0001", A(2) when "0010", A() when "0011", A(4) when "0100", A(5) when "0101", A(6) when "0110", A(7) when "0111", A(8) when "1000", A(9) when "1001", A(10) when "1010", A(11) when "1011", A(12) when "1100", A(1) when "1101", A(14) when "1110", A(15) when others; end RTL; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( downto 0); Y : out std_logic); end SELECTOR; architecture RTL2 of SELECTOR is p1 : process (A, SEL) case SEL is when "0000" => Y <= A(0); when "0001" => Y <= A(1); when "0010" => Y <= A(2); when "0011" => Y <= A(); when "0100" => Y <= A(4); when "0101" => Y <= A(5); when "0110" => Y <= A(6); when "0111" => Y <= A(7); when "1000" => Y <= A(8); when "1001" => Y <= A(9); when "1010" => Y <= A(10); when "1011" => Y <= A(11); when "1100" => Y <= A(12); when "1101" => Y <= A(1); when "1110" => Y <= A(14); when others => Y <= A(15); end case; end process; end RTL2; 11/06/200 UAH-CPE/EE 422/522 AM 21 11/06/200 UAH-CPE/EE 422/522 AM 22 MUX Models (4) Compilation and Simulation of VHDL Code library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( downto 0); Y : out std_logic); end SELECTOR; architecture RTL4 of SELECTOR is Y <= A( conv_integer(sel)); end RTL4; Compiler (Analyzer) checks the VHDL source code does it conforms with VHDL syntax and semantic rules are references to libraries correct Intermediate form used by a simulator or by a synthesizer Elaboration create ports, allocate memory storage, create interconnections,... establish mechanism for executing of VHDL processes 11/06/200 UAH-CPE/EE 422/522 AM 2 11/06/200 UAH-CPE/EE 422/522 AM 24 4
5 Timing Model VHDL uses the following simulation cycle to model the stimulus and response nature of digital hardware Start Simulation Delay Delay Types All VHDL signal assignment statements prescribe an amount of time that must transpire before the signal assumes its new value This prescribed delay can be in one of three forms: Transport -- prescribes propagation delay only Inertial -- prescribes propagation delay and minimum input pulse width Delta -- the default if no delay time is explicitly specified Update Signals Execute Processes delay End Simulation 11/06/200 UAH-CPE/EE 422/522 AM 25 11/06/200 UAH-CPE/EE 422/522 AM 26 Transport Delay Transport delay must be explicitly specified I.e. keyword TRANSPORT must be used Signal will assume its new value after specified delay -- TRANSPORT delay example <= TRANSPORT NOT AFTER 10 ns; Inertial Delay Provides for specification propagation delay and input pulse width, i.e. inertia of output: target <= [REJECT time_expression] INERTIAL waveform; Inertial delay is default and REJECT is optional: <= NOT AFTER 10 ns; -- Propagation delay and minimum pulse width are 10ns /06/200 UAH-CPE/EE 422/522 AM /06/200 UAH-CPE/EE 422/522 AM 28 Inertial Delay (cont.) Example of gate with inertia smaller than propagation delay e.g. Inverter with propagation delay of 10ns which suppresses pulses shorter than 5ns <= REJECT 5ns INERTIAL NOT AFTER 10ns; Note: the REJECT feature is new to VHDL /06/200 UAH-CPE/EE 422/522 AM 29 Delta Delay Default signal assignment propagation delay if no delay is explicitly prescribed VHDL signal assignments do not take place immediately Delta is an infinitesimal VHDL time unit so that all signal assignments can result in signals assuming their values at a future time E.g. <= NOT ; -- assumes new value in one delta cycle Supports a model of concurrent VHDL process execution Order in which processes are executed by simulator does not affect simulation output 11/06/200 UAH-CPE/EE 422/522 AM 0 5
6 Simulation Example 11/06/200 UAH-CPE/EE 422/522 AM 1 Using the labels, list the order in which the following signal assignments are evaluated if in2 changes from a '0' to a '1'. Assume in1 has been a '1' and in2 has been a '0' for a long time, and then at time t in2 changes from a '0' to a '1'. Problem #1 entity not_another_prob is port (in1, in2: in bit; a: out bit); end not_another_prob; architecture oh_behave of not_another_prob is end oh_behave; signal b, c, d, e, f: bit; L1: d <= not(in1); L2: c<= not(in2); L: f <= (d and in2) ; L4: e <= (c and in1) ; L5: a <= not b; L6: b <= e or f; 11/06/200 UAH-CPE/EE 422/522 AM 2 Problem #2 Under what conditions do the two assignments below result in the same behavior? Different behavior? Draw waveforms to support your answers. Modeling a Sequential Machine Mealy Machine for 8421 BCD to 8421 BCD + bit serial converter out <= reject 5 ns inertial (not a) after 20 ns; out <= transport (not a) after 20 ns; How to model this in VHDL? 11/06/200 UAH-CPE/EE 422/522 AM 11/06/200 UAH-CPE/EE 422/522 AM 4 Behavioral VHDL Model Simulation of the VHDL Model Simulation command file: Waveforms: Two processes: the first represents the combinational network; the second represents the state register 11/06/200 UAH-CPE/EE 422/522 AM 5 11/06/200 UAH-CPE/EE 422/522 AM 6 6
7 Dataflow VHDL Model Structural Model + Q ( t ) = Q 1 Q ( t ) = Q Q ( t ) = Q 1 Q 2 Q Z = X ' Q ' + XQ X ' Q Q ' + X ' Q ' Q ' Package bit_pack is a part of library BITLIB includes gates, flip-flops, counters (See Appendix B for details) 11/06/200 UAH-CPE/EE 422/522 AM 7 11/06/200 UAH-CPE/EE 422/522 AM 8 Simulation of the Structural Model Simulation command file: Waveforms: Wait Statements... an alternative to a sensitivity list Note: a process cannot have both wait statement(s) and a sensitivity list Generic form of a process with wait statement(s) process sequential-statements wait statement sequential-statements wait-statement... end process; How wait statements work? Execute seq. statement until a wait statement is encountered. Wait until the specified condition is satisfied. Then execute the next set of sequential statements until the next wait statement is encountered.... When the end of the process is reached start over again at the ning. 11/06/200 UAH-CPE/EE 422/522 AM 9 11/06/200 UAH-CPE/EE 422/522 AM 40 Forms of Wait Statements Using Wait Statements (1) wait on sensitivity-list; wait for time-expression; wait until boolean-expression; Wait on until one of the signals in the sensitivity list changes Wait for waits until the time specified by the time expression has elapsed What is this: wait for 0 ns; Wait until the booleanexpression is evaluated whenever one of the signals in the expression changes, and the process continues execution when the expression evaluates to TRUE 11/06/200 UAH-CPE/EE 422/522 AM 41 11/06/200 UAH-CPE/EE 422/522 AM 42 7
8 Using Wait Statements (2) To Do Read Textbook chapters 2.1, /06/200 UAH-CPE/EE 422/522 AM 4 11/06/200 UAH-CPE/EE 422/522 AM 44 8
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