JHDLBits: The Merging of Two Worlds

Transcription

1 JHDLBits: The Merging of Two Worlds Alexandra Poetter 1, Jesse Hunter 1, Cameron Patterson 1, Peter Athanas 1, Brent Nelson 2, and Neil Steiner 1 1 Configurable Computing Lab, Virginia Tech, Blacksburg, VA 24061, USA {apoetter, jehunte3, cdp, athanas, nsteiner}@vt.edu, 2 Configurable Computing Lab, Brigham Young University, Provo, UT 84602, USA nelson@ee.byu.edu Abstract. This paper introduces JHDLBits, the integration of two prominent FPGA design tools: JHDL and JBits. JHDLBits offers the low-level access and control provided by JBits with the high-level structural circuit design of JHDL. Furthermore, the JHDLBits flow provides greater control of resource manipulation, placement, and routing, and gives researchers a sandbox to explore advanced interactions with FPGA bitstreams. This paper presents the overall architecture of the open-source JHDLBits project. Details are provided on how the core components - JHDL, JBits3 for Virtex-II, and the ADB connectivity database - are linked together to provide a cohesive design environment. 1 Introduction Investigators involved in FPGA-related research often require a testbed for exploring and evaluating new tools, new algorithms, and new ways to interact with FPGA bitstreams. Historically, this has often proven to be a difficult task. Exceptional exploratory environments have been created, such as VPR by Betz and Rose [1] that provide realistic models of FPGAs. With the infrastructure created by VPR, researchers could determine the effects of, for example, placement enhancements on wire length. The relevance of such exploration was sometimes diminished since the results from the experimental environment could not be definitively confirmed on a real FPGA since FPGA vendors tend to be secretive on the low-level architectural details of their products. Many languages, IDEs, and compilers have emerged in recent years that offer interesting environments for creating FPGA bitstreams, but most rely on the FPGA vendors implementation flows to map, place, and route the final design. The authors of JBits [2] addressed this problem to a certain degree by providing an API to the FPGA bitstream. As a result, researchers were empowered with the ability to manipulate FPGA resources at the lowest level. With JBits, researchers could develop, say, their own FPGA router, and test it on real devices. JBits also enabled researchers to interact with FPGAs in ways prohibited by the vendor s prescribed implementation tool flow. While JBits was in many ways an enabling technology for exploring nontraditional uses of FPGAs, the abstraction presented to the developer was at a

2 fairly low level (at least in early versions of JBits), and sometimes required detailed architectural knowledge. In contrast to this, tools such as Brigham Young s JHDL [3] use a much higher level of abstraction, often making it a more conducive environment for large application development. JHDLBits is an open-source endeavor striving to merge the salient features of these two prominent FPGA research environments. JHDLBits blends the lowlevel control of JBits with the high-level design abstractions of JHDL. Users can take advantage of the run-time and partial reconfiguration features of JBits without having to work entirely at the bitstream level. Furthermore, full control over placement and routing is still possible. The JHDLBits project consists of a collection of tightly integrated components that together provide an end-toend pathway for creating, manipulating, and debugging FPGA bitstreams. More importantly, because most of the components of this project are open-source, researchers investigating architecture-specific placers/planners/routers/compilers have the advantage of replacing the stock JHDLBits components at will. JHDLBits integrates JBits low-level bit manipulation capabilities into the JHDL integrated development environment. The extensible JHDL netlister has been modified to produce bitstreams directly. The JHDL debugger communicates to a target FPGA through JBits XHWIF [4]. JHDL is naturally extended so that instead of generating an EDIF file, which is run through the traditional vendor tools to generate a bitstream, the primitive and net information is extracted into a database that is suitable for JBits to process. A bitstream is created by elaborating, placing, and routing the corresponding JBits primitives all within the JHDLBits environment. Figure 1 illustrates the components that collectively make up the JHDLBits project. Fig. 1. Relationships of the open source constituents of JHDLBits This paper presents the overall architecture of the JHDLBits project. Details are provided on how the core components - JHDL, JBits3 for Virtex-II, and the

3 ADB connectivity database [5] - are linked together to provide a cohesive design environment. Sections 2, 3, and 4 provide background information on JHDL, JBits, and ADB, respectively. Section 5 introduces the FPGA device simulator that can be used to verify the JHDLBits design. The architecture of JHDLBits is discussed in Section 6. A JHDLBits design implementation and results are included in Section 7 and Appendix A. 2 JHDL JHDL is a Java-based design language for FPGAs developed at Brigham Young University. Java was selected because it is object-oriented, easy to use, has builtin documentation capabilities, is portable, and has a rich set of GUI APIs that are integral to the language. The primary distinction of JHDL is the creation of a single integrated API that allows the designer to express circuit organizations that dynamically change over time [3]. JHDL [10] is a structural HDL - that is, circuits are described by structurally instantiating lower-level building blocks. In JHDL, two basic Java classes form the basis for all circuits: Logic and Wire. Designers create a new logic cell in their design by extending Logic (creating a new class), defining a cell interface (essentially a VHDL entity declaration), and defining the architecture of the cell (essentially a VHDL architecture body). Wires support an API for creation and manipulation: users can create single- or multi-bit wires, and concatenate or extract wires from existing wires. The body of a design instantiates predefined circuit modules selected from the JHDL design libraries. The JHDL design libraries were created in a layered fashion and range from a library of Xilinx primitives such as gates and flip flops, to parameterized logic generator methods, to technology-independent and technology-specific module generators for the creation of larger elements (such as counters, memories, floating point arithmetic modules, CORDIC units, FFTs). JHDL circuit descriptions are based on Java; thus the full range of Java language features are available to construct the circuit. These features include file I/O, recursion, control flow constructs (for, while, do loops), functions, user-defined types (objects), and reflection. A key feature of JHDL is its ability to operate in either simulation or hardware mode. When in simulation mode, the values of all elements in the circuit data structure are computed by the JHDL simulator. However, JHDL also supports a hardware-in-the-loop mode of execution. In this case, starting execution of the circuit downloads a bitstream to the FPGA platform, and stepping the clock triggers a clock step on the actual hardware. Between clock steps, bitstream readback extracts the hardware state, which is back annotated into the circuit data structure for graphical display. As a result, the same GUI interface and tools can be used for debugging in either in simulation mode or hardware execution mode. This simplifies the transition from simulation to hardware debug, and streamlines the development process. Figure 2 presents a screen capture of the JHDL GUI.

4 Fig. 2. JHDL graphical user interface screen shot 3 JBits Background and Enhancements JBits is a collection of Java classes that build upon an API that provides access to every configurable resource in a Xilinx FPGA. The JBits3 SDK [9] is the latest release from Xilinx that provides support for the Virtex-II FPGA family. This API permits device resources to be programmed and probed individually at run-time, even with the FPGA active in a working system. This interface operates on either bitstreams generated by Xilinx design tools, or on bitstreams read back from actual hardware. Through this mechanism, JBits supports the run-time reconfiguration of Xilinx FPGAs. For JHDL to function with JBits, several extensions and enhancements were needed. A bridging object, called the Bitstream class, was created to allow abstract access to both the JBits and router objects, enabling the creation of primitives without dependencies on architecture-specific classes. The Net class was extended to allow the connection of primitives by maintaining a list of the source and sink pins that form a net. To bridge the gap between JHDL and JBits, a library of primitive cores was created that map the JHDL primitives directly to the FPGA fabric. For completeness, each JHDL primitive requires a corresponding JBits primitive. The primitives created for JHDLBits have one constructor specifically designed for the JHDL-to-JBits flow, with the other constructors catering to a JBits-only

5 design flow. A primitive requires two pieces of information to be implemented: a list of input and output nets, and placement information. The primitive uses the placement location to assign source and sink pins to the associated nets, and then accesses the JBits object from the Bitstream class to configure the internal logic and resources using JBits calls. 4 ADB Background ADB is an alternate wire database for Xilinx Virtex, Virtex-E, Virtex-II, and Virtex-II Pro FPGAs [6]. Its purpose is to provide exhaustive coverage of device wiring and connectivity, while remaining fast, compact, and compatible with JBits. The exhaustive coverage is derived from the same proprietary data that the Xilinx mainstream tools use, and presents an improvement over the coverage available in past and present JBits wire databases. In addition, the database files used by ADB are more than an order of magnitude smaller than their counterparts in the mainstream tools. Although ADB is primarily a wire database, it also includes support services for routing, unrouting, and tracing. These interfaces are publicly exposed, so they can be extended or replaced as necessary by the user. An ADB-based router is included with JHDLBits, and is based on a robust search algorithm enhanced with heuristics suited to each FPGA family. The unrouter provides services not normally found in static tool flows, by allowing the user to disconnect existing nets, in order to reconnect other nets at runtime. This may be especially useful in embedded systems that have to dynamically reconfigure themselves [7]. The tracer may also be used to support reconfiguration, by inferring connectivity information from a configuration bitstream, in order to safely modify designs without causing contention. Because JBits 3.0 ships without a router, ADB currently provides the only routing option available to JBits users. However, ADB may also be of interest to researchers wanting to evaluate routing algorithms with wiring data from commercial FPGAs. In the context of JHDLBits, the ADB router simply implements RouterInterface as defined by JBits, which makes it reasonable to plug ADB into the project without concern for its inner workings. 5 FPGA Device Simulator Included in the JHDLBits project is the design of a Virtex-II device simulator (VTsim) [11]. Initially, a functional simulator has been created using a globally synchronous event-driven model with CLB granularity. The simulator can be used as part of the JHDLBits design flow, but can also function independently because it only requires a bitstream as input. The simulator first invokes the ADB tracer on the bitstream to be simulated. After the tracer builds a database of all internal connections, the simulator constructs the netlist from this information. An optional JHDLBits simulation file can be used to provide the simulator with specific information such as net

6 z z names and placement information. A simulation cycle begins with the evaluation of all clocked elements within the CLBs, followed by the evaluation of all nonclocked elements. Upon completion of a simulation cycle, the simulator can either write the updated results back to a bitstream, or allow GUI access to the modified information. It should be noted that this simulator can simulate any Virtex-II bitstream, regardless of the flow used to create the bitstream. 6 JHDLBits Design Flow The traditional JHDL design flow produces an EDIF file, which is used by the Xilinx implementation tools to generate a bitstream. The JHDLBits flow instead relies upon JBits extensions to generate a bitstream. A high-level design is created and simulated with JHDL libraries and graphical debugging tools. The JHDL primitives, instances, and nets are extracted and mapped to equivalent JBits primitives and nets. JBits primitives are placed using either placement directives or an extendable placement algorithm, and then routed using ADB. A bitstream is generated, along with net and simulator files. Figure 3 shows the steps involved in the JHDLBits design flow. JHDL Design ADB Netlist JHDLBits TechMapper ADB Router JHDLBits Extractor extract primitive information Nets Dimensions Instances Placement Directives Placer VTsim Virtex-II Device Simulator Builder create JBits ULPrimitives Bitstream JHDLBits JBits Fig. 3. JHDLBits design flow The first step in the JHDLBits design flow is the JHDLBitsTechMapper. The JHDLBitsTechMapper extends the JHDL Virtex2TechMapper by overriding the netlist method, which invokes the JHDLBitsExtractor instead of the EDIFNetlister. Overriding device specific helper methods, such as add and subtract, allows for more optimized primitives.

7 The JHDLBitsExtractor uses JHDL libraries such as the Cell and Net classes to extract primitive, instance and net information, which are stored in HashMap collections. The primitive HashMap contains the ports and directions, and the instance HashMap contains the associated primitive, nets, and dimensions. The net HashMap contains ports of the net and a JBits net of the same name. The instance HashMap is then iterated in order to specify placement of the instances. The default placement algorithm stores the assigned CLB, slice, LUT, and LE (logic element) to the instance HashMap. The assigned coordinate information is also maintained for an instance that is ExternallyUpdateable, which refers to a JHDL cell (flip-flops, memories, etc.) that changes value and can be read back using the JHDL simulator in hardware execution mode. A JBits primitive is now created for each instance. Once all of the JBits primitives have been created, a router utilizing the connectivity information in ADB routes all nets connected to the JBits primitives. After the design has been successfully routed, JBits is used to generate a bitstream. JHDLBits and VTsim tie into the JHDL simulator through the JHDL HardwareInterface. VTsim is given the bitstream generated, along with coordinate information for the cells that are ExternallyUpdateable, and returns values for these cells after each clock cycle. The updated values are displayed in the JHDL GUI interface. Partial reconfiguration will be supported in JHDLBits through an incremental design flow. In an incremental design methodology, a user has completed part of a design, and would like to lock it down by no longer having to repeatedly place and route this part of the design. This would be accomplished by including a reserved area with defined inputs and outputs into the current JHDL design. This design is run through the JHDLBitsExtractor, but the placer and router are constrained to avoid the reserved area. At a later time, the user can then include additional logic into the reserved area, and once again run through the JHDLBitsExtractor in order to generate a bitstream. 7 JHDLBits Implementation and Results JHDLBits has been used to generate bitstreams for simple JHDL designs such as the following partial NBitAdder code: 1 // Simple model of a simple parameterized n-bit adder: 2 Wire carries = wire(width); // Intermediate carry wires 3 for (int i=0; i < width; i++) { 4 if (i==0) 5 new FullAdder(this,a.gw(i),b.gw(i),gnd(), 6 sum.gw(i), carries.gw(0)); 7 else 8 new FullAdder(this, a.gw(i), b.gw(i), carries.gw(i-1), 9 sum.gw(i), carries.gw(i)); 10 } Once the above design is compiled, the user needs to wire the NBitAdder design into the top-level system as shown below:

8 1 public class tb nbitadder extends Logic implements TestBench { 2 static JBitsTechMapper tm; 3 static Cell mynadd; 4 static HWSystem hw; 5 6 public static void main(string args[]) { 7 hw = new HWSystem(); // create a new system 8 tb nbitadder tb = new tb nbitadder(hw); 9 tm.netlist(mynadd, true, "testnbitadd.txt"); 10 } 11 public tb nbitadder(node parent) { 12 super(parent); 13 tm = new JBitsTechMapper(); 14 Logic.setDefaultTechMapper(tm); 15 Wire a = wire(4, "a"); 16 Wire b = wire(4, "b"); 17 Wire sum = wire(4, "sum"); 18 mynadd = new NBitAdder(this, a, b, sum); // connect 19 } // NBitAdder design 20 } Lines 2 and 13 indicate how JHDLBits is invoked from a JHDL design. As previously mentioned, the JHDLBitsBitsTechMapper netlist method calls the JHDLBitsExtractor instead of the EDIFNetlister. The JHDLBitsExtractor obtains all the information required from the JHDL design to create, place and route JBits primitives. A bitstream is then generated. The output generated for this sample run is included in Appendix A. As shown at the start of the output file, the ADB database is imported for the Virtex-II XC2V40 device. Next, the JHDLBitsExtractor begins traversing the hierarchical logic blocks at the top-level NBitAdder cell, and then through all successive children. When a new gnd or and2 primitive is encountered, the ports and directions are stored. The specific instance information of the gnd and and2 primitives is also retained. This is done recursively for all primitives and instances. Next, the b<1> net, then all remaining nets are extracted and converted to JBits nets. The placer assigns CLB, slice, LUT, and LE (logic elements) locations for each instance. After placement, JBits primitives are created, such as the and2, and associated nets are assigned source and sink pins. An example is the FullAdder-3/and_out-2 net, which is assigned to pin CLB.X1[0][2]. This pin refers to the X output in CLB row zero, column two, slice one. Once all JBits primitives are created and pins assigned, ADB is invoked to route the nets. Finally, a bitstream is generated. A few pertinent statistics are placements per second, and routes per second. The average placement rate is 512 primitives in 11 milliseconds, or 46,545 primitives per second. Please note that this design was run using a simple placer. A 100% utilization stress test on a Pentium 3.2 GHz processor running Sun Java HotSpot(tm) Client VM (build b05, mixed mode) yielded the ADB routing results in Table 1. The stress test consisted of a design that filled up every LE in the FPGA device with logic gates, which were then routed in a random fashion. Table 1. ADB routing performance for a 100% utilization stress test Device Route Time Total Nets Total Wires Nets/sec Wires/sec XC2V40 5,462 ms , ,813 XC2V500 80,865 ms 6, , ,130 XC2V ,080 ms 28,671 2,479, ,916

9 8 Conclusions and Future Work A major goal of the JHDLBits project has been to retain the properties and philosophies of JBits. Following this principle, it is essential to provide the ability to reconfigure the device through the JHDLBits design flow. This area is important and will be addressed in the near future. Another goal is to allow for partitioning of the design, so that the user can run part of the JHDL design through the mainstream tools and part through JBits via the JHDLBits extractor. The developers would like to investigate using JHDLBits in an embedded system, possibly using a small subset of JHDL and ADB rewritten in a language other than Java to reduce memory usage. In the current version of JHDLBits, placement is performed in a greedy suboptimal manner. Placement directives inherent in JHDL along with cell properties are currently being investigated and may possibly need refinement. Controlled placement will allow the user to identify a specific location in the device, permitting easier debugging as well as optimizing performance. The placer could potentially benefit from the use of previously designed placement algorithms, such as a core-based incremental placement algorithm [8]. Additional work is also needed to complete the JBits primitive library. The net interaction with the router must be improved to decrease memory usage and reduce routing time. The device simulator will continue to be developed in order to become more robust. It has been successfully applied to small static designs. The next step in the simulator design is to decrease memory usage, improve execution time, and provide a more flexible interface between JHDL and the router. The JHDLBits source code along with additional information can be found at 9 Acknowledgements This project is supported by a grant from Xilinx, Inc.; JBits (Xilinx and Virginia Tech) and JHDL (Brigham Young University) were both funded under the DARPA ACS program. References 1. V. Betz and J. Rose, VPR: A New Packing, Placement and Routing Tool for FPGA Research, International Workshop on Field Programmable Logic and Applications, pages , September S. A. Guccione and D. Levi, XBI: A Java-based interface to FPGA hardware, Configurable Computing Technology and its uses in High Performance Computing, DSP and Systems Engineering, Proc. SPIE Photonics East, J. Schewel (Ed.), SPIE - The International Society for Optical Engineering, volume 3526, pages , Bellingham, WA, November B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting, A CAD Suite for High-Performance FPGA Design, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 12 24, Napa, CA, April 1999.

10 4. D. Levi and S. A. Guccione, BoardScope: A Debug Tool for Reconfigurable Systems, Configurable Computing Technology and its uses in High Performance Computing, DSP and Systems Engineering, Proc. SPIE Photonics East, J. Schewel (Ed.), SPIE - The International Society for Optical Engineering, volume 3526, pages , Bellingham, WA, November N. Steiner, A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs, Master s thesis, Virginia Tech, August N. Steiner, An Alternate Wire Database for Xilinx FPGAs, Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, April R. Fong, S. Harper, and P. Athanas, A Versatile Framework for FPGA Field Updates: An Application of Partial Self-Reconfiguration, Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping, pages , San Diego, CA, June J. Ma, Incremental Design Techniques with Non-Preemptive Refinement for Million-Gate FPGAs, Doctoral dissertation, Virginia Tech, January The JBits SDK, Xilinx, Inc., The JHDL Home Page, Brigham Young University, J. Hunter, A Device-Level FPGA Simulator, Master s thesis, Virginia Tech, June Appendix A: Sample JHDLBits Run (Partial Listing) 1 Opening ADB database...edu\vt\adb\virtex2\xc2v40.db... 2 In JBitsExtractor expand function. 3 cell NBitAdder 4 In JBitsExtractor expand function. 5 cell gnd 6 In JBits extractprimitive function. 7 (port GROUND (direction 1)) 8 In JBits extractinstance function. 9 Instance Name gnd-1 10 cellref gnd 11 In JBitsExtractor expand function. 12 cell and2 13 In JBits extractprimitive function. 14 (port i0 (direction 0)) 15 (port i1 (direction 0)) 16 (port o (direction 1)) 17 In JBits extractinstance function. 18 Instance Name FullAdder/andX g/andx/and2 19 cellref and Net name b<1> 22 portname: i1 instancename: FullAdder-1/xor3 23 portname: i1 instancename: FullAdder-1/andX g-2/andx/and2 24 portname: i0 instancename: FullAdder-1/andX g/andx/and Placing in progress Instance 18 FullAdder-3/andX g-2/andx/and2 28 Port 0: Xwire<2> 29 Port 1: b<3> 30 Port 2: FullAdder-3/and out-2 31 Creating JBits and2 Object Adding SINK on Net(Xwire<2>): CLB.F1 B1[0][2] 33 Adding SINK on Net(b<3>): CLB.F2 B1[0][2] 34 Adding SOURCE on Net(FullAdder-3/and out-2): CLB.X1[0][2] Calling router Net name = FullAdder-3/and out-2 38 Sourcepin = CLB.Y2[0][4] 39 Sinkpins: 40 CLB.G1 B1[0][2] 41 Routing this connection Evaluated 71 groups in 8 tiles. 44 Bitstream Generated.