It also defines interaction between the above components. It is this low level programming model which makes programmed computations possible.

Size: px
Start display at page:

Download "It also defines interaction between the above components. It is this low level programming model which makes programmed computations possible."

Transcription

1 ProgrammingModel1 A.Introduction Objectives Attheendofthislabyoushouldbeableto: UsetheCPUsimulatortocreatebasicCPUinstructions UsethesimulatortoexecutebasicCPUinstructions UseCPUinstructionstomovedatatoregisters,comparevaluesinregisters, pushdatatothestack,popdatafromthestack,jumptoaddresslocations andaddvaluesheldinregisters. ExplainthefunctionsofspecialCPUregisterssuchasthePC,SRandSP registers. B.Processor(CPU)Simulators Thecomputerarchitecturetutorialsaresupportedbysimulators,whicharecreated tounderpintheoreticalconceptsnormallycoveredduringthelectures.the simulatorsprovidevisualandanimatedrepresentationofmechanismsinvolvedand enablethestudentstoobservethehiddeninnerworkingsofsystems,whichwould bedifficultorimpossibletodootherwise.theaddedadvantageofusingsimulators isthattheyallowthestudentstoexperimentandexploredifferenttechnological aspectsofsystemswithouthavingtoinstallandconfiguretherealsystems. C.BasicTheory Theprogrammingmodelofcomputerarchitecturedefinesthoselowlevel architecturalcomponents,whichincludethefollowing CPUinstructionset CPUregisters Differentwaysofaddressinginstructionsanddataininstructions Italsodefinesinteractionbetweentheabovecomponents.Itisthislowlevel programmingmodelwhichmakesprogrammedcomputationspossible. D.SimulatorDetails Thissectionincludessomebasicinformationonthesimulator,whichshouldenable thestudentstousethesimulator.thetutor(s)willbeavailabletohelpanyone experiencingdifficultyinusingthesimulator.thesimulatorforthislabisan applicationrunningonapcrunningmswindowsoperatingsystem. Themainwindowiscomposedofseveralviews,whichrepresentdifferentfunctional partsofthesimulatedprocessor.theseareshowninimage1belowandare composedof 1

2 CPUInstructionmemory SpecialCPUregisters CPU(generalpurpose)registers Programstack Programcreationandrunningfeatures CPUInstruction memoryview Addprogram instructionstab Createprogramtab SpecialCPU registersview Programlistview Image1 CPUSimulatorwindow CPUregistersview Programstackview Thepartsofthesimulatorrelevanttothislabaredescribedbelow.Pleasereadthis informationcarefullyandtrytoidentifythedifferentpartsonthecpusimulator windowbeforeattemptingthefollowingexercises.usethisinformationin conjunctionwiththeexercisesthatfollow. 2

3 1.CPUinstructionmemoryview Image2Instructionmemory view Thisviewcontainstheprogram instructions. The instructions are displayed as sequences of lowlevel instruction mnemonics (assemblerlevel format)andnotasbinarycode. This is done for clarity and makes code more readable by humans. Each instruction is associated with two addresses: the physicaladdress(padd)andthe logical address (LAdd). This view also displays the base address (Base) against each instruction. The sequence of instructions belonging to the same program will have the samebaseaddress. 2.SpecialCPUregistersview ThisviewshowsthesetofCPUregisters, whichhavepredefinedspecialistfunctions: PC:ProgramCountercontainstheaddress ofthenextinstructiontobeexecuted. IR:InstructionRegistercontainsthe instructioncurrentlybeingexecuted. SR:StatusRegistercontainsinformation pertainingtotheresultofthelastexecuted instruction. SP:StackPointerregisterpointstothevalue maintainedatthetopoftheprogramstack (seebelow). BR:BaseRegistercontainscurrentbase address. MAR:MemoryAddressRegistercontains Image3SpecialCPU registersview thememoryaddresscurrentlybeing accessed. Statusbits:OV:Overflow;Z:Zero;N: Negative 3

4 3.CPUregistersview Image4 CPURegistersview The register set view shows the contents of all the generalpurpose registers, which are used to maintain temporary values as the program's instructionsareexecuted.registersare very fast memories that hold temporary values while the CPU executesinstructions. Thisarchitecturesupportsfrom8to64 registers. These registers are often used to hold values of a program's variables as defined in highlevel languages. Not all architectures have this many registers. Some have more ( 128 register) and some others have less ( 8 registers). In all cases, these registersservesimilarpurposes. Thisviewdisplayseachregister'sname (Reg),itscurrentvalue(Val)andsome additional values, which are reserved for program debugging. It can also be used to reset the individual register values manually which is often useful for advanced debugging. To manually changearegister scontent,firstselect the register then enter the new value inthetextbox,regvalue,andclickon the CHANGE button in the Registers tab. 4

5 4.Programstackview Image5Programstackview Theprogramstackisanotherareawhich maintains temporary values as the instructionsareexecuted.thestackisa LIFO(lastinfirstout)datastructure.Itis often used for efficient interrupt handling and subroutine calls. Each programhasitsownindividualstack. TheCPUinstructionsPSH(push)andPOP areusedtostorevaluesontopofstack and pop values from top of stack respectively. 5.Programlistview Image6 ProgramListView Use the REMOVE PROGRAM button to remove the selected program from the list; use the REMOVE ALL PROGRAMS buttontoremovealltheprogramsfrom the list. Note that when a program is removed, its instructions are also removed from the Instruction Memory Viewtoo. 6.Programcreation Image7 Createprogramtab Tocreateanewprogramenterits nameintheprogramnamebox anditsbaseaddressinthebase AddressboxthenclickontheADD button.thenewprogram sname willappearintheprogramlistview (seeimage6). 5

6 Image8 Addprogram instructionstab UseADDNEW buttontoadda new instruction; use EDIT button to edit the selected instruction; use MOVE DOWN/ MOVE UP buttons to move the selected instruction down or up; use INSERT ABOVE /INSERT BELOW buttonstoinsertanew instruction above or below the selectedinstructionrespectively. E. Lab Exercises - Investigate and Explore Thelabexercisesareaseriesofactivities,whicharecarriedoutbythestudents underbasicguidelines.so,howisthistutorialconducted?thestudentsareexpected tofollowtheinstructionsgiveninordertoidentifyandlocatetherequired information,toactuponitandmakenotesoftheirobservations.inordertobeable todotheseactivitiesyoushouldconsulttheinformationinsectiondaboveandalso frequentlyrefertotheappendixforinformationonvariouscpuinstructionsyouwill beaskedtocreateanduse.remember,youneedtocarefullyreadandunderstand theinstructionsbeforeyoucanattempteachactivity. Now,letusstart.FirstyouneedtoplacesomeinstructionsintheInstruction MemoryView(seeImage2),representingtheRAMintherealmachine,before executinganyinstructions.todothis,followthestepsbelow: IntheProgramtab(seeImage7),firstenteraProgramName,andthenenteraBase Address(thiscanbeanynumber,butforthisexerciseuse100).ClickontheADD button.anewprogramnamewillbeenteredintheprogramlistview(seeimage6). YoucanusetheSAVE buttontosaveinstructionsinafile.youcanalsousethe LOAD buttontoloadinstructionsfromafile. YouarenowreadytoenterinstructionsintotheCPUSimulator.Youdothisby clickingontheaddnew buttonintheinstructionstab(seeimage8).thiswill displaytheinstructions:cpu0window.youusethiswindowtoselectandenterthe CPUinstructions.Appendixlistssomeoftheinstructionsthissimulatorusesandalso givesexamplesoftheirusage. Now,haveagoatthefollowingactivities(enteryouranswersinthetextboxes provided).awordofcaution:regularlysaveyourcodeinafileincasethesimulator crashesinwhichcaseyoucanrestartthesimulatorandreloadyourfile. 6

7 1. Createaninstruction,whichmovesnumber5toregisterR Executetheaboveinstruction(todothissimplydoubleclickonitinthe InstructionMemoryView).ObservetheresultintheCPURegistersview(Image 4). 3. Createaninstruction,whichmovesnumber8toregisterR Executeit(Youdothisbydoubleclickingontheinstruction) 5. ObservethecontentsofR00andR01intheCPURegistersview(Image4). 6. Createaninstruction,whichaddsthecontentsofR00andR Executeit. 8. Observewhichregistertheresultisputin. 9. Createaninstruction,whichpushestheaboveresulttothetopof thehardwarestack,andthenexecuteit. 10. Createaninstructiontopushnumber2ontopofthestackandexecuteit. ObservethevalueinProgramStack(Image5). 11. ObservethevalueintheSPregister(SpecialCPURegistersview Image3). WheneveryoupushavalueonProgramStack,theSPregisterisupdated. 12. CreateaninstructiontocomparethevaluesinregistersR00andR01. 7

8 13. Executeit. 14. ObservethevalueintheSRregister(SpecialCPURegistersview Image3). 15. ObservethestatusoftheOV/Z/Npartsofthestatusregister.Whichboxesare checkedandwhicharenot?whatdotheyindicate? 16. Createaninstructiontounconditionallyjumptothefirstinstruction. 17. Executeit. 18. ObservethevalueinthePCregister.Thisistheaddressofthenextinstructionto beexecuted.makeanoteofwhichinstructionitispointingto? 19. ObservethevaluesinthePAddandLAddcolumns.Whatdothesevalues indicate?aretheydifferent(hint:checkoutthebaseaddressvalue)? 20. WhatisthedifferencebetweentheLAddvalueofthefirstinstructionandthe LAddvalueofthesecondinstruction?Whatdoesthisvalueindicate(Hint:Think oftheinstructionlengthsinbytes)? 21. CreateaninstructiontopopthevalueontopoftheProgramStackintoregister R02. 8

9 22. Executeit. 23. ObservethevalueintheSPregister. 24. CreateaninstructiontopopthevalueontopoftheProgramStackintoregister R Executeit. 26. ObservethevalueintheSPregister. 27. Executethelastinstructionagain.Whathappened?Explain. 28. Createacompareinstruction,whichcomparesvaluesinregistersR04andR ManuallyinserttwoequalvaluesinregistersR04andR05(Image4). 30. Oneagainexecutethecompareinstructioninstep28above. 31. WhichofthestatusflagsOV/Z/Nisset(i.e.boxischecked)?Why? 32. ManuallyinsertavalueinregisterR05greaterthanthatinregisterR Executethecompareinstructioninstep28above. 34. WhichofthestatusflagsOV/Z/Nisset?Why? 35. ManuallyinsertavalueinregisterR04greaterthanthatinregisterR Executethecompareinstructioninstep28above. 37. WhichofthestatusflagsOV/Z/Nisset?Why? 9

10 38. Createaninstruction,whichwilljumptothefirstinstructionifthevaluesin registersr04andr05areequal. 39. TesttheaboveinstructionbymanuallyputtingequalvaluesinregistersR04 andr05,thenfirstexecutingthecompareinstructionfollowedbyexecutingthe jumpinstruction(remember:youexecuteaninstructionbydoubleclickingon it).diditwork? 40. SavetheinstructionsintheInstructionMemoryViewinafilebyclickingon thesave button(image7). ***Endofexercises*** 10

11 Instruction Data transfer instructions MOV LDB LDW STB STW PSH POP Appendix - Simulator Instruction Sub-set Description Move data to register; move register to register MOV #2, R01 moves number 2 into register R01 MOV R01, R03 moves contents of register R01 into register R03 Load a byte from memory to register Load a word (2 bytes) from memory to register Store a byte from register to memory Store a word (2 bytes) from register to memory Push data to top of hardware stack (TOS); push register to TOS PSH #6 pushes number 6 on top of the stack PSH R03 pushes the contents of register R03 on top of the stack Pop data from top of hardware stack to register Arithmetic instructions ADD SUB MUL DIV POP R05 pops contents of top of stack into register R05 Note: If you try to POP from an empty stack you will get the error message Stack overflow. Add number to register; add register to register ADD #3, R02 adds number 3 to contents of register R02 and stores the result in register R02. ADD R00, R01 adds contents of register R00 to contents of register R01 and stores the result in register R01. Subtract number from register; subtract register from register Multiply number with register; multiply register with register Divide number with register; divide register with register Control transfer instructions JMP Jump to instruction address unconditionally 11

12 JLT JGT JEQ JNE CAL RET SWI HLT JMP 100 unconditionally jumps to address location 100 Jump to instruction address if less than (after last comparison) Jump to instruction address if greater than (after last comparison) Jump to instruction address if equal (after last comparison instruction) JEQ 200 jumps to address location 200 if the previous comparison instruction result indicates that the two numbers are equal, i.e. the Z status flag is set (the Z box will be checked in this case). Jump to instruction address if not equal (after last comparison) Jump to subroutine address Return from subroutine Software interrupt (used to request OS help) Halt simulation Comparison instruction CMP Compare number with register; compare register with register CMP #5, R02 compare number 5 with the contents of register R02 CMP R01, R03 compare the contents of registers R01 and R03 Note: Input, output instructions IN OUT If R01 = R03 then the status flag Z will be set, i.e. the Z box is checked. If R03 > R01 then non of the status flags will be set, i.e. none of the status flag boxes are checked. If R01 > R03 then the status flag N will be set, i.e. the N status box is checked. Get input data (if available) from an external IO device Output data to an external IO device 12

Tutorial 1: Programming Model 1

Tutorial 1: Programming Model 1 Tutorial 1: Programming Model 1 Introduction Objectives At the end of this lab you should be able to: Use the CPU simulator to create basic CPU instructions Use the simulator to execute the basic CPU instructions

More information

Programming Model 2 A. Introduction

Programming Model 2 A. Introduction Programming Model 2 A. Introduction Objectives At the end of this lab you should be able to: Use direct and indirect addressing modes of accessing data in memory Create an iterative loop of instructions

More information

SOEN228, Winter Revision 1.2 Date: October 25,

SOEN228, Winter Revision 1.2 Date: October 25, SOEN228, Winter 2003 Revision 1.2 Date: October 25, 2003 1 Contents Flags Mnemonics Basic I/O Exercises Overview of sample programs 2 Flag Register The flag register stores the condition flags that retain

More information

Registers. Registers

Registers. Registers All computers have some registers visible at the ISA level. They are there to control execution of the program hold temporary results visible at the microarchitecture level, such as the Top Of Stack (TOS)

More information

It is possible to define a number using a character or multiple numbers (see instruction DB) by using a string.

It is possible to define a number using a character or multiple numbers (see instruction DB) by using a string. 1 od 5 17. 12. 2017 23:53 (https://github.com/schweigi/assembler-simulator) Introduction This simulator provides a simplified assembler syntax (based on NASM (http://www.nasm.us)) and is simulating a x86

More information

SPRING TERM BM 310E MICROPROCESSORS LABORATORY PRELIMINARY STUDY

SPRING TERM BM 310E MICROPROCESSORS LABORATORY PRELIMINARY STUDY BACKGROUND 8086 CPU has 8 general purpose registers listed below: AX - the accumulator register (divided into AH / AL): 1. Generates shortest machine code 2. Arithmetic, logic and data transfer 3. One

More information

Practical Malware Analysis

Practical Malware Analysis Practical Malware Analysis Ch 4: A Crash Course in x86 Disassembly Revised 1-16-7 Basic Techniques Basic static analysis Looks at malware from the outside Basic dynamic analysis Only shows you how the

More information

TYPES OF INTERRUPTS: -

TYPES OF INTERRUPTS: - There are 3 types of interrupts. TYPES OF INTERRUPTS: - External Interrupts. Internal Interrupts. Software interrupts. Hardware Interrupts (1) External interrupts come from I/O devices, from a timing device

More information

The CS5600 micro-computer

The CS5600 micro-computer The CS5600 micro-computer The CS5600 is a fictional computer that will be used for examples in class. The architecture of the system is shown in Figure 1, below. 8 general-purpose registers R0-R7 R7 FFFF

More information

The CSx600 micro-computer

The CSx600 micro-computer The CSx600 micro-computer The CSx600 is a fictional computer that will be used for examples in class. The architecture of the system is shown in Figure 1, below. 8 general-purpose registers R0-R7 R7 FFFF

More information

(2) Explain the addressing mode of OR What do you mean by addressing mode? Explain diff. addressing mode for 8085 with examples.

(2) Explain the addressing mode of OR What do you mean by addressing mode? Explain diff. addressing mode for 8085 with examples. (1) Explain instruction format and Opcode format of 8085 μp with example. OR With help of examples, explain the formation of opcodes of 8085 OR What is an instruction? List type of instruction based on

More information

10-1 C D Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e

10-1 C D Pearson Education, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e 10-1 C D E A B 10-2 A B A B C (A B) C D A A B (A B) C E D (A B) C D E (A B) C + D E (A B) C 10-3 Opcode Mode Address or operand 10-4 Memory 250 Opcode Mode PC = 250 251 ADRS 252 Next instruction ACC Opcode:

More information

1 The mnemonic that is placed before the arithmetic operation is performed is A. AAA B. AAS C. AAM D. AAD ANSWER: D

1 The mnemonic that is placed before the arithmetic operation is performed is A. AAA B. AAS C. AAM D. AAD ANSWER: D 1 The mnemonic that is placed before the arithmetic operation is performed is B. AAS C. AAM D. AAD 2 The Carry flag is undefined after performing the operation B. ADC C. AAD D. AAM 3 The instruction that

More information

Chapter 1 Background. Professor Gwan-Hwan Hwang Dept. Computer Science and Information Engineering National Taiwan Normal University

Chapter 1 Background. Professor Gwan-Hwan Hwang Dept. Computer Science and Information Engineering National Taiwan Normal University Chapter 1 Background Professor Gwan-Hwan Hwang Dept. Computer Science and Information Engineering National Taiwan Normal University 9/17/2009 1 Outlines 1.1 Introduction 1.2 System Software and Machine

More information

Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 153) Pass Marks: 24

Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 153) Pass Marks: 24 Prepared By ASCOL CSIT 2070 Batch Institute of Science and Technology 2065 Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 153) Pass

More information

INSTRUCTION SET OF 8085

INSTRUCTION SET OF 8085 INSTRUCTION SET OF 8085 Instruction Set of 8085 An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor

More information

9/25/ Software & Hardware Architecture

9/25/ Software & Hardware Architecture 8086 Software & Hardware Architecture 1 INTRODUCTION It is a multipurpose programmable clock drive register based integrated electronic device, that reads binary instructions from a storage device called

More information

Quiz 2 CSCI 1103 Computer Science I Honors KEY. Tuesday November 8, 2016 Instructor Muller Boston College. Fall 2016

Quiz 2 CSCI 1103 Computer Science I Honors KEY. Tuesday November 8, 2016 Instructor Muller Boston College. Fall 2016 Quiz 2 CSCI 1103 Computer Science I Honors KEY Tuesday November 8, 2016 Instructor Muller Boston College Fall 2016 Please do not write your name on the top of this quiz. Before reading further, please

More information

Today s Menu. >Use the Internal Register(s) >Use the Program Memory Space >Use the Stack >Use global memory

Today s Menu. >Use the Internal Register(s) >Use the Program Memory Space >Use the Stack >Use global memory Today s Menu Methods >Use the Internal Register(s) >Use the Program Memory Space >Use the Stack >Use global memory Look into my See examples on web-site: ParamPassing*asm and see Methods in Software and

More information

TABLE 9-1. Symbolic Convention for Addressing Modes. Register indirect LDA (R1) ACC M[ R1] Refers to Figure 9-4. Addressing mode. Symbolic convention

TABLE 9-1. Symbolic Convention for Addressing Modes. Register indirect LDA (R1) ACC M[ R1] Refers to Figure 9-4. Addressing mode. Symbolic convention T-236 Symbolic Convention for Addressing Modes TABLE 9-1 Symbolic Convention for Addressing Modes Refers to Figure 9-4 Addressing mode Symbolic convention Register transfer Effective address Contents of

More information

Chapter 1: Background

Chapter 1: Background Chapter 1: Background Hsung-Pin Chang Department of Computer Science National Chung Hsing University Outline 1.1 Introduction 1.2 System Software and Machine Architecture 1.3 The Simplified Instructional

More information

8085 INSTRUCTION SET INSTRUCTION DETAILS

8085 INSTRUCTION SET INSTRUCTION DETAILS 8085 INSTRUCTION SET INSTRUCTION DETAILS DATA TRANSFER INSTRUCTIONS MOV Rd, Rs Copy from source to destination This instruction copies the contents of the source register Rs into the destination register

More information

Systems Architecture The Stack and Subroutines

Systems Architecture The Stack and Subroutines Systems Architecture The Stack and Subroutines The Stack p. 1/9 The Subroutine Allow re-use of code Write (and debug) code once, use it many times A subroutine is called Subroutine will return on completion

More information

CSC 2400: Computer Systems. Towards the Hardware: Machine-Level Representation of Programs

CSC 2400: Computer Systems. Towards the Hardware: Machine-Level Representation of Programs CSC 2400: Computer Systems Towards the Hardware: Machine-Level Representation of Programs Towards the Hardware High-level language (Java) High-level language (C) assembly language machine language (IA-32)

More information

3.1 DATA MOVEMENT INSTRUCTIONS 45

3.1 DATA MOVEMENT INSTRUCTIONS 45 3.1.1 General-Purpose Data Movement s 45 3.1.2 Stack Manipulation... 46 3.1.3 Type Conversion... 48 3.2.1 Addition and Subtraction... 51 3.1 DATA MOVEMENT INSTRUCTIONS 45 MOV (Move) transfers a byte, word,

More information

Computer Organization: A Programmer's Perspective

Computer Organization: A Programmer's Perspective A Programmer's Perspective Instruction Set Architecture Gal A. Kaminka galk@cs.biu.ac.il Outline: CPU Design Background Instruction sets Logic design Sequential Implementation A simple, but not very fast

More information

Module 8: Atmega32 Stack & Subroutine. Stack Pointer Subroutine Call function

Module 8: Atmega32 Stack & Subroutine. Stack Pointer Subroutine Call function Module 8: Atmega32 Stack & Subroutine Stack Pointer Subroutine Call function Stack Stack o Stack is a section of RAM used by the CPU to store information temporarily (i.e. data or address). o The CPU needs

More information

CSC 8400: Computer Systems. Machine-Level Representation of Programs

CSC 8400: Computer Systems. Machine-Level Representation of Programs CSC 8400: Computer Systems Machine-Level Representation of Programs Towards the Hardware High-level language (Java) High-level language (C) assembly language machine language (IA-32) 1 Compilation Stages

More information

Islamic University Gaza Engineering Faculty Department of Computer Engineering ECOM 2125: Assembly Language LAB

Islamic University Gaza Engineering Faculty Department of Computer Engineering ECOM 2125: Assembly Language LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering ECOM 2125: Assembly Language LAB Lab # 9 Integer Arithmetic and Bit Manipulation April, 2014 1 Assembly Language LAB Bitwise

More information

Description of the Simulator

Description of the Simulator Description of the Simulator The simulator includes a small sub-set of the full instruction set normally found with this style of processor. It includes advanced instructions such as CALL, RET, INT and

More information

CNIT 127: Exploit Development. Ch 1: Before you begin. Updated

CNIT 127: Exploit Development. Ch 1: Before you begin. Updated CNIT 127: Exploit Development Ch 1: Before you begin Updated 1-14-16 Basic Concepts Vulnerability A flaw in a system that allows an attacker to do something the designer did not intend, such as Denial

More information

8051 Overview and Instruction Set

8051 Overview and Instruction Set 8051 Overview and Instruction Set Curtis A. Nelson Engr 355 1 Microprocessors vs. Microcontrollers Microprocessors are single-chip CPUs used in microcomputers Microcontrollers and microprocessors are different

More information

Program Exploitation Intro

Program Exploitation Intro Program Exploitation Intro x86 Assembly 04//2018 Security 1 Univeristà Ca Foscari, Venezia What is Program Exploitation "Making a program do something unexpected and not planned" The right bugs can be

More information

Ex : Write an ALP to evaluate x(y + z) where x = 10H, y = 20H and z = 30H and store the result in a memory location 54000H.

Ex : Write an ALP to evaluate x(y + z) where x = 10H, y = 20H and z = 30H and store the result in a memory location 54000H. Ex : Write an ALP to evaluate x(y + z) where x = 10H, y = 20H and z = 30H and store the result in a memory location 54000H. MOV AX, 5000H MOV DS, AX MOV AL, 20H MOV CL, 30H ADD AL, CL MOV CL, 10H MUL CL

More information

Computer Organization

Computer Organization Computer Organization (Instruction set Architecture & Assembly Language Programming) KR Chowdhary Professor & Head Email: kr.chowdhary@gmail.com webpage: krchowdhary.com Department of Computer Science

More information

Assembly Language Programming of 8085

Assembly Language Programming of 8085 Assembly Language Programming of 8085 1. Introduction A microprocessor executes instructions given by the user Instructions should be in a language known to the microprocessor Microprocessor understands

More information

Instruction Set Instruction set of 8085 can be classified in following groups: Data Transfer Instructions These instructions can perform data transfer operations between Registers of 8085 e.g. MOV 8085

More information

db "Please enter up to 256 characters (press Enter Key to finish): ",0dh,0ah,'$'

db Please enter up to 256 characters (press Enter Key to finish): ,0dh,0ah,'$' PA4 Sample Solution.model large.stack 100h.data msg1 db "This programs scans a string of up to 256 bytes and counts the repetitions of the number 4206 and sums them.",0dh,0ah,'$' msg2 db "Please enter

More information

Chapter Four Instructions Set

Chapter Four Instructions Set Chapter Four Instructions set Instructions set 8086 has 117 instructions, these instructions divided into 6 groups: 1. Data transfer instructions 2. Arithmetic instructions 3. Logic instructions 4. Shift

More information

Computer Architecture Lecture No.4 5-Instruction Set Architecture and Design 5-1 Memory locations and Operations. word

Computer Architecture Lecture No.4 5-Instruction Set Architecture and Design 5-1 Memory locations and Operations. word 5-Instruction Set Architecture and Design There are basic principles involved in instruction set architecture and design. Therefore, this section includes many important issues will discuss. 5-1 Memory

More information

Gechstudentszone.wordpress.com

Gechstudentszone.wordpress.com UNIT - 1 MACHINE ARCHITECTURE 11 Introduction: The Software is set of instructions or programs written to carry out certain task on digital computers It is classified into system software and application

More information

IFE: Course in Low Level Programing. Lecture 6

IFE: Course in Low Level Programing. Lecture 6 IFE: Course in Low Level Programing Lecture 6 Instruction Set of Intel x86 Microprocessors Conditional jumps Jcc jump on condition cc, JMP jump always, CALL call a procedure, RET return from procedure,

More information

ARM Architecture and Instruction Set

ARM Architecture and Instruction Set AM Architecture and Instruction Set Ingo Sander ingo@imit.kth.se AM Microprocessor Core AM is a family of ISC architectures, which share the same design principles and a common instruction set AM does

More information

Second Part of the Course

Second Part of the Course CSC 2400: Computer Systems Towards the Hardware 1 Second Part of the Course Toward the hardware High-level language (C) assembly language machine language (IA-32) 2 High-Level Language g Make programming

More information

Intel 8086: Instruction Set

Intel 8086: Instruction Set IUST-EE (Chapter 6) Intel 8086: Instruction Set 1 Outline Instruction Set Data Transfer Instructions Arithmetic Instructions Bit Manipulation Instructions String Instructions Unconditional Transfer Instruction

More information

Computer Systems Lecture 9

Computer Systems Lecture 9 Computer Systems Lecture 9 CPU Registers in x86 CPU status flags EFLAG: The Flag register holds the CPU status flags The status flags are separate bits in EFLAG where information on important conditions

More information

Its Assembly language programming

Its Assembly language programming 8085 Architecture & Its Assembly language programming Dr A Sahu Dept of Computer Science & Engineering IIT Guwahati 8085 Era and Features 8085 Outline Block diagram (Data Path) Bus Structure Register Structure

More information

CSIS1120A. 10. Instruction Set & Addressing Mode. CSIS1120A 10. Instruction Set & Addressing Mode 1

CSIS1120A. 10. Instruction Set & Addressing Mode. CSIS1120A 10. Instruction Set & Addressing Mode 1 CSIS1120A 10. Instruction Set & Addressing Mode CSIS1120A 10. Instruction Set & Addressing Mode 1 Elements of a Machine Instruction Operation Code specifies the operation to be performed, e.g. ADD, SUB

More information

CS 11 C track: lecture 8

CS 11 C track: lecture 8 CS 11 C track: lecture 8 n Last week: hash tables, C preprocessor n This week: n Other integral types: short, long, unsigned n bitwise operators n switch n "fun" assignment: virtual machine Integral types

More information

Programming of 8085 microprocessor and 8051 micro controller Study material

Programming of 8085 microprocessor and 8051 micro controller Study material 8085 Demo Programs Now, let us take a look at some program demonstrations using the above instructions Adding Two 8-bit Numbers Write a program to add data at 3005H & 3006H memory location and store the

More information

PESIT Bangalore South Campus

PESIT Bangalore South Campus INTERNAL ASSESSMENT TEST 2 Date : 02/04/2018 Max Marks: 40 Subject & Code : Microprocessor (15CS44) Section : IV A and B Name of faculty: Deepti.C Time : 8:30 am-10:00 am Note: Note: Answer any five complete

More information

Architecture & Instruction set of 8085 Microprocessor and 8051 Micro Controller

Architecture & Instruction set of 8085 Microprocessor and 8051 Micro Controller of 8085 microprocessor 8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configuration 8-bit

More information

Microprocessors 1. The 8051 Instruction Set. Microprocessors 1 1. Msc. Ivan A. Escobar Broitman

Microprocessors 1. The 8051 Instruction Set. Microprocessors 1 1. Msc. Ivan A. Escobar Broitman Microprocessors 1 The 8051 Instruction Set Microprocessors 1 1 Instruction Groups The 8051 has 255 instructions Every 8-bit opcode from 00 to FF is used except for A5. The instructions are grouped into

More information

complement) Multiply Unsigned: MUL (all operands are nonnegative) AX = BH * AL IMUL BH IMUL CX (DX,AX) = CX * AX Arithmetic MUL DWORD PTR [0x10]

complement) Multiply Unsigned: MUL (all operands are nonnegative) AX = BH * AL IMUL BH IMUL CX (DX,AX) = CX * AX Arithmetic MUL DWORD PTR [0x10] The following pages contain references for use during the exam: tables containing the x86 instruction set (covered so far) and condition codes. You do not need to submit these pages when you finish your

More information

CHAPTER ASSEMBLY LANGUAGE PROGRAMMING

CHAPTER ASSEMBLY LANGUAGE PROGRAMMING CHAPTER 2 8051 ASSEMBLY LANGUAGE PROGRAMMING Registers Register are used to store information temporarily: A byte of data to be processed An address pointing to the data to be fetched The vast majority

More information

CPU: SOFTWARE ARCHITECTURE INSTRUCTION SET (PART

CPU: SOFTWARE ARCHITECTURE INSTRUCTION SET (PART General Introduction CPU: SOFTWARE ARCHITECTURE INSTRUCTION SET (PART 1) General Introduction (1/5): On Instructions Instruction operate with data or with the flow of the program The following information

More information

Memory Models. Registers

Memory Models. Registers Memory Models Most machines have a single linear address space at the ISA level, extending from address 0 up to some maximum, often 2 32 1 bytes or 2 64 1 bytes. Some machines have separate address spaces

More information

By: Dr. Hamed Saghaei

By: Dr. Hamed Saghaei By: Dr. Hamed Saghaei The AVR RISC Microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory (SRAM). This section describes the different

More information

FUBAR RISC Computer Architecture

FUBAR RISC Computer Architecture FUBAR RISC Computer Architecture Roland Kammerer, Christian Paukovits, Mark Volcic, Gernot Vormayr October 15, 2007 1 General 16 16-bit registers, r0... r15 any register as return address little endian

More information

Instruction Set Architecture

Instruction Set Architecture CS:APP Chapter 4 Computer Architecture Instruction Set Architecture Randal E. Bryant adapted by Jason Fritts http://csapp.cs.cmu.edu CS:APP2e Hardware Architecture - using Y86 ISA For learning aspects

More information

231 Spring Final Exam Name:

231 Spring Final Exam Name: 231 Spring 2010 -- Final Exam Name: No calculators. Matching. Indicate the letter of the best description. (1 pt. each) 1. address 2. object code 3. condition code 4. byte 5. ASCII 6. local variable 7..global

More information

CHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY COMMUNICATION ENGINEERING REG 2008 TWO MARKS QUESTION AND ANSWERS

CHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY COMMUNICATION ENGINEERING REG 2008 TWO MARKS QUESTION AND ANSWERS CHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY B.E.,/B.TECH., ELECTRONICS EC6504 MICROPROCESSORS & MICRO CONTROLLERS COMMUNICATION ENGINEERING REG 2008 TWO MARKS QUESTION AND ANSWERS UNIT 1 AND 2 CS SUBJECT

More information

Assembly Language Programming of 8085

Assembly Language Programming of 8085 Assembly Language Programming of 8085 Topics 1. Introduction 2. Programming model of 8085 3. Instruction set of 8085 4. Example Programs 5. Addressing modes of 8085 6. Instruction & Data Formats of 8085

More information

MSMF GATE CENTRE. Sub: MICROPROCESSORS. Time: 50min Date: Marks:33

MSMF GATE CENTRE. Sub: MICROPROCESSORS. Time: 50min Date: Marks:33 MSMF GATE CENTRE Sub: MICROPROCESSORS Time: 50min Date:20-12-16 Marks:33 1. Which interrupt has highest priority in 8085 microprocessor? a) INTR b) RST 4.5 c) RST 6.5 d) RST 7.5 2. In 8085 microprocessor,

More information

UNIT-II. Part-2: CENTRAL PROCESSING UNIT

UNIT-II. Part-2: CENTRAL PROCESSING UNIT Page1 UNIT-II Part-2: CENTRAL PROCESSING UNIT Stack Organization Instruction Formats Addressing Modes Data Transfer And Manipulation Program Control Reduced Instruction Set Computer (RISC) Introduction:

More information

Microcontroller Intel [Instruction Set]

Microcontroller Intel [Instruction Set] Microcontroller Intel 8051 [Instruction Set] Structure of Assembly Language [ label: ] mnemonic [operands] [ ;comment ] Example: MOV R1, #25H ; load data 25H into R1 2 8051 Assembly Language Registers

More information

CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK

CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK Question 1: Choose the most appropriate answer 1. In which of the following gates the output is 1 if and only if all the inputs

More information

CPS104 Recitation: Assembly Programming

CPS104 Recitation: Assembly Programming CPS104 Recitation: Assembly Programming Alexandru Duțu 1 Facts OS kernel and embedded software engineers use assembly for some parts of their code some OSes had their entire GUIs written in assembly in

More information

Chapter 9. Programming Framework

Chapter 9. Programming Framework Chapter 9 Programming Framework Lesson 1 Registers Registers Pointers Accumulator Status General Purpose Outline CPU Registers Examples 8-bitA (Accumulator) Register 8-bit B Register 8-bitPSW (Processor

More information

Lecture V Toy Hardware and Operating System

Lecture V Toy Hardware and Operating System 2. THE Machine Lecture V Page 1 Lecture V Toy Hardware and Operating System 1. Introduction For use in our OS projects, we introduce THE Machine where THE is an acronym 1 for Toy HardwarE. We also introduce

More information

Microprocessor and Assembly Language Week-5. System Programming, BCS 6th, IBMS (2017)

Microprocessor and Assembly Language Week-5. System Programming, BCS 6th, IBMS (2017) Microprocessor and Assembly Language Week-5 System Programming, BCS 6th, IBMS (2017) High Speed Memory Registers CPU store data temporarily in these location CPU process, store and transfer data from one

More information

Ex: Write a piece of code that transfers a block of 256 bytes stored at locations starting at 34000H to locations starting at 36000H. Ans.

Ex: Write a piece of code that transfers a block of 256 bytes stored at locations starting at 34000H to locations starting at 36000H. Ans. INSTRUCTOR: ABDULMUTTALIB A H ALDOURI Conditional Jump Cond Unsigned Signed = JE : Jump Equal JE : Jump Equal ZF = 1 JZ : Jump Zero JZ : Jump Zero ZF = 1 JNZ : Jump Not Zero JNZ : Jump Not Zero ZF = 0

More information

Name (10) # Student. Student. 2017, Microprocessors 1 / 11

Name (10) # Student. Student. 2017, Microprocessors 1 / 11 Microprocessorss Laboratory 01 Debug/EMU86 # Student ID Student Name Grade (10) 1 / 11 DEBUG COMMAND SUMMARY Debug commands may be divided into four categories: program creation/debugging, memory manipulation,

More information

Introduction. 3 major parts of CPU : Fig Design Examples of simple CPU. In this chapter : Chap. 8. Chap. 8 Central Processing Unit

Introduction. 3 major parts of CPU : Fig Design Examples of simple CPU. In this chapter : Chap. 8. Chap. 8 Central Processing Unit Central Processing Unit 8-1 Introduction 3 major parts of CPU : Fig. 8-1 1) Register Set 2) ALU 3) Control Design Examples of simple CPU Hardwired Control : Chap. 5 Microprogrammed Control : Chap. 7 In

More information

ELECTRICAL ENGINEERING

ELECTRICAL ENGINEERING Serial : 1. JP_EE_Microprocessor_130618 CLASS TEST Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: 011-45124612 ELECTRICAL ENGINEERING

More information

2. Arithmetic Instructions addition, subtraction, multiplication, divison (HCS12 Core Users Guide, Sections 4.3.4, and ).

2. Arithmetic Instructions addition, subtraction, multiplication, divison (HCS12 Core Users Guide, Sections 4.3.4, and ). AS12 Assembler Directives A Summary of 9S12 instructions Disassembly of 9S12 op codes Huang Section 1.8, Chapter 2 MC9S12 V1.5 Core User Guide Version 1.2, Section 12 o A labels is a name assigned the

More information

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI-621213. QUESTION BANK DEPARTMENT: EEE SUB CODE: EE2324 YR/ SEM:III/ VI SUB NAME: MICROPROCESSORS & MICROCONTROLLERS UNIT 2- PROGRAMMING OF 8085 MICROPROCESSORS

More information

Summer 2003 Lecture 12 06/26/03

Summer 2003 Lecture 12 06/26/03 Summer 2003 Lecture 12 06/26/03 Implementing Standard C Control Structures: IF THEN ELSE if (a == b) { mov ax,a blah; cmp ax,b jnz endif blah endif: if (a == b) { true clause else { false clause mov ax,a

More information

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Interrupt Handling Module No: CS/ES/13 Quadrant 1 e-text

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Interrupt Handling Module No: CS/ES/13 Quadrant 1 e-text e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Interrupt Handling Module No: CS/ES/13 Quadrant 1 e-text 1. Interrupt An interrupt is the occurrence of a condition--an event --

More information

CDA 3103 Computer Organization Homework #7 Solution Set

CDA 3103 Computer Organization Homework #7 Solution Set CDA 3103 Computer Organization Homework #7 Solution Set 1 Problems 1. Write a MARIE assembly program for the following algorithm where the subroutine takes two numbers and returns their product. Your assembly

More information

Writing ARM Assembly. Steven R. Bagley

Writing ARM Assembly. Steven R. Bagley Writing ARM Assembly Steven R. Bagley Introduction Previously, looked at how the system is built out of simple logic gates Last week, started to look at the CPU Writing code in ARM assembly language Assembly

More information

CHAPTER 8: Central Processing Unit (CPU)

CHAPTER 8: Central Processing Unit (CPU) CS 224: Computer Organization S.KHABET CHAPTER 8: Central Processing Unit (CPU) Outline Introduction General Register Organization Stack Organization Instruction Formats Addressing Modes 1 Major Components

More information

Instruction set of 8085

Instruction set of 8085 Instruction set of 05 /23/2016 ptkarule@rediffmail.com 1 Instruction set of 05 Instruction set is divided into various groups depending on the operations performed: 1. Data transfer 2. rithmetic 3. Logical

More information

Q. Classify the instruction set of 8051 and list out the instructions in each type.

Q. Classify the instruction set of 8051 and list out the instructions in each type. INTRODUCTION Here is a list of the operands and their meanings: A - accumulator; Rn - is one of working registers (R0-R7) in the currently active RAM memory bank; Direct - is any 8-bit address register

More information

CS401 Assembly Language Solved MCQS From Midterm Papers

CS401 Assembly Language Solved MCQS From Midterm Papers CS401 Assembly Language Solved MCQS From Midterm Papers May 14,2011 MC100401285 Moaaz.pk@gmail.com MC100401285@gmail.com PSMD01(IEMS) Question No:1 ( Marks: 1 ) - Please choose one The first instruction

More information

Virtual Machine Tutorial

Virtual Machine Tutorial Virtual Machine Tutorial CSA2201 Compiler Techniques Gordon Mangion Virtual Machine A software implementation of a computing environment in which an operating system or program can be installed and run.

More information

Instruction Set Of 8051

Instruction Set Of 8051 Instruction Set Of 8051 By Darshan Patel M.Tech (Power Electronics & Drives) Assistant Professor, Electrical Department Sankalchand Patel college of Engineering-Visnagar Introduction The process of writing

More information

Chapter 7 Central Processor Unit (S08CPUV2)

Chapter 7 Central Processor Unit (S08CPUV2) Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more

More information

ECE 3210 Lab 4: Calculator

ECE 3210 Lab 4: Calculator ECE 3210 Lab 4: Calculator Fall 2017 1 Objective In this lab, you will develop an complete assembly program that takes an user input, performs data operations, and produces the expected output. After finishing

More information

8051 Microcontrollers

8051 Microcontrollers 8051 Microcontrollers Richa Upadhyay Prabhu NMIMS s MPSTME richa.upadhyay@nmims.edu March 8, 2016 Controller vs Processor Controller vs Processor Introduction to 8051 Micro-controller In 1981,Intel corporation

More information

Lecture 8: Control Structures. Comparing Values. Flags Set by CMP. Example. What can we compare? CMP Examples

Lecture 8: Control Structures. Comparing Values. Flags Set by CMP. Example. What can we compare? CMP Examples Lecture 8: Control Structures CMP Instruction Conditional High Level Logic Structures Comparing Values The CMP instruction performs a comparison between two numbers using an implied subtraction. This means

More information

Computer Science Final Examination Wednesday December 13 th 2006

Computer Science Final Examination Wednesday December 13 th 2006 Computer Science 03-60-266 Final Examination Wednesday December 13 th 2006 Dr. Alioune Ngom Last Name: First Name: Student Number: INSTRUCTIONS EXAM DURATION IS 3 hours. OPEN NOTES EXAM: lecture notes,

More information

Betriebssysteme und Sicherheit Sicherheit. Buffer Overflows

Betriebssysteme und Sicherheit Sicherheit. Buffer Overflows Betriebssysteme und Sicherheit Sicherheit Buffer Overflows Software Vulnerabilities Implementation error Input validation Attacker-supplied input can lead to Corruption Code execution... Even remote exploitation

More information

ADVANCE MICROPROCESSOR & INTERFACING

ADVANCE MICROPROCESSOR & INTERFACING VENUS INTERNATIONAL COLLEGE OF TECHNOLOGY Gandhinagar Department of Computer Enggineering ADVANCE MICROPROCESSOR & INTERFACING Name : Enroll no. : Class Year : 2014-15 : 5 th SEM C.E. VENUS INTERNATIONAL

More information

Computer System Architecture

Computer System Architecture CSC 203 1.5 Computer System Architecture Department of Statistics and Computer Science University of Sri Jayewardenepura Addressing 2 Addressing Subject of specifying where the operands (addresses) are

More information

Lecture 16: Passing Parameters on the Stack. Push Examples. Pop Examples. CALL and RET

Lecture 16: Passing Parameters on the Stack. Push Examples. Pop Examples. CALL and RET Lecture 1: Passing Parameters on the Stack Push Examples Quick Stack Review Passing Parameters on the Stack Binary/ASCII conversion ;assume SP = 0202 mov ax, 124h push ax push 0af8h push 0eeeh EE 0E F8

More information

Signed number Arithmetic. Negative number is represented as

Signed number Arithmetic. Negative number is represented as Signed number Arithmetic Signed and Unsigned Numbers An 8 bit number system can be used to create 256 combinations (from 0 to 255), and the first 128 combinations (0 to 127) represent positive numbers

More information

8.7 TM: A SIMPLE TARGET MACHINE

8.7 TM: A SIMPLE TARGET MACHINE 8.7 TM: A SIMPLE TARGET MACHINE In the section following this one we will present a code generator for the TINY language. In order to make this a meaningful task, we generate target code directly for a

More information

Y86 Processor State. Instruction Example. Encoding Registers. Lecture 7A. Computer Architecture I Instruction Set Architecture Assembly Language View

Y86 Processor State. Instruction Example. Encoding Registers. Lecture 7A. Computer Architecture I Instruction Set Architecture Assembly Language View Computer Architecture I Instruction Set Architecture Assembly Language View Processor state Registers, memory, Instructions addl, movl, andl, How instructions are encoded as bytes Layer of Abstraction

More information

Towards the Hardware"

Towards the Hardware CSC 2400: Computer Systems Towards the Hardware Chapter 2 Towards the Hardware High-level language (Java) High-level language (C) assembly language machine language (IA-32) 1 High-Level Language Make programming

More information