By: Dr. Hamed Saghaei

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1 By: Dr. Hamed Saghaei

6 The AVR RISC Microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory (SRAM). This section describes the different addressing modes supported by the AVR architecture and all of them are divided to 3 modes: Immediate Addressing Direct Addressing Indirect Addressing

7 Immediate Addressing Example 1: LDI R16, $55 OP.CODE OPERAND SUBI Rd, k Rd belong to {R0,,R31} k belong to {0,,$FF}

8 Direct Addressing Direct Register Addressing 1) Direct Single Register Addressing 2)Direct Two Registers Addressing I/O Direct Addressing Direct Data Addressing

9 1-Direct Register Addressing The operand is contained in register d (Rd). Example2: INC Rd INC R11 DEC R13

10 2-Direct Two Registers Addressing Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). Example3: ADD Rd,Rr MOV R10,R11

11 Direct Data Addressing A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. Example5: LDS Rd,k STS k,rr

12 Data Indirect Addressing Data Indirect Addressing in SRAM 1) Constant Data Indirect Addressing 2) Data Indirect Addressing with Displacement 3) Data Indirect With Pre-Decrement 4) Data Indirect With Post-Increment Indirect Addressing in Flash (Code Memory) 1) Code Memory Constant Addressing 2) Code Memory Indirect With Post-Increment 3) Relative Program Addressing

13 1) Constant Data Indirect Addressing Operand address is the contents of the X, Y or the Z-register. Example6: LD Rd,X LD Rd,Y LD Rd,Z ST X,Rr ST Y,Rr ST Z,Rr

14 2) Data Indirect with Displacement Operand address is the result of the Y or Z-register contents added to the address contained in 6 bits of the instruction word. Example 7: LDD Rd,Z+a STD Z+a,Rr LDD R1,Z+1

15 3) Data Indirect With Pre-Decrement The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y or the Z-register. Example 8: LD Rd,-X ST -Y,Rr

16 4) Data Indirect With Post-Increment The X, Y or the Z-register is incremented after the operation. Operand address is the content of the X, Y or the Z-register prior to incrementing. Example9: LD Rd,X+ LD Rd,Y+ LD Rd,Z+ ST X+,Rr ST Y+,Rr ST Z+,Rr

17 1) Code Memory Constant Addressing Constant byte address is specified by the Z-register contents. The 15 MSBs select word address, the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). Example10: LPM Rd,Z ELPM Rd,Z 2) Code Memory Indirect With Post-Increment LPM Rd,Z+ ELPM Rd,Z+

18 3) Relative Program Memory Addressing Program execution continues at address PC + k + 1. The relative address k is to For RJMP and RCALL

19 HAMED SAGHAEI

20 The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book. INSTRUCTION In AVR: 1) ARITHMETIC & LOGIC INSTRUCTIONS 2) DATA TRANSFER INSTRUCTIONS 3) BRANCH INSTRUCTIONS 4) BIT AND BIT-TEST INSTRUCTIONS

21 ARITHMETIC INSTRUCTIONS Instructions Op.code &Operands ADD Rd, Rr Description Operation Flags(SRE G) Add without Carry Cycle Rd Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rd, K Add Immediate to Word Rd+1:Rd Rd+1:Rd + K Z,C,N,V 2 SUB Rd, Rr SUBI Rd, K Subtract without Carry Subtract Immediate Rd Rd - Rr Z,C,N,V,H 1 Rd Rd - K Z,C,N,V,H 1

22 ARITHMETIC INSTRUCTIONS Instructions Op.code &Operands SBC Rd, Rr SBCI Rd, K SBIW Rd, K MUL Rd,Rr Description Operation Flags(SREG) Cycle Subtract with Carry Subtract Immediate with Carry Subtract Immediate from Word Multiply Unsigned Rd Rd - Rr - C Z,C,N,V,H 1 Rd Rd - K - C Z,C,N,V,H 1 Rd+1:Rd Rd+1:Rd - K Z,C,N,V 2 R1, R0 Rd. Rr C 1 * INC Rd Increment Rd Rd + 1 Z,N,V 1

23 ARITHMETIC & LOGIC INSTRUCTIONS Instructions Op.code &Operands Description Operation Flags(SREG) Cycle DEC Rd Decrement Rd Rd - 1 Z,N,V 1 OR Rd, Rr Logical OR Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR with Immediate Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Rd Rd xor Rr Z,N,V 1 COM Rd NEG Rd One's Complement Two's Complement Rd $FF - Rd Z,C,N,V 1 Rd $00 - Rd Z,C,N,V,H 1

24 ARITHMETIC & LOGIC INSTRUCTIONS Instructions Op.code &Operands Description Operation Flags(SRE G) CLR Rd Clear Register Rd Rd xor Rd Z,N,V 1 SER Rd Set Register Rd $FF None 1 SBR Rd,K CBR Rd,K TST Rd Set Bit(s) in Register Rd Clear Bit(s) in Register Test for Zero or Minus Cycle Rd Rd v K Z,N,V 1 Rd Rd ($FFh - K) Z,N,V 1 Rd Rd Rd Z,N,V 1

25 Instructions Op.code &Operands Description Operation Flags(SR EG) RJMP k Relative Jump PC PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC Z None 2 JMP k Jump PC k None 3 RCALL k Relative Call Subroutine Cycle PC PC + k + 1 None 3 CALL k Call Subroutine PC k None 4 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I 4 CPSE Rd,Rr BRANCH INSTRUCTIONS Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1 / 2 / 3

26 Instructions Op.code &Operands BRANCH INSTRUCTIONS Description Operation Flags(SRE G) Cycle CP Rd,Rr Compare Rd - Rr Z,C,N,V,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,H 1 CPI Rd,K SBRC Rr, b SBRS Rr, b SBIC P, b SBIS P, b Compare with Immediate Skip if Bit in Register Cleared Skip if Bit in Register Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register Set Rd - K Z,C,N,V,H 1 if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if(i/o(p,b)=0) PC PC + 2 or 3 if(i/o(p,b)=1) PC PC + 2 or 3 None 1 / 2 / 3 None 1 / 2 / 3 None 1 / 2 / 3 None 1 / 2 / 3

27 Instructions Op.code &Operands BRANCH INSTRUCTIONS Description Operation Flags(S REG) Cycle BRBS s, k BRBC s, k Branch if Status Flag Set Branch if Status Flag Cleared if (SREG(s) = 1) then PC PC+k + 1 if (SREG(s) = 0) then PC PC+k + 1 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 BRCC k BRSH k Branch if Carry Cleared Branch if Same or Higher if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 None 1 / 2 None 1/2 None 1/2 None 1/2 None 1 / 2 None 1 / 2 None 1 / 2

28 DATA TRANSFER INSTRUCTIONS Instructions Op.code &Operands Description Operation Flags(S REG) Cycle MOV Rd, Rr Copy Register Rd Rr None 1 LDI Rd, K Load Immediate Rd K None 1 LDS Rd, k Load Direct from SRAM Rd (k) None 3 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ LD Rd, -X LDD Rd,Y+q Load Indirect and Post-Increment Load Indirect and Pre-Decrement Load Indirect with Displacement Rd (X), X X + 1 None 2 X X - 1, Rd (X) None 2 Rd (Y + q) None 2

29 DATA TRANSFER INSTRUCTIONS Instructions Op.code &Operands Description Operation Flags( SREG) Cycle STS k, Rr Store Direct to SRAM (k) Rr None 3 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr ST -X, Rr Store Indirect and Post-Increment Store Indirect and Pre-Decrement (X) Rr, X X + 1 None 2 X X - 1, (X) Rr None 2 STD Y+q,Rr LPM Store Indirect with Displacement Load Program Memory (Y + q) Rr None 2 R0 (Z) None 3 IN Rd, P In Port Rd P None 1

30 DATA TRANSFER INSTRUCTIONS Instructions Op.code &Operands Description Operation Flags( SREG) Cycle OUT P, Rr Out Port P Rr None 1 PUSH Rr POP Rd Push Register on Stack Pop Register from Stack STACK Rr None 2 Rd STACK None 2

31 BIT AND BIT-TEST INSTRUCTIONS Instructions Op.code &Operands Description Operation Flags( SREG) LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0, C Rd(7). LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0, C Rd(0) ROL Rd ROR Rd ASR Rd Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Rd(0) C, Rd(n+1) Rd(n), C Rd(7) Rd(7) C, Rd(n) Rd(n+1), C Rd(0) Rd(n) Rd(n+1), n=0..6 Z,C,N,V, H Cycle Z,C,N,V 1 Z,C,N,V, H Z,C,N,V 1 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4) None 1 1 1

32 BIT AND BIT-TEST INSTRUCTIONS Instructions Op. code &Operands Description Operation Flags( SREG) BSET s Flag Set SREG(s) 1 SREG(s) 1 Cycle BCLR s Flag Clear SREG(s) 0 SREG(s) 1 SBI P, b Set Bit in I/O Register I/O(P, b) 1 None 2 CBI P, b Clear Bit in I/O Register I/O(P, b) 0 None 2 BST Rr, b BLD Rd, b Bit Store from Register to T Bit load from T to Register T Rr(b) T 1 Rd(b) T None 1

33 BIT AND BIT-TEST INSTRUCTIONS Instructions Op. code &Operands Description Operation Flags( SREG) SEC Set Carry C 1 C 1 Cycle CLC Clear Carry C 0 C 1 (SEI, SES SEV, SET SHE. SEN) NOP No Operation None 1 SLEEP Sleep None 1 WDR Watchdog Reset None 1

AT90S Bit Microcontroller with 1K bytes Downloadable Flash AT90S1200. Features. Description. Pin Configuration

AT90S Bit Microcontroller with 1K bytes Downloadable Flash AT90S1200. Features. Description. Pin Configuration Features Utilizes the AVR Enhanced RISC Architecture 89 Powerful Instructions - Most Single Clock Cycle Execution 1K bytes of In-System Reprogrammable Downloadable Flash - SPI Serial Interface for Program