DIGITAL SYSTEM DESIGN

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1 DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1

2 Name: Registration No: Roll No: Semester: Batch: Digital System Design 2

3 CONTENTS Exp No List of Experiments Digital System Design 3

4 LAB 01 A - GATE LEVEL DESIGN At gate level, the circuit is described in terms of gates (e.g. and, nand). Hardware design at this level is intuitive for a user with a basic knowledge of digital logic design because it is possible to see a one-to-one correspondence between the logic circuit diagram and the Verilog description. Lab Overview In this lab you will: Learn modeling at gate level Half adder design Full adder design Multiplexer design Decoder design Background: The simplest form of adder is called a Half-Adder (HA). The HA performs bit-wise addition between two input bits. Depending on the result of the operation, the HA either sets or clears its Sum and Carry bit. A HA can be expanded to include the logic for carry in, and the modified unit is called the Full Adder (FA). Digital System Design 4

5 The verilog code for the half adder is module HA(a,b,s,c); input a,b; output s,c; xor(s,a,b); and(c,a,b); The test bench of the half adder is module testbench_ha(); reg a,b; wire s,c; HA HA_inst(a,b,s,c); initial begin a=0; b=0; #10 a=0; b=1; #10 a=1; b=0; #10 a=1; b=1; end We can use the half adder to design a full adder as shown in figure 1.3. The full adder takes an extra bit as input for carry in. Digital System Design 5

6 The verilog code of full adder is module FA(a,b,cin,s,cout); input a,b,cin; output s,cout; wire c0, s0, c1; HA HA_inst0(a,b,s0,c0); HA HA_inst1(cin,s0,s,c1); or(cout, c1,c0); Digital System Design 6

7 LAB 01 B - DATAFLOW LEVEL DESIGN Dataflow modeling provides a powerful way to implement a design. Verilog allows a circuit to be designed in terms of the data flow between registers and how a design processes data rather than instantiation of individual gates. Lab Overview In this lab you will: Learn modeling at dataflow level Half adder design (dataflow) Full adder design (dataflow) 4-bit adder design 12-bit Carry Select Adder (CSA) Multiplexer design (dataflow) Decoder design (dataflow) Background: The simplest form of adder is called a Half-Adder (HA). The HA performs bit-wise addition between two input bits. Depending on the result of the operation, the HA either sets or clears its Sum and Carry bit. A HA can be expanded to include the logic for carry in, and the modified unit is called the Full Adder (FA). Digital System Design 7

$The verilog code for the half adder at dataflow level is module HA(a,b,s,c); input a,b; output s,c; assign s = a^b; assign c = a&b; // assign {s,c} = a+b; The test bench of$

8 The verilog code for the half adder at dataflow level is module HA(a,b,s,c); input a,b; output s,c; assign s = a^b; assign c = a&b; // assign {s,c} = a+b; The test bench of the half adder is module testbench_ha(); reg a,b; wire s,c; HA HA_inst(a,b,s,c); initial begin a=0; b=0; #10 a=0; b=1; #10 a=1; b=0; #10 a=1; b=1; end Digital System Design 8

9 We can use the half adder to design a full adder as shown in figure 2.3. The full adder takes an extra bit as input for carry in. The verilog code of full adder at dataflow level is module FA(a,b,cin,s,cout); input a,b,cin; output s,cout; wire c0, s0, c1; HA HA_inst0(a,b,s0,c0); HA HA_inst1(cin,s0,s,c1); assign cout = c1 c0; assign {s,cout} = a + b + cin; Digital System Design 9

10 LAB 02 BEHAVIORAL LEVEL DESIGN With the increasing complexity of digital design, it has become vitally important to make wise design decisions early in a project. Designers need to be able to evaluate the trade-offs of various architectures and algorithms before they decide on the optimum architecture and algorithm to implement in hardware. Thus, architectural evaluation takes place at an algorithmic level where the designers do not necessarily think in terms of logic gates or data flow but in terms of the algorithm they wish to implement in hardware. They are more concerned about the behavior of the algorithm and its performance. Only after the high-level architecture and algorithm are finalized, do designers start focusing on building the digital circuit to implement the algorithm. Verilog provides designers the ability to describe design functionality in an algorithmic manner. In other words, the designer describes the behavior of the circuit. Thus, behavioral modeling represents the circuit at a very high level of abstraction. Lab Overview In this lab you will: Learn modeling at dataflow level Half adder design (dataflow) Full adder design (dataflow) 4-bit adder design 12-bit Carry Select Adder (CSA) Multiplexer design (dataflow) Decoder design (dataflow) Background: The simplest form of adder is called a Half-Adder (HA). The HA performs bit-wise addition between two input bits. Depending on the result of the operation, the HA either sets or clears its Sum and Carry bit. A HA can be expanded to include the logic for carry in, and the modified unit is called the Full Adder (FA). At behavioral level you don t need to know the structural model but you are only concerned with the behavioral of a circuit. Comments have been added in the code which give a feel for behavioral level coding. Digital System Design 10

$The verilog code for the half adder at behavioral level is module HA(a,b,s,c); input a,b; output s,c; reg s,c; always @(a or b) begin s= a^b; c = a&b; //OR {s,c} = a+b; end The test$

11 The verilog code for the half adder at behavioral level is module HA(a,b,s,c); input a,b; output s,c; reg s,c; or b) begin s= a^b; c = a&b; //OR {s,c} = a+b; end The test bench of the half adder is module testbench_ha(); reg a,b; wire s,c; HA HA_inst(a,b,s,c); initial begin a=0; b=0; #10 a=0; b=1; #10 a=1; b=0; #10 a=1; b=1; end Digital System Design 11

12 You can use the half adder to design a full adder. The full adder takes an extra bit as input for carry in. The Verilog code of full adder at behavioral level is module FA(a,b,cin,s,cout); input a,b,cin; output s,cout; wire c0, s0, c1; HA HA_inst0(a,b,s0,c0); HA HA_inst1(cin,s0,s,c1); assign cout = c1 c0; // OR // or b or cin) //{s,cout} = a+b+cin; Digital System Design 12

13 LAB 03 TO OBSERVE THE OPERATION OF 2 TO 1 LINE MUX The Verilog code of 2 to 1 line multiplexer at dataflow level is module mux(i0,i1,selct,m,n,out); input i0,i1,selct; output m,n,out; assign m=i0&selct; assign n=i1&~selct; assign out=m n; The test bench of 2 to 1 line multiplexer is module testbench_mux; reg i0,i1,selct; wire m,n; mux ff(i0,i1,selct,m,n,out); initial begin i0=1'b0;i1=1'b1;selct=1'b1; //inputs a=0 and b=1 #10 i0=1'b0;i1=1'b1;selct=1'b0; #10 $finish; end Lab Tasks: 1. Write a verilog code for 2 to 1 line multiplexer in behavioral level 2. Write a verilog code for 4 to 1 line multiplexer in behavioral level. Digital System Design 13

14 Lab 4 16 bit Ripple Carry Adder Digital System Design 14

15 DESIGN HIERARCY OF A 16-BIT RIPPLE-CARRY ADDER module Add_rca_16 (sum, c_out, a, b, c_in); output [15: 0] sum; output c_out; input [15: 0] a, b; input c_in; wire c_in4, c_in8, c_in12; Add_rca_4 M1 (sum[3:0], c_in4, a[3:0], b[3:0], c_in); Add_rca_4 M2 (sum[7:4], c_in8, a[7:4], b[7:4], c_in4); Add_rca_4 M3 (sum[11:8], c_in12, a[11:8], b[11:8], c_in8); Add_rca_4 M4 (sum[15:12], c_out, a[15:12], b[15:12], c_in12); module Add_rca_4 (sum, c_out, a, b, c_in); output [3: 0] sum; output c_out; input [3: 0] a, b; input c_in; wire c_in2, c_in3, c_in4; Add_full M1 (sum[0], c_in2,a[0], b[0], c_in); Add_full M2 (sum[1], c_in3, a[1], b[1], c_in2); Add_full M3 (sum[2], c_in4, a[2], b[2], c_in3); Add_full M4 (sum[3], c_out, a[3], b[3], c_in4); Digital System Design 15

16 module Add_full (sum, c_out, a, b, c_in); output sum, c_out; input a, b, c_in; wire w1, w2, w3; Add_half M1 (w1, w2, a, b); Add_half M2 (sum, w3, w1, c_in); or M3 (c_out, w2, w3); module Add_half (sum, c_out, a, b); output sum, c_out; input a, b; wire c_out_bar; xor M1 (sum, a, b); and M2 (c_out, a, b); Test Bench module test_add_rca_16 (); wire [15: 0] sum; wire c_out; reg [15: 0] a, b; reg c_in; Add_rca_16 M1 (sum, c_out, a, b, c_in); initial begin #10 a = 16'h0000; b = 16'h0000; c_in = 0; #10 a = 16'h000f; b = 16'h000c; c_in = 0; #10 a = 16'h000f; b = 16'h000c; c_in = 1; #10 a = 16'h0000; b = 16'h0000; c_in = 1; #10 a = 16'h000f; b = 16'h0001; c_in = 0; #10 a = 16'h000f; b = 16'h0001; c_in = 1; end $finish; Digital System Design 16

17 Lab 5: BEHAVIORAL MODELS (level Sensitive) A. (Continuous Assignment Statement) Lab 5.1 (Continuous Assignment Statement) Digital System Design 17

18 Lab 5.2 (Continuous Assignment Statement with Conditional Operator) Digital System Design 18

19 Lab 5.3 (Continuous Assignment Statement with Conditional Operator) Digital System Design 19

both levels- sensitive and edge sensitive

20 B. Cyclic behavioral models of flip flops and latches Cyclic behaviors are used to model (and synthesize) both levels- sensitive and edge sensitive (synchronous) behavior (e.g flip flop) Lab 5.4 Digital System Design 20

21 1. Blocking (the = operator) Blocking and Non-Blocking Assignment With blocking assignments each statement in the same time frame is executed in sequential order within their blocks. If there is a time delay in one line then the next statement will not be executed until this delay is over. initial begin end a = 4; b = 3; example 1 #10 c = 18; #5 d = 7; Above, at time=0 both a and b will have 4 and 3 assigned to them respectively and at time=10, c will equal 18 and at time=15, d will equal Non-Blocking (the <= operator) Non-Blocking assignments tackle the procedure of assigning values to variables in a totally different way. Instead of executing each statement as they are found, the right-hand side variables of all non-blocking statements are read and stored in temporary memory locations. When they have all been read, the left-hand side variables will be determined. They are non-blocking because they allow the execution of other events to occur in the block even if there are time delays set. integera,b,c; initial begin a = 67; #10; a <= 4; example 2 c <= #15 a; d <= #10 9; b <= 3; end This example sets a=67 then waits for a count of 10. Then the right-hand variables are read and stored in tempory memory locations. Here this is a=67. Then the left-hand variables are set. At time=10 a and b will be set to 4 and 3. Then at time=20 d=9. Finally at time=25, c=a which was 67, therefore c=67. Note that d is set before c. This is because the four statements for setting a-d are performed at the same time. Variable d is not waiting for variable c to complete its task. This is similar to a Parallel Block. Digital System Design 21

22 This example has used both blocking and non-blocking statements. The blocking statement could be non-blocking, but this method saves on simulator memory and will not have as large a performance drain. Digital System Design 22

23 Application of Non-Blocking Assignments We have already seen that non-blocking assignments can be used to enable variables to be set anywhere in time without worrying what the previous statements are going to do. Another important use of the non-blocking assignment is to prevent race conditions. If the programmer wishes two variables to swap their values and blocking operators are used, the output is not what is expected: initial begin end x = 5; y = 3; clock) begin x = y; y = x; end example 3 This will give both x and y the same value. If the circuit was to be built a race condition has been entered which is unstable. The compliler will give a stable output, however this is not the output expected. The simulator assigns x the value of 3 and then y is then assigned x. As x is now 3, y will not change its value. If the non-blocking operator is used instead: begin x <= y; example 4 y <= x; end both the values of x and y are stored first. Then x is assigned the old value of y (3) and y is then assigned the old value of x (5). Digital System Design 23

DIGITAL SYSTEM DESIGN

DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1 Name: Registration No: Roll No: Semester: