D4.5 OS Allocation and Migration Support Final Release

Size: px
Start display at page:

Download "D4.5 OS Allocation and Migration Support Final Release"

Transcription

1 Project Number D4.5 OS Allocation and Migration Support Final Release Version 1.01 Final Public Distribution University of York, aicas, Bosch and University of Stuttgart Project Partners: aicas, Bosch, CNRS, Rheon Media, The Open Group, University of Stuttgart, University of York Every effort has been made to ensure that all statements and information contained herein are accurate, however the DreamCloud Project Partners accept no liability for any error or omission in the same Copyright in this document remains vested in the DreamCloud Project Partners.

2 Project Partner Contact Information aicas Bosch Fridtjof Siebert Devendra Rai Haid-und-Neue Strasse 18 Robert-Bosch-Strasse Karlsruhe Schwieberdingen Germany Germany Tel: Tel: siebert@aicas.com devendra.rai@de.bosch.com CNRS Rheon Media Gilles Sassatelli Raj Patel Rue Ada Leighton Avenue Montpellier Pinner Middlesex HA5 3BW France United Kingdom Tel: Tel: sassatelli@lirmm.fr raj@rheonmedia.com The Open Group University of Stuttgart Scott Hansen Bastian Koller Avenue du Parc de Woluwe 56 Nobelstrasse Brussels Stuttgart Belgium Germany Tel: Tel: s.hansen@opengroup.org koller@hlrs.de University of York Leandro Indrusiak Deramore Lane York YO10 5GH United Kingdom Tel: leandro.indrusiak@cs.york.ac.uk Page ii Version 1.01

3 Contents List of Figures iv 1 Executive Summary 2 2 Overview of Prototype Release 3 3 OS Support for Migration Migration of Bundles Between Nodes Test of Migrating Bundles Between Nodes Conclusion 10 5 References 11 Version 1.01 Page iii

4 List of Figures 1 Conceptual DreamCloud migration architecture Xilinx Zynq SoC block diagram [5] Conceptual architecture with Linux OS running on each node Conceptual architecture with Linux OS and JVM running on each node Applications (Ts) running on different nodes within JVM Migration process to migrate bundles between nodes Counter bundle is running when a migration request is received Counter bundle starts counting from last state of the freeze bundle Management webpage of the Openfire server showing established connections Spark XMPP client. The left hand side shows sending chat message text window, and the right hand side shows the connected users available to chat Page iv Version 1.01

5 Document Control Version Status Date 0.1 Initial Draft 4 March Version after addressing 7 March 2016 project partners reviews 1.0 Final version 9 March Added link to the demonstration video Version 1.01 Page 1

6 1 Executive Summary This document constitutes deliverable D4.5 OS Allocation and Migration Support Final Release of work package 4 of the DreamCloud project. To fulfill the requirement of the deliverable, allocation and migration support including software and documentation is presented along with a brief review of the prototype deliverable. The prototype architecture used field-programmable gate arrays (FPGAs) as they support easy and rapid prototyping. A brief review of the prototype deliverable is provided in next section. This document also provides an elaboration of the achievements for the final release. Page 2 Version 1.01

7 2 Overview of Prototype Release D4.5 OS Allocation and Migration Support Final Release The DreamCloud conceptual migration architecture proposed in the prototype release and adopted in the final release is shown in Figure 1. The architecture contains a set of 4 nodes connected via Ethernet/Fibre Channel, where each node is a Xilinx Zynq-7000 System-on-Chip (SoC) board [1]. The board has a FPGA which contains the processor system and reconfigurable region. The board also contains other peripherals such as memories and inputs/outputs. Data streams Zynq-7000 SoC Zynq-7000 SoC Zynq-7000 SoC Zynq-7000 SoC Processor System Processor System Processor System Processor System Interconnect Interconnect Interconnect Interconnect IP IP IP IP Ethernet/Fibre Channel Figure 1: Conceptual DreamCloud migration architecture. Figure 2 shows the structure of the Zynq FPGA (figure with more details can be found in deliverable D4.3). The upper part of the figure shows the processing system which is a dual core 32-bits ARM Cortex-A9 processor. The bottom part shows the programmable logic, which can be configured with a set of pre-compiled accelerators (s). The accelerators are connected by an interconnection network that could be a bus or Network-on-Chip (NoC) depending upon the number of s to support [4]. The accelerators and the CPU cores communicate through the AMBA (ARM Advanced Microcontroller Bus Architecture) interconnection, which is an open standard, on-chip intereconnect specification for the connection and management of functional blocks in system-on-chip (SoC) designs. Figure 2: Xilinx Zynq SoC block diagram [5]. Version 1.01 Page 3

8 In the industrial use-case to be evaluated in deliverable D6.4, this conceptual architecture is expected to process the streams received by a satellite feed or stored by prior streaming. The main reason behind choosing this architecture is that it can be used where data streams are received continuously and sent for processing to various nodes at run-time. Further, it provides the opportunity to balance the load over the nodes and accelerate some heavy computations by using reconfigurable hardware. The DreamCloud project aims to address the load balancing and acceleration requirements, which could arise to process a heavy computation request or multiple requests for the same video content. The industrial use-case will exploit this architecture mainly to process the Micro Cloud (video processing) workload (from the transcoding applications) to be provided by the industrial partner Rheon Media. The nodes in the architecture could be located in different flats/houses and could act as DreamCloud media servers 1. For various users requesting different kinds of streams to different devices (e.g., laptop, phone, etc.) the processing can be distributed to various nodes such that the loads of the nodes are balanced. Such distribution for balanced load processing is to be achieved by the resource allocation approaches developed in work package 2 (D2.1, D2.2 and D2.3). In case of performance bottleneck, identified compute intensive components can be offloaded to the reconfigurable area. These components can be compiled in advance in the form of s so that they can be used to configure the FPGAs whenever acceleration is required. In the prototype release, the OS allocation and migration infrastructure was developed for one node of the architecture shown in Figure 1. The deliverable D4.3 provides the details of the node, where Linux OS runs on the dual-core ARM Cortex-A9 processor of the node in order to facilitate efficient allocation and migration. A simple example application specified in high level language was run on a real-time Java Virtual Machine (VM) instantiated under the Linux running on the ARM processor. The OS support for various kinds of migrations was introduced in D4.3. Additionally, the acceleration approach to be followed to offload the compute intensive components on the reconfigurable area was introduced. 1 There maybe one or more servers depending on the reachability and latency between sets of nodes Page 4 Version 1.01

9 3 OS Support for Migration D4.5 OS Allocation and Migration Support Final Release For our conceptual migration architecture, OS support is developed for each node, where the OS can reserve an appropriate amount of resources, bandwidth and prioritize processes to access the resources (e.g., processors and networks). We choose Linux OS as it can cope with the diversity in the hardware architecture in foreseeable future. Additionally, it offers several advantages such as ability to modify it for our needs as it is open source, its availability for most of the hardware platforms and the existence of a big list of libraries and tools that could be used for the development. Linux on nodes (done) Figure 3 provides an overview of the conceptual architecture, where Linux OS is running on each node. We chose PetaLinux as it is a full Linux distribution which includes the Linux OS as well as a complete configuration, Linux working build and deploy on environment different fornodes, Xilinx silicon, i.e. provided each by Xilinx [3]. Further, it is fully node featured, acts integrated, as atested, PC and with documented, its IPandaddress, thus recommended to be used. By running Linux on each node, the nodes act as PCs with their IP addresses, enabling communication enabling communication between nodes between nodes via simple Linux commands for communication. Linux Linux Linux Linux JVM on each node of microcloud architecture Figure 3: Conceptual (ongoing) architecture with Linux OS running on each node. Communication between the 4 FPGA boards over the fibre as well Trying now, hopefully will be done soon As mentioned earlier in the overview of the prototype release, the application/task is executed on a real-time Java Virtual Machine (JVM) instantiated under the Linux running on the ARM processor. Therefore, JVM is installed on each node as shown in Figure 4. This JVM is provided by the Project Review 6 industrial partner Aicas. JVM JVM JVM JVM Linux Linux Linux Linux Figure 4: Conceptual architecture with Linux OS and JVM running on each node. The applications/tasks are to be executed on the JVM and these applications are modeled as Open Services Gateway Initiative (OSGi) bundles. The OSGi defines an infrastructure for developing and deploying Project modular Review applications and libraries. This infrastructure 8 allows us to break a complex application into multiple modules that can be managed more easily. These modules are also referred to as Version 1.01 Page 5

10 OSGi bundles, as mentioned earlier. They hide their internals from other bundles and communicate through well defined services. This provides more freedom for changing at later stages, reduces the number of bugs and makes the development of bundles simpler, which implements a piece of computation (functionality) through well defined interfaces. The OS s offers several other advantages as mentioned in D4.3. Figure 5 shows some example applications modeled as OSGi bundles (T) and installed and running on JVMs on each node within an OSGi container. The OSGi container can contain and execute multiple bundles as shown in the figure. Figure 5: Applications (Ts) running on different nodes within JVM. 3.1 Migration of Bundles Between Nodes To support migration of bundles between nodes, freeze and resume techniques are employed, where the bundles are frozen, migrated to a destination JVM and resumed on the destination. Figure 6 shows the process of migrating a bundle (highlighted with distinct color) from one node to another. For the bundle, once the migration request is received or a need of migration arises due to load balancing requirement, the bundle is freezed on the currently running node, migrated to the destination node, and resumed on the destination node to start the processing from the current state. Such required techniques are developed by the industrial project partner and detailed into deliverable D4.4. During the execution of a bundle at run-time, monitoring of the bundle and system infrastructure takes place in order to identify the need for migration of the bundle to some other node, which is possibly less loaded. Figure 6: Migration process to migrate bundles between nodes. Page 6 Version 1.01

11 In order to keep the migration overhead low, the bundles that might need migrations are installed on each node so that only the state of a bundle needs to be transferred. Then, the bundle on the destination node can be started with the current received state. This facilitates to achieve executions without long delays that might incur to send the whole program code of the bundles from one node to another. In order to explain the migration, we can consider as an example the migration of a simple counter application. In this example, the migration is started when the board running a bundle receives the request to migrate the running bundle to another board. That request is a text message with the structure migrate <bundle-id> 2 <destination-board>. It is sent and received through an XMPP (Extensible Messaging and Presence Protocol) server. The board freezes the bundle and sends the current state and a bundle activation request as an XMPP message to the destination board. In this example, the migration order is given to the XMPP shell extension, which parses the command and then uses the migration API to trigger the migration. In Deliverable 6.4 (validation in video domain), the heuristics will be communicating with the JavaDispatcher service to trigger migration. The JavaDispatcher will in its turn use the migration API to execute the orders coming from the heuristics. The decision to use XMPP lies in the fact that it is a well known established standard, and it is a realtime communication protocol which includes chat. It has been known as Jabber; however, as Jabber was not the only software relying on XMPP, it has been renamed to XMPP. We use the Spark as XMPP client and Openfire 3 as XMPP server, both installed in one of the boards. We use these client and server software when testing on the boards, because our partner aicas has been using them when developing the bundles due to aforementioned benefits. Notice that we are running, during the test of migrating bundles, the Openfire server in one of the boards, and Spark-XMPP- Client for sending the migration request message, but in the industrial use-case the XMPP server can run in a remote server, and there is not need for any XMPP-Client since the OSGi containers will establish their own XMPP connections. The detailed exploitation of these migration mechanisms and tools for industrial partner use-case application will take place in work package 6. In the next section, we show the exploitation of the migration mechanisms for a simple counter application. 3.2 Test of Migrating Bundles Between Nodes The migration process described earlier has been tested by a counter application that is migrated from one node to another after sending manually a migration request [2]. Figures 7 and 8 shows such process, where the counter application executing on one node was counting when the migration request is received. In Figure 8, a different counting bundle resumes the counting from the last value counted before the migration. As mentioned earlier, the counter bundle is installed on each node so that migration overhead is minimized. 2 Each bundle gets an unique identification number, this value is used as <bundle-id>. 3 Openfire is a real time collaboration (RTC) server licensed under the Open Source Apache License. It uses the XMPP protocol and can be managed via a web interface. It is easy to setup and configure, but has a high level of security and performance. It runs using Java. It should be noted that with Openfire, no chat is possible yet. A client is needed: Openfire cannot be used alone, just like web servers need a browser. Version 1.01 Page 7

12 Figure 7: Counter bundle is running when a migration request is received. Figure 8: Counter bundle starts counting from last state of the freeze bundle. In order to perform the migration example just described, it was required to start a Openfire server. In this test, we run the Openfire in one of the boards. Figure 9 shows the configuration webpage of Openfire server, on which we can see 3 users connected. The users corresponds to the XMPP bundles connected to the server, whose names come from the last 4 characters of the MAC address 4 of the board where they are running. It was decided to define names in such way to avoid confusions or future errors. The 3 XMPP bundles connected appear as 0194, 0197, and C In order for a network device to be able to communicate, the MAC Address it is using must be unique. No other device on that local network subnet can use that MAC address. Page 8 Version 1.01

13 Figure 9: Management webpage of the Openfire server showing established connections. The migration message is generated manually in this test. It is sent from a Spark XMPP client which allows to send chat text messages. We were logged in the Openfire with Spark using the account admin. The figure 10 shows on the right the list of possible chat destinations when logged as admin. On the left, there is the chat window showing the last message sent to user 0194, the content of the message was migrate @localhost/Smack. The message request that XMPP bundle logged as 0194 migrates the bundle number 20 running on same board, to the board where the XMPP bundle logged as 0197 is running. Figure 10: Spark XMPP client. The left hand side shows sending chat message text window, and the right hand side shows the connected users available to chat. Version 1.01 Page 9

14 4 Conclusion This document has introduced the OS allocation and migration support in terms of tools and documentation. The OS support has been tested for an example counter application in order to successfully migrate the counter bundle from one node to another and for offloading a simple function to FPGA. The followed migration techniques are introduced in D4.2 and D4.4. The technique adopted to offload a function to FPGA is introduced in D4.3. In the industrial use-case study (D6.4), multiple applications will need to be allocated on the nodes. To accomplish the same, we plan to exploit the resource allocation approached reported in work package 2 (D2.1, D2.2 and D2.3). This will be realized after receiving the transcoder and other required bundles from the industrial partner. The transcoder bundles will be installed on the nodes in order to observe the capacity of the nodes, and the resource allocation will be performed such that load on the nodes is balanced. The load balanced allocation is expected to lead to high performance. To support multiple applications on a node, the hierarchical scheduling approach introduced in D4.3 will be exploited. Page 10 Version 1.01

15 5 References [1] Zynq-7000 All Programmable SoC, [2] Migration of bundles in the JamaicaVM framework, [3] Petalinux full linux distribution, (Last visited: 3 March, 2016). [4] Luca Benini and Giovanni De Micheli. Networks on chips: a new SoC paradigm. Computer, (1):70 78, [5] Xilinx Kees Vissers. Programming novel recognition algorithms on heterogeneous architectures. In Embedded vision submit, Version 1.01 Page 11

D6.1 Integration Report

D6.1 Integration Report Project Number 611411 D6.1 Integration Report Version 1.0 Final Public Distribution Bosch with contributions from all partners Project Partners: aicas, Bosch, CNRS, Rheon Media, The Open Group, University

More information

D5.3 Accurate Simulation Platforms

D5.3 Accurate Simulation Platforms Project Number 611411 D5.3 Accurate Simulation Platforms Version 2.0 Final Public Distribution CNRS, Bosch Project Partners: aicas, Bosch, CNRS, Rheon Media, The Open Group, University of Stuttgart, University

More information

University of York, University of Stuttgart

University of York, University of Stuttgart Project Number 611411 D1.2 Dynamic Resource Allocation Requirements Version 1.0 30 April 2014 Final EC Distribution University of York, University of Stuttgart Project Partners: Aicas, Bosch, CNRS, Rheon

More information

D3.5 Operating System with Real-Time Support and FPGA Interface

D3.5 Operating System with Real-Time Support and FPGA Interface Project Number 318763 D3.5 Operating ystem with Real-Time upport and FPGA Interface Version 1.0 Final Public Distribution cuola uperiore ant Anna, University of York Project Partners: aicas, HMI, petafuel,

More information

D3.8 First Prototype of the Real-time Scheduling Advisor

D3.8 First Prototype of the Real-time Scheduling Advisor Project Number 318763 D3.8 First Prototype of the Real-time Scheduling Advisor Version 1.0 Final EC Distribution Brno University of Technology Project Partners: aicas, HMI, petafuel, SOFTEAM, Scuola Superiore

More information

D 3.6 FPGA implementation of self-timed NOC

D 3.6 FPGA implementation of self-timed NOC Project Number 288008 D 3.6 FPGA implementation of self-timed NOC Version 1.0 Final Public Distribution Technical University of Denmark Project Partners: AbsInt Angewandte Informatik, Eindhoven University

More information

D2.3 Static Acceleration Design

D2.3 Static Acceleration Design Project Number 318763 D2.3 Static Acceleration Design Version 1.0 Final Public Distribution University of York, aicas, SOFTEAM Scuola Superiore Sant Anna, University of Stuttgart Project Partners: aicas,

More information

D3.6 Final Operating System with Real-Time Support

D3.6 Final Operating System with Real-Time Support Project Number 318763 D3.6 Final Operating System with Real-Time Support Version 1.0 Final Public Distribution Scuola Superiore Sant Anna Project Partners: aicas, HMI, petafuel, SOFTEAM, Scuola Superiore

More information

Simplify System Complexity

Simplify System Complexity Simplify System Complexity With the new high-performance CompactRIO controller Fanie Coetzer Field Sales Engineer Northern South Africa 2 3 New control system CompactPCI MMI/Sequencing/Logging FieldPoint

More information

Simplify System Complexity

Simplify System Complexity 1 2 Simplify System Complexity With the new high-performance CompactRIO controller Arun Veeramani Senior Program Manager National Instruments NI CompactRIO The Worlds Only Software Designed Controller

More information

Enyx soft-hardware design services and development framework for FPGA & SoC

Enyx soft-hardware design services and development framework for FPGA & SoC soft-hardware design services and development framework for FPGA & SoC Smart NIC Smart Switch Your custom hardware hardware acceleration experts 3rd party IP Cores AXI ARM DMA CPU Your own soft-hardware

More information

Optimizing ARM SoC s with Carbon Performance Analysis Kits. ARM Technical Symposia, Fall 2014 Andy Ladd

Optimizing ARM SoC s with Carbon Performance Analysis Kits. ARM Technical Symposia, Fall 2014 Andy Ladd Optimizing ARM SoC s with Carbon Performance Analysis Kits ARM Technical Symposia, Fall 2014 Andy Ladd Evolving System Requirements Processor Advances big.little Multicore Unicore DSP Cortex -R7 Block

More information

Bringing the benefits of Cortex-M processors to FPGA

Bringing the benefits of Cortex-M processors to FPGA Bringing the benefits of Cortex-M processors to FPGA Presented By Phillip Burr Senior Product Marketing Manager Simon George Director, Product & Technical Marketing System Software and SoC Solutions Agenda

More information

Model-Based Design for effective HW/SW Co-Design Alexander Schreiber Senior Application Engineer MathWorks, Germany

Model-Based Design for effective HW/SW Co-Design Alexander Schreiber Senior Application Engineer MathWorks, Germany Model-Based Design for effective HW/SW Co-Design Alexander Schreiber Senior Application Engineer MathWorks, Germany 2013 The MathWorks, Inc. 1 Agenda Model-Based Design of embedded Systems Software Implementation

More information

SoC Systeme ultra-schnell entwickeln mit Vivado und Visual System Integrator

SoC Systeme ultra-schnell entwickeln mit Vivado und Visual System Integrator SoC Systeme ultra-schnell entwickeln mit Vivado und Visual System Integrator FPGA Kongress München 2017 Martin Heimlicher Enclustra GmbH Agenda 2 What is Visual System Integrator? Introduction Platform

More information

Next Generation Enterprise Solutions from ARM

Next Generation Enterprise Solutions from ARM Next Generation Enterprise Solutions from ARM Ian Forsyth Director Product Marketing Enterprise and Infrastructure Applications Processor Product Line Ian.forsyth@arm.com 1 Enterprise Trends IT is the

More information

Big.LITTLE Processing with ARM Cortex -A15 & Cortex-A7

Big.LITTLE Processing with ARM Cortex -A15 & Cortex-A7 Big.LITTLE Processing with ARM Cortex -A15 & Cortex-A7 Improving Energy Efficiency in High-Performance Mobile Platforms Peter Greenhalgh, ARM September 2011 This paper presents the rationale and design

More information

INT G bit TCP Offload Engine SOC

INT G bit TCP Offload Engine SOC INT 10011 10 G bit TCP Offload Engine SOC Product brief, features and benefits summary: Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured ASIC flow.

More information

Copyright 2014 Xilinx

Copyright 2014 Xilinx IP Integrator and Embedded System Design Flow Zynq Vivado 2014.2 Version This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able

More information

Profiling and Debugging OpenCL Applications with ARM Development Tools. October 2014

Profiling and Debugging OpenCL Applications with ARM Development Tools. October 2014 Profiling and Debugging OpenCL Applications with ARM Development Tools October 2014 1 Agenda 1. Introduction to GPU Compute 2. ARM Development Solutions 3. Mali GPU Architecture 4. Using ARM DS-5 Streamline

More information

COMPUTE CLOUD SERVICE. Moving to SPARC in the Oracle Cloud

COMPUTE CLOUD SERVICE. Moving to SPARC in the Oracle Cloud COMPUTE CLOUD SERVICE Moving to A new way forward: SPARC in the. Does your IT organization support mission-critical applications that would benefit from the unsurpassed security performance of SPARC servers

More information

Migration and Building of Data Centers in IBM SoftLayer

Migration and Building of Data Centers in IBM SoftLayer Migration and Building of Data Centers in IBM SoftLayer Advantages of IBM SoftLayer and RackWare Together IBM SoftLayer offers customers the advantage of migrating and building complex environments into

More information

Altera SDK for OpenCL

Altera SDK for OpenCL Altera SDK for OpenCL A novel SDK that opens up the world of FPGAs to today s developers Altera Technology Roadshow 2013 Today s News Altera today announces its SDK for OpenCL Altera Joins Khronos Group

More information

Maximizing heterogeneous system performance with ARM interconnect and CCIX

Maximizing heterogeneous system performance with ARM interconnect and CCIX Maximizing heterogeneous system performance with ARM interconnect and CCIX Neil Parris, Director of product marketing Systems and software group, ARM Teratec June 2017 Intelligent flexible cloud to enable

More information

Unify Virtual and Physical Networking with Cisco Virtual Interface Card

Unify Virtual and Physical Networking with Cisco Virtual Interface Card White Paper Unify Virtual and Physical Networking with Cisco Virtual Interface Card Simplicity of Cisco VM-FEX technology and Power of VMware VMDirectPath What You Will Learn Server virtualization has

More information

SoC Systeme ultra-schnell entwickeln mit Vivado und Visual System Integrator

SoC Systeme ultra-schnell entwickeln mit Vivado und Visual System Integrator SoC Systeme ultra-schnell entwickeln mit Vivado und Visual System Integrator Embedded Computing Conference 2017 Matthias Frei zhaw InES Patrick Müller Enclustra GmbH 5 September 2017 Agenda Enclustra introduction

More information

Multi-core microcontroller design with Cortex-M processors and CoreSight SoC

Multi-core microcontroller design with Cortex-M processors and CoreSight SoC Multi-core microcontroller design with Cortex-M processors and CoreSight SoC Joseph Yiu, ARM Ian Johnson, ARM January 2013 Abstract: While the majority of Cortex -M processor-based microcontrollers are

More information

«Real Time Embedded systems» Multi Masters Systems

«Real Time Embedded systems» Multi Masters Systems «Real Time Embedded systems» Multi Masters Systems rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL Chargé de cours rene.beuchat@hesge.ch LSN/hepia Prof. HES 1 Multi Master on Chip On a System On Chip, Master can

More information

Fault-Tolerant Multiple Task Migration in Mesh NoC s over virtual Point-to-Point connections

Fault-Tolerant Multiple Task Migration in Mesh NoC s over virtual Point-to-Point connections Fault-Tolerant Multiple Task Migration in Mesh NoC s over virtual Point-to-Point connections A.SAI KUMAR MLR Group of Institutions Dundigal,INDIA B.S.PRIYANKA KUMARI CMR IT Medchal,INDIA Abstract Multiple

More information

Adaptable Computing The Future of FPGA Acceleration. Dan Gibbons, VP Software Development June 6, 2018

Adaptable Computing The Future of FPGA Acceleration. Dan Gibbons, VP Software Development June 6, 2018 Adaptable Computing The Future of FPGA Acceleration Dan Gibbons, VP Software Development June 6, 2018 Adaptable Accelerated Computing Page 2 Three Big Trends The Evolution of Computing Trend to Heterogeneous

More information

Building High Performance, Power Efficient Cortex and Mali systems with ARM CoreLink. Robert Kaye

Building High Performance, Power Efficient Cortex and Mali systems with ARM CoreLink. Robert Kaye Building High Performance, Power Efficient Cortex and Mali systems with ARM CoreLink Robert Kaye 1 Agenda Once upon a time ARM designed systems Compute trends Bringing it all together with CoreLink 400

More information

Design of an open hardware architecture for the humanoid robot ARMAR

Design of an open hardware architecture for the humanoid robot ARMAR Design of an open hardware architecture for the humanoid robot ARMAR Kristian Regenstein 1 and Rüdiger Dillmann 1,2 1 FZI Forschungszentrum Informatik, Haid und Neustraße 10-14, 76131 Karlsruhe, Germany

More information

D6.6 MILS Console System

D6.6 MILS Console System Project Number 318772 D6.6 MILS Console System Version 1.0 Final Public Distribution Frequentis, LynuxWorks Project Partners: Fondazione Bruno Kessler, fortiss, Frequentis, LynuxWorks, The Open Group,

More information

FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC)

FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC) FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC) D.Udhayasheela, pg student [Communication system],dept.ofece,,as-salam engineering and technology, N.MageshwariAssistant Professor

More information

AMD ACCELERATING TECHNOLOGIES FOR EXASCALE COMPUTING FELLOW 3 OCTOBER 2016

AMD ACCELERATING TECHNOLOGIES FOR EXASCALE COMPUTING FELLOW 3 OCTOBER 2016 AMD ACCELERATING TECHNOLOGIES FOR EXASCALE COMPUTING BILL.BRANTLEY@AMD.COM, FELLOW 3 OCTOBER 2016 AMD S VISION FOR EXASCALE COMPUTING EMBRACING HETEROGENEITY CHAMPIONING OPEN SOLUTIONS ENABLING LEADERSHIP

More information

FPGA-based Evaluation Platform for Disaggregated Computing

FPGA-based Evaluation Platform for Disaggregated Computing This project has received funding from the European Union s Horizon 2020 research and innovation programme under grant agreement No 687632 FPGA-based Evaluation Platform for Disaggregated Computing Dimitris

More information

SUSE Linux Entreprise Server for ARM

SUSE Linux Entreprise Server for ARM FUT89013 SUSE Linux Entreprise Server for ARM Trends and Roadmap Jay Kruemcke Product Manager jayk@suse.com @mr_sles ARM Overview ARM is a Reduced Instruction Set (RISC) processor family British company,

More information

ISSN Vol.03, Issue.08, October-2015, Pages:

ISSN Vol.03, Issue.08, October-2015, Pages: ISSN 2322-0929 Vol.03, Issue.08, October-2015, Pages:1284-1288 www.ijvdcs.org An Overview of Advance Microcontroller Bus Architecture Relate on AHB Bridge K. VAMSI KRISHNA 1, K.AMARENDRA PRASAD 2 1 Research

More information

Using FPGAs as Microservices

Using FPGAs as Microservices Using FPGAs as Microservices David Ojika, Ann Gordon-Ross, Herman Lam, Bhavesh Patel, Gaurav Kaul, Jayson Strayer (University of Florida, DELL EMC, Intel Corporation) The 9 th Workshop on Big Data Benchmarks,

More information

A Seamless Tool Access Architecture from ESL to End Product

A Seamless Tool Access Architecture from ESL to End Product A Seamless Access Architecture from ESL to End Product Albrecht Mayer Infineon Technologies AG, 81726 Munich, Germany albrecht.mayer@infineon.com Abstract access to processor cores is needed from the first

More information

Vortex Whitepaper. Intelligent Data Sharing for the Business-Critical Internet of Things. Version 1.1 June 2014 Angelo Corsaro Ph.D.

Vortex Whitepaper. Intelligent Data Sharing for the Business-Critical Internet of Things. Version 1.1 June 2014 Angelo Corsaro Ph.D. Vortex Whitepaper Intelligent Data Sharing for the Business-Critical Internet of Things Version 1.1 June 2014 Angelo Corsaro Ph.D., CTO, PrismTech Vortex Whitepaper Version 1.1 June 2014 Table of Contents

More information

Network-on-Chip Architecture

Network-on-Chip Architecture Multiple Processor Systems(CMPE-655) Network-on-Chip Architecture Performance aspect and Firefly network architecture By Siva Shankar Chandrasekaran and SreeGowri Shankar Agenda (Enhancing performance)

More information

Did I Just Do That on a Bunch of FPGAs?

Did I Just Do That on a Bunch of FPGAs? Did I Just Do That on a Bunch of FPGAs? Paul Chow High-Performance Reconfigurable Computing Group Department of Electrical and Computer Engineering University of Toronto About the Talk Title It s the measure

More information

Chapter 1 Overview of Digital Systems Design

Chapter 1 Overview of Digital Systems Design Chapter 1 Overview of Digital Systems Design SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 8, 2017 Why Digital Design? Many times, microcontrollers

More information

Bus AMBA. Advanced Microcontroller Bus Architecture (AMBA)

Bus AMBA. Advanced Microcontroller Bus Architecture (AMBA) Bus AMBA Advanced Microcontroller Bus Architecture (AMBA) Rene.beuchat@epfl.ch Rene.beuchat@hesge.ch Réf: AMBA Specification (Rev 2.0) www.arm.com ARM IHI 0011A 1 What to see AMBA system architecture Derivatives

More information

NVIDIA'S DEEP LEARNING ACCELERATOR MEETS SIFIVE'S FREEDOM PLATFORM. Frans Sijstermans (NVIDIA) & Yunsup Lee (SiFive)

NVIDIA'S DEEP LEARNING ACCELERATOR MEETS SIFIVE'S FREEDOM PLATFORM. Frans Sijstermans (NVIDIA) & Yunsup Lee (SiFive) NVIDIA'S DEEP LEARNING ACCELERATOR MEETS SIFIVE'S FREEDOM PLATFORM Frans Sijstermans (NVIDIA) & Yunsup Lee (SiFive) NVDLA NVIDIA DEEP LEARNING ACCELERATOR IP Core for deep learning part of NVIDIA s Xavier

More information

Transforming the way people watch TV

Transforming the way people watch TV Transforming the way people watch TV Nokia Siemens Networks Ubiquity Multiscreen TV Platform - Executive summary An open solution for delivering TV and Internet as a single service on any device over any

More information

Rapid-Prototyping Emulation System using a SystemC Control System Environment and Reconfigurable Multimedia Hardware Development Platform

Rapid-Prototyping Emulation System using a SystemC Control System Environment and Reconfigurable Multimedia Hardware Development Platform Rapid-Prototyping Emulation System using a SystemC System Environment and Reconfigurable Multimedia Development Platform DAVE CARROLL, RICHARD GALLERY School of Informatics and Engineering, Institute of

More information

Scalable Middleware Environment for Agent-Based Internet Applications]

Scalable Middleware Environment for Agent-Based Internet Applications] Scalable Middleware Environment for Agent-Based Internet Applications] Benno J. Overeinder and Frances M.T. Brazier Department of Computer Science, Vrije Universiteit Amsterdam De Boelelaan 1081a, 1081

More information

RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures

RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures Presentation Brief RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures Delivers Independent Resource Scaling, Open Source, and Modular Chip Design for Big Data and Fast Data Environments

More information

Shared Address Space I/O: A Novel I/O Approach for System-on-a-Chip Networking

Shared Address Space I/O: A Novel I/O Approach for System-on-a-Chip Networking Shared Address Space I/O: A Novel I/O Approach for System-on-a-Chip Networking Di-Shi Sun and Douglas M. Blough School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA

More information

mbed OS Update Sam Grove Technical Lead, mbed OS June 2017 ARM 2017

mbed OS Update Sam Grove Technical Lead, mbed OS June 2017 ARM 2017 mbed OS Update Sam Grove Technical Lead, mbed OS June 2017 ARM mbed: Connecting chip to cloud Device software Device services Third-party cloud services IoT device application mbed Cloud Update IoT cloud

More information

Cost-Optimized Backgrounder

Cost-Optimized Backgrounder Cost-Optimized Backgrounder A Cost-Optimized FPGA & SoC Portfolio for Part or All of Your System Optimizing a system for cost requires analysis of every silicon device on the board, particularly the high

More information

S2C K7 Prodigy Logic Module Series

S2C K7 Prodigy Logic Module Series S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device

More information

HETEROGENEOUS SYSTEM ARCHITECTURE: PLATFORM FOR THE FUTURE

HETEROGENEOUS SYSTEM ARCHITECTURE: PLATFORM FOR THE FUTURE HETEROGENEOUS SYSTEM ARCHITECTURE: PLATFORM FOR THE FUTURE Haibo Xie, Ph.D. Chief HSA Evangelist AMD China OUTLINE: The Challenges with Computing Today Introducing Heterogeneous System Architecture (HSA)

More information

Hypervisors at Hyperscale

Hypervisors at Hyperscale Hypervisors at Hyperscale ARM, Xen, Servers and Evolution of the Data Center Larry Wikelius Co-Founder & VP Software 1 Overview l Market Dynamics l Technology Trends l Roadmaps Where are we today l Use

More information

Stellar performance for a virtualized world

Stellar performance for a virtualized world IBM Systems and Technology IBM System Storage Stellar performance for a virtualized world IBM storage systems leverage VMware technology 2 Stellar performance for a virtualized world Highlights Leverages

More information

Unleashing the benefits of GPU Computing with ARM Mali TM Practical applications and use-cases. Steve Steele, ARM

Unleashing the benefits of GPU Computing with ARM Mali TM Practical applications and use-cases. Steve Steele, ARM Unleashing the benefits of GPU Computing with ARM Mali TM Practical applications and use-cases Steve Steele, ARM 1 Today s Computational Challenges Trends Growing display sizes and resolutions, richer

More information

What s New in VMware vsphere 4.1 Performance. VMware vsphere 4.1

What s New in VMware vsphere 4.1 Performance. VMware vsphere 4.1 What s New in VMware vsphere 4.1 Performance VMware vsphere 4.1 T E C H N I C A L W H I T E P A P E R Table of Contents Scalability enhancements....................................................................

More information

Broadcast-Quality, High-Density HEVC Encoding with AMD EPYC Processors

Broadcast-Quality, High-Density HEVC Encoding with AMD EPYC Processors Solution Brief December, 2018 2018 Broadcast-Quality, High-Density HEVC Encoding with AMD EPYC Processors HIGHLIGHTS o The AMD EPYC SoC brings a new balance to the datacenter. Utilizing an x86-architecture,

More information

CMP Conference 20 th January Director of Business Development EMEA

CMP Conference 20 th January Director of Business Development EMEA CMP Conference 20 th January 2011 eric.lalardie@arm.com Director of Business Development EMEA +33 6 07 83 09 60 1 1 Unparalleled Applicability ARM Cortex Advanced Processors Architectural innovation, compatibility

More information

SoftFlash: Programmable Storage in Future Data Centers Jae Do Researcher, Microsoft Research

SoftFlash: Programmable Storage in Future Data Centers Jae Do Researcher, Microsoft Research SoftFlash: Programmable Storage in Future Data Centers Jae Do Researcher, Microsoft Research 1 The world s most valuable resource Data is everywhere! May. 2017 Values from Data! Need infrastructures for

More information

A unified multicore programming model

A unified multicore programming model A unified multicore programming model Simplifying multicore migration By Sven Brehmer Abstract There are a number of different multicore architectures and programming models available, making it challenging

More information

Chapter 17: Distributed Systems (DS)

Chapter 17: Distributed Systems (DS) Chapter 17: Distributed Systems (DS) Silberschatz, Galvin and Gagne 2013 Chapter 17: Distributed Systems Advantages of Distributed Systems Types of Network-Based Operating Systems Network Structure Communication

More information

4. Hardware Platform: Real-Time Requirements

4. Hardware Platform: Real-Time Requirements 4. Hardware Platform: Real-Time Requirements Contents: 4.1 Evolution of Microprocessor Architecture 4.2 Performance-Increasing Concepts 4.3 Influences on System Architecture 4.4 A Real-Time Hardware Architecture

More information

Developing Core Software Technologies for TI s OMAP Platform

Developing Core Software Technologies for TI s OMAP Platform SWPY006 - August 2002 White Paper By Justin Helmig Texas Instruments Senior Technical Staff, Wireless Software Applications Texas Instruments OMAP platform for wireless handsets offers a powerful hardware

More information

Introduction Optimizing applications with SAO: IO characteristics Servers: Microsoft Exchange... 5 Databases: Oracle RAC...

Introduction Optimizing applications with SAO: IO characteristics Servers: Microsoft Exchange... 5 Databases: Oracle RAC... HP StorageWorks P2000 G3 FC MSA Dual Controller Virtualization SAN Starter Kit Protecting Critical Applications with Server Application Optimization (SAO) Technical white paper Table of contents Introduction...

More information

IQ for DNA. Interactive Query for Dynamic Network Analytics. Haoyu Song. HUAWEI TECHNOLOGIES Co., Ltd.

IQ for DNA. Interactive Query for Dynamic Network Analytics. Haoyu Song.   HUAWEI TECHNOLOGIES Co., Ltd. IQ for DNA Interactive Query for Dynamic Network Analytics Haoyu Song www.huawei.com Motivation Service Provider s pain point Lack of real-time and full visibility of networks, so the network monitoring

More information

XPU A Programmable FPGA Accelerator for Diverse Workloads

XPU A Programmable FPGA Accelerator for Diverse Workloads XPU A Programmable FPGA Accelerator for Diverse Workloads Jian Ouyang, 1 (ouyangjian@baidu.com) Ephrem Wu, 2 Jing Wang, 1 Yupeng Li, 1 Hanlin Xie 1 1 Baidu, Inc. 2 Xilinx Outlines Background - FPGA for

More information

China Big Data and HPC Initiatives Overview. Xuanhua Shi

China Big Data and HPC Initiatives Overview. Xuanhua Shi China Big Data and HPC Initiatives Overview Xuanhua Shi Services Computing Technology and System Laboratory Big Data Technology and System Laboratory Cluster and Grid Computing Laboratory Huazhong University

More information

PI System Pervasive Data Collection

PI System Pervasive Data Collection PI System Pervasive Data Collection Presented by Christian Leroux Enterprise Program Manager Chris Felts Sr. Product Manager OSIsoft on Industrial IoT Connecting people with sensor based data in ways that

More information

Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA. Singh, A.K.; Kumar, A.; Srikanthan, Th.; Ha, Y.

Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA. Singh, A.K.; Kumar, A.; Srikanthan, Th.; Ha, Y. Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA. Singh, A.K.; Kumar, A.; Srikanthan, Th.; Ha, Y. Published in: Proceedings of the 2010 International Conference on Field-programmable

More information

FPGA BASED ADAPTIVE RESOURCE EFFICIENT ERROR CONTROL METHODOLOGY FOR NETWORK ON CHIP

FPGA BASED ADAPTIVE RESOURCE EFFICIENT ERROR CONTROL METHODOLOGY FOR NETWORK ON CHIP FPGA BASED ADAPTIVE RESOURCE EFFICIENT ERROR CONTROL METHODOLOGY FOR NETWORK ON CHIP 1 M.DEIVAKANI, 2 D.SHANTHI 1 Associate Professor, Department of Electronics and Communication Engineering PSNA College

More information

Midterm Exam. Solutions

Midterm Exam. Solutions Midterm Exam Solutions Problem 1 List at least 3 advantages of implementing selected portions of a design in hardware, and at least 3 advantages of implementing the remaining portions of the design in

More information

Introduction to data centers

Introduction to data centers Introduction to data centers Paolo Giaccone Notes for the class on Switching technologies for data centers Politecnico di Torino December 2017 Cloud computing Section 1 Cloud computing Giaccone (Politecnico

More information

Copyright 2016 Xilinx

Copyright 2016 Xilinx Zynq Architecture Zynq Vivado 2015.4 Version This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able to: Identify the basic building

More information

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow Abstract: High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture

More information

Chapter 2. Literature Survey. 2.1 Remote access technologies

Chapter 2. Literature Survey. 2.1 Remote access technologies Chapter 2 Literature Survey This chapter presents a brief report on literature reviewed in context to present work with an aim to identify current state of research in the domain. Literature review is

More information

SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS

SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS Embedded System System Set of components needed to perform a function Hardware + software +. Embedded Main function not computing Usually not autonomous

More information

Overview of ROCCC 2.0

Overview of ROCCC 2.0 Overview of ROCCC 2.0 Walid Najjar and Jason Villarreal SUMMARY FPGAs have been shown to be powerful platforms for hardware code acceleration. However, their poor programmability is the main impediment

More information

Apache Hadoop 3. Balazs Gaspar Sales Engineer CEE & CIS Cloudera, Inc. All rights reserved.

Apache Hadoop 3. Balazs Gaspar Sales Engineer CEE & CIS Cloudera, Inc. All rights reserved. Apache Hadoop 3 Balazs Gaspar Sales Engineer CEE & CIS balazs@cloudera.com 1 We believe data can make what is impossible today, possible tomorrow 2 We empower people to transform complex data into clear

More information

Cloud Security Gaps. Cloud-Native Security.

Cloud Security Gaps. Cloud-Native Security. Cloud Security Gaps Cloud-Native Security www.aporeto.com Why Network Segmentation is Failing Your Cloud Application Security How to Achieve Effective Application Segmentation By now it s obvious to security-minded

More information

Brocade Virtual Traffic Manager and Parallels Remote Application Server

Brocade Virtual Traffic Manager and Parallels Remote Application Server White Paper Parallels Brocade Virtual Traffic Manager and Parallels Deployment Guide 01 Contents Preface...4 About This Guide...4 Audience...4 Contacting Brocade...4 Internet...4 Technical Support...4

More information

ARM SERVER STANDARDIZATION

ARM SERVER STANDARDIZATION ARM SERVER STANDARDIZATION (and a general update on some happenings at Red Hat) Jon Masters, Chief ARM Architect, Red Hat 6+ YEARS OF ARM AT RED HAT Red Hat ARM Team formed in March 2011 Bootstrapped ARMv8

More information

Building blocks for 64-bit Systems Development of System IP in ARM

Building blocks for 64-bit Systems Development of System IP in ARM Building blocks for 64-bit Systems Development of System IP in ARM Research seminar @ University of York January 2015 Stuart Kenny stuart.kenny@arm.com 1 2 64-bit Mobile Devices The Mobile Consumer Expects

More information

Chapter 4: Threads. Overview Multithreading Models Thread Libraries Threading Issues Operating System Examples Windows XP Threads Linux Threads

Chapter 4: Threads. Overview Multithreading Models Thread Libraries Threading Issues Operating System Examples Windows XP Threads Linux Threads Chapter 4: Threads Overview Multithreading Models Thread Libraries Threading Issues Operating System Examples Windows XP Threads Linux Threads Chapter 4: Threads Objectives To introduce the notion of a

More information

Don t Think You Need an FPGA? Think Again!

Don t Think You Need an FPGA? Think Again! 1 Don t Think You Need an FPGA? Think Again! Arun Veeramani Senior Program Manager National Instruments Don t Think You Need an FPGA? Think Again! Goals for Today Define and explain FPGAs Address common

More information

Revolutionizing Open. Cecilia Carniel IBM Power Systems Scale Out sales

Revolutionizing Open. Cecilia Carniel IBM Power Systems Scale Out sales Revolutionizing Open Cecilia Carniel IBM Power Systems Scale Out sales cecilia_carniel@it.ibm.com Copyright IBM Corporation 2015 Technical University/Symposia materials may not be reproduced in whole or

More information

Vernetzte Fahrerassistenzsysteme (BMW + AWS ) Hazard Preview

Vernetzte Fahrerassistenzsysteme (BMW + AWS ) Hazard Preview + = Vernetzte Fahrerassistenzsysteme (BMW + AWS ) Hazard Preview Andreas Winckler BMW EE-51 Location Based Services Walter Pernstecher AWS Enterprise Account Management Gartner Magic Quadrant for Cloud

More information

ARM Trusted Firmware From Embedded to Enterprise. Dan Handley

ARM Trusted Firmware From Embedded to Enterprise. Dan Handley ARM Trusted Firmware From Embedded to Enterprise Dan Handley Agenda Quick recap Project news Security hardening AArch32 support ENGINEERS AND DEVICES WORKING TOGETHER Other enhancements Translation table

More information

ADQ14-FWATD. User Guide. Author(s): SP Devices Document no.: Classification: Public Revision: PA7 Date:

ADQ14-FWATD. User Guide. Author(s): SP Devices Document no.: Classification: Public Revision: PA7 Date: ADQ14-FWATD User Guide Author(s: SP Devices Document no.: 16-1849 Classification: Revision: Date: 2018-03-02 Contents 1 Introduction 3 1.1 Definitions & Abbreviations...................................

More information

Reconfigurable Architecture Requirements for Co-Designed Virtual Machines

Reconfigurable Architecture Requirements for Co-Designed Virtual Machines Reconfigurable Architecture Requirements for Co-Designed Virtual Machines Kenneth B. Kent University of New Brunswick Faculty of Computer Science Fredericton, New Brunswick, Canada ken@unb.ca Micaela Serra

More information

OPERA. Low Power Heterogeneous Architecture for the Next Generation of Smart Infrastructure and Platforms in Industrial and Societal Applications

OPERA. Low Power Heterogeneous Architecture for the Next Generation of Smart Infrastructure and Platforms in Industrial and Societal Applications OPERA Low Power Heterogeneous Architecture for the Next Generation of Smart Infrastructure and Platforms in Industrial and Societal Applications Co-funded by the Horizon 2020 Framework Programme of the

More information

SDACCEL DEVELOPMENT ENVIRONMENT. The Xilinx SDAccel Development Environment. Bringing The Best Performance/Watt to the Data Center

SDACCEL DEVELOPMENT ENVIRONMENT. The Xilinx SDAccel Development Environment. Bringing The Best Performance/Watt to the Data Center SDAccel Environment The Xilinx SDAccel Development Environment Bringing The Best Performance/Watt to the Data Center Introduction Data center operators constantly seek more server performance. Currently

More information

Juniper Care Plus Advanced Services Credits

Juniper Care Plus Advanced Services Credits Juniper Care Plus Advanced Services Credits Service Overview Today s organizations are under constant pressure to meet dynamic market demands while increasing their return on investment. IT departments

More information

Extending the Power of FPGAs to Software Developers:

Extending the Power of FPGAs to Software Developers: Extending the Power of FPGAs to Software Developers: The Journey has Begun Salil Raje Xilinx Corporate Vice President Software and IP Products Group Page 1 Agenda The Evolution of FPGAs and FPGA Programming

More information

20 Fast Facts About Microsoft Windows Server 2012

20 Fast Facts About Microsoft Windows Server 2012 20 Fast Facts About Microsoft Windows Server 2012 Laying the Cornerstone of the Next Generation of Computing Contents Virtualization and the Cloud................................................2 Data

More information

App-ID. PALO ALTO NETWORKS: App-ID Technology Brief

App-ID. PALO ALTO NETWORKS: App-ID Technology Brief App-ID Application Protocol Detection / Decryption Application Protocol Decoding Application Signature Heuristics App-ID is a patent-pending traffic classification technology that identifies more than

More information

The CoreConnect Bus Architecture

The CoreConnect Bus Architecture The CoreConnect Bus Architecture Recent advances in silicon densities now allow for the integration of numerous functions onto a single silicon chip. With this increased density, peripherals formerly attached

More information

10 th AUTOSAR Open Conference

10 th AUTOSAR Open Conference 10 th AUTOSAR Open Conference Ravi Akella, Software Researcher Akihito Iwai, Director Silicon Valley Innovation Center DENSO International America, Inc. Integrating an actor based connected car platform

More information