SoC Systeme ultra-schnell entwickeln mit Vivado und Visual System Integrator
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1 SoC Systeme ultra-schnell entwickeln mit Vivado und Visual System Integrator Embedded Computing Conference 2017 Matthias Frei zhaw InES Patrick Müller Enclustra GmbH 5 September 2017
2 Agenda Enclustra introduction What is Visual System Integrator? Introduction Platform System
3 Enclustra Company Profile Focused on FPGA Technology Everything FPGA! Founded in 2004 successfully in business for 13 years! Headquarters in Zürich, Switzerland Branch offices in Germany, USA and China 2 Business units: FPGA Design Center, FPGA Solution Center 30 employees: 15 FPGA engineers plus 11 staff in Zurich, 4 employees abroad Vendor-Independent
4 Enclustra Company Profile FPGA Design Center Hardware (High-Speed, Analog, RF) HDL firmware (VHDL, Verilog) Embedded software (for FPGA processors) FPGA Solution Center IP-Cores FPGA & SoC Modules FPGA? Enclustra!
5 The Problem Embedded Systems Getting Increasingly Complex System Design Span Multiple Chips (CPUs, GPUs, FPGAs, DSPs.) Difficult to Integrate, No Visibility No Universal Tool Exists for Integration
6 The Solution: Visual System Integrator Rapid, visual application development: Describe the hardware platform. Develop the application by importing C/C++/RTL blocks and interconnecting them Automatic code generation for the complete system: software/hardware projects, drivers, DMAs Get unprecedented transaction-level visibility at runtime through the trace function. Focus on your application, not the platform & firmware!
7 Visual System Integrator: Work Flow Compile Platform Describe Hardware Platform (Import Existing) Software Projects Eclipse, Qt, VC++, Platform Meta data Compile Generate System Runtime, Drivers & OS Configurations Import Platform Develop Application System FPGA Projects
8 Development Context Platform Defines what Chips/Devices are used Defines how these are linked Builds the basis of your system/application Can be reused for different applications System The place where you actually develop your application/system No need to think about links between devices
9 Application Development : Example Import Platform Develop Application TCP SERVER User C/C++ Code Synthesizable C/C++ Function DSP Function Synthesizable C/C++ Function Software Library X86 C/C++ Functions FPGA FPGA Library
10 Platform Basic structure of your project Use existing templates Reusable easily
11 MPSoC + X86 Platform Contexts Connectivity Associated IP & drivers Additional Memory and/or IO X86 (Linux) TCP Server TCP Client Ethernet (TCP/IP) RPMSG Driver Cortex-R5 (FreeRTOS) Shared Memory VirtIO/RPMSG RPMSG Driver Cortex A53 (Linux) DMA Driver AXI DMA IPs Memory UltraScale FPGA Fabric GPIO
12 Supported Platforms Xilinx FPGA and MPSoC Zynq 7000 Ultrascale+ Ultrascale Artix-7 Kintex-7 CPUs ARM ARM64 Linux x86 Roadmap Windows x86 Also runs in the Amazon EC2 F1 cloud!
13 Interconnectivity AXI FPGA Ethernet (TCP/IP) PCIe Shared Memory
14 System The place where your applications is developed. Add blocks using drag-and-drop. Change execution context of a block easily.
15 MPSoC + X86 Application Application TCP Server X86 (Linux) converter control 1 Second Timer Driven Command I/O Driver Compute Block Cortex-R5 (FreeRTOS) Cortex A53 (Linux) UltraScale FPGA Fabric
16 Supported Languages for CPUs C/C++ Java Python
17 Supported Languages for FPGA/SoC Xilinx IPs Synthesizable C/C++ Code Custom VHDL/Verilog Blocks AXI memory mapped AXI streaming interface
18 What VSI does for you Generating FPGA Bitstream Generating Software executables Creating the linux driver with device-tree entry if necessary Script to load the driver with parameters
19 Distribution Problem Pay attention on how to distribute processing across platforms Performance Resources Blocks can be moved per drag-and-drop Measure the performance with Built-in tool
20 System Level Verification - Trace Application detail overview
21 VSI: System Design Life Cycle Define Abstract Platform Create Blocks with interfaces Represent external interfaces Functional system integration Performance analysis Formalize Platform Groups are assigned to tasks External dependencies formalized Blocks moved across Contexts Functional Debug, Co-Simulation Performance analysis Stimulus generation Platform becomes concrete Block designs are completed External interfaces frozen
22 Current Status: Release 1.0 (2017.1) User Interface Platform canvas System canvas Run Time & Transports Road Map Partial Reconfiguration
23
24 Evaluate Visual System Integrator today! 90 days for free!
25 Everything FPGA.
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