Optimizing ARM SoC s with Carbon Performance Analysis Kits. ARM Technical Symposia, Fall 2014 Andy Ladd

Transcription

1 Optimizing ARM SoC s with Carbon Performance Analysis Kits ARM Technical Symposia, Fall 2014 Andy Ladd

2 Evolving System Requirements Processor Advances big.little Multicore Unicore DSP Cortex -R7 Block are now Sub-Systems Cortex -R7 CoreLink NIC-400 Cortex -A57 GIC-500 Cortex -A53 Mali GPU IPU DMA 300 Cortex -M3 CoreLink NIC-400 System Control Evolution big-little DVFS None AXI3 Modem Throughput LTE 4G 3G Edge Video Ctrl LCD Ctrl CoreLink NIC-400 ADB-400 ADB-400 ADB-400 ADB-400 CoreLink CCI-400 TZC-400 TZC-400 TZC-400 TZC-400 MMU-500 Protocol Advances AMBA 5 AXI4 /ACE AXI AHB Video Display 1080p 1080i 720i 480i DDR3/2 LPDDR2 CoreLink DMC-400 DDR3/2 LPDDR2 CoreLink NIC-400 Other Slaves Other Slaves Memory Complexity LPDDR4 DDR4 DDR3 DDR2 Need a solution to enable optimization of systems and subsystems with the understanding of the ideal performance of each piece of IP

3 SoC Optimization IP Selection IP Optimization Subsystem Optimization System Bringup System Optimization IP Level Selection Getting the right IP to meet the design requirements IP Optimization Configuration and optimization of individual IP to understand the Ideal performance in isolation Subsystem Level Optimization Optimizing the IP interactions at a subsystem level System Level System Bring-up Integrating the subsystems into complete a system together with associated firmware System Optimization Optimizing performance of complete the system with software

4 Phase Two Phase Virtual Prototype Methodology 1. Start at the IP level with interconnect and traffic generators Optimize the IP in isolation Tune and understand the idealized performance Start with idealized memory, migrate to real memory and memory controllers 2. Subsystem/System Level a) Add important subsystem components to build subsystem CPUs, GPUs, DMA, Internal IP Add software Find bottlenecks by comparing with idealized performance from phase 1 Optimize and tune subsystem In many cases this will be the final system b) Build out system level by integrating subsystems Exercise system with bare metal software Boot OS to optimize system level performance with OS-level benchmarks Find bottlenecks with the understanding of the performance from the previous stages

5 5 Tools to help us along the way Model Creation -100% accurate models compiled directly from RTL IP Models -Carbon IP Exchange portal offering 100% accurate ARM IP Models Virtual Platforms -Carbon System Exchange portal offering pre-built Carbon Performance Analysis Kits (CPAKs) Architectural Analysis and Firmware Development -SoC Designer provides 100% accuracy for architectural analysis and firmware development -Switch from 100s of MIPS to 100% accuracy at any software breakpoint RTL System Level Model CPAKs IP Models LT Model LT Model LT Model

6 Carbon Performance Analysis Kits Pre-built, extensible virtual prototypes ARM Cortex -A57, Cortex-A53, Cortex- A15, Cortex-A9, Cortex-A7, big.little and more Reconfigurable memory and fabric NIC-400, NIC-301, CCI-400, PL310, etc. Pre-built bare-metal software Pre-built OS ports Swap & Play enabled Execute at 10s to 100s of MIPS Debug with 100% accuracy Source code for all software components Downloadable 24/7 from Carbon System Exchange

7 Leveraging CPAKs GPU GPU Custom Mem Ctlr Custom Mem Ctlr 1. Download CPAK from web portal Contains standard ARM IP configurations Software source for bare metal configuration, OS and benchmarks ARM Fast Model enabled Save weeks in developing platform and software 2. Customize CPAK with differentiating IP Easily replace existing components or add new ones Analyze performance on actual system Quickly iterate on design optimizations Optimize IP against industry benchmarks 3. Deploy CPAK to development teams Early benchmarking on actual SoC design Enable development of bare metal, OS and application code System debug months before emulation, FPGAs or silicon

8 Phase 1: IP Selection Cortex A Processors Cortex-A57 Cortex-A53 Cortex-A15 Cortex-A9 Cortex-A8 Cortex-A7 Cortex-A5 Cortex R Processors Cortex-R7 Cortex-R5 Cortex-R4 Cortex M Processors Cortex-M4 Cortex-M3 Cortex-M0 And many more CoreLink IP NIC-400 NIC-301 PL301 CCI-400 DMC-400 MMU-400 GIC-400 PL34x PL35x Mali GPU Mali-400MP Mali-450MP Mali-55 Mali-T604 Mali-T628 Cores A Series R Series M Series Older Generations CoreLink IP Interconnect Memory Controllers Interrupt Controllers DMA Miscellaneous GPUs

9 Phase 1: IP Optimization CPAKs provide initial starting point Use traffic generators for producers and idealized memory for Consumers Parameterize traffic to mimic system Sweep across various parameters Analyze results Reconfigure Re-simulate reanalyze Can substitute idealized memory with real memory controllers and memory

10 Phase 1: Driving the Traffic Parameterizable traffic Random addresses, data, burst lengths, outstanding transactions, etc. User defined loading to stress system Vector Playback More realistic traffic Easily extracted from components Programmed Traffic Much more configurable Can easily target real functions

11 Phase 1: IP Re-Configuration Build any valid configuration Only valid configurations are buildable 100% accurate model available for download Simple, fast model creation

12 Phase 1: Analyzing Analyze caches, program flow, bus activity, throughput, latency, etc., to find hot spots and problems Multi-run comparison highlights difference in results between different configurations or loads Customize based on your needs

13 Phase 1: Results Benefits Quickly get started early in the project CPAKs provide the starting point Can be done before software is available Before all the IP has been chosen Executes much faster than RTL simulation Easy to examine wide range of possibilities and configurations Corner case targeting Optimize subsystem for ideal behavior Understand what is achievable Important data to understand later when looking for bottlenecks Drawbacks It s not the real system Ideal behavior isn t actual behavior Software and other IP can greatly impact performance

14 Phase 2: Subsystem Optimization Real components enable more accurate decisions Replace traffic generators with real components Interaction between components can have significant impact on performance and coherency Subsystem software plays a pivotal role in characterizing performance Carbon CPAKs provide starting point Contains base subsystem IP, connectivity, and software Bottlenecks are easily found Results from phase 1 provides an understanding of idealized IP performance Refinements typically deliver 25-40% improvement in IP performance

15 Phase 2: Building the Subsystem CPAKs Expand from phase 1 (IP analysis) Replace TG with producers Replace consumers with memory and IO devices Analyze results Reconfigure Re-simulate reanalyze Software provides realistic loads

16 Phase 2: Subsystem Optimization What cache size do I need for MPEG4 decode? Requires cycle accuracy Requires significant number of simulation cycles Requires many configurations to be analysed DSP Hardware Accelerator CPU Level 2 Cache AXI No L2 128K L2 +63% performance increase Dedicated Peripherals Memory Controller Logic 256K L2 +85% performance increase 512K L2 +87% performance increase Relative Performance Benchmark : MPEG4 decode QCIF (foreman bitstream) System : ARM1176ZJ-S / L220 / PL340 CPU : 400MHz ARM1176ZJ-S 16K I & D caches Memory : 100MHz 32 bit DDR SDRAM, ARM PL340 63% increase 3.5mm 2 128K L2 cache 50mm 2 SoC on TSMC 90nm Best performance / cost trade-off

17 Phase 2: System Bring-up Building accurate virtual prototypes for a complete system can be a non-trivial task Memory mapping Device configuration Software configuration System Integration System debug Diverse set of expertise required to model, debug and bring up the system Leverage pre-built systems containing configured IP and software in order to streamline system bring-up CPAKs from Carbon System Exchange

18 Phase 2: Building the System CPAKs help expand from subsystem Additional components needed for system analysis Analyze benchmarks running on the OS Dynamically change abstraction levels (Swap and Play) Analyze results Reconfigure Resimulate reanalyze

19 Phase 2: System Optimization System software is the best way to optimize system performance Bare metal benchmarks to target hardware hot spots OS level benchmarks to highlight areas of hardware/software interaction Requires substantial number of cycles to be run Dynamically switching from behavioral level to cycle accurate is required Get to areas of interest quickly (behavioral simulation) and dynamically switch to cycle accuracy for analysis The earlier it s done, the more optimizations can be made to hardware and software

20 Phase 2: System Bring up Problem: Need to test and optimize driver code for Mali 400 GPU in the system Driver code only runs at the end of Linux boot Need lots of cycles! Solution: Used Fast Model of Dual Cortex A9 Swap and Play with Carbon Cycle Accurate models Compiled MALI RTL using Carbon Model Studio Booted Linux with both ARM Fast Models & Carbon Cycle Accurate Models in the platform Results: Able to validate and tune 3D drivers at the system level in complete virtual environment Built, validated and optimized firmware platform in a matter of days utilizing CPAKs

21 Phase 2: System Optimization Linux Boot F + Frame Frame Frame Frame Frame Frame Frame Frame Frame Frame 5 Min 10 Min 15 Min Speed and accuracy with one platform Leverages 100+ MIPS performance of ARM Fast Models Leverages 100% accuracy of Carbonized IP models Swap and play allows swapping into fully cycle accurate system at any time Boot Linux in less than a minute with Cortex A9 Fast Model system and Carbonized Mali model Display 9 frames of graphics in virtual platform while emulator is still booting Linux

22 Phase 2: Results Benefits Optimize the interaction of IP in the subsystem/system Understanding performance with real SW loading Bottlenecks easily identified because already know idealized performance from phase 1 Application benchmarking Changing abstraction levels (Swap and Play) Gets you to the area of interest quickly in behavioral mode Change to cycle accuracy for analysis Path clearing bring-up to validate the hardware and software is correctly working Resolve integration and configuration issues System Coherency Fast to setup CPAKs provide pre-built virtual platform to do bare metal and OS-level benchmarking Reconfigurable IP to target your end system

23 Summary Two phase approach to bring-up and optimize your ARM SoC IP analysis (understanding idealized performance) Subsystem System analysis (finding bottlenecks) Increased productivity with Carbon Performance Analysis Kits (CPAKs) Pre-built virtual platforms Facilitates building the system without the need for deep domain expertise Pre-built IP models and software make bring-up easy Can be customized to represent your exact system configuration Bare metal and OS level application benchmarking and optimization

24 Thank You Andy Ladd (VP Asia Sales)