SoC Systeme ultra-schnell entwickeln mit Vivado und Visual System Integrator
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1 SoC Systeme ultra-schnell entwickeln mit Vivado und Visual System Integrator FPGA Kongress München 2017 Martin Heimlicher Enclustra GmbH
2 Agenda 2 What is Visual System Integrator? Introduction Platform System Demo Applications Software acceleration: Quick sort Hardware acceleration: Mandelbrot fractal
3 The Problem 3 Embedded Systems Getting Increasingly Complex System Design Span Multiple Chips (CPUs, GPUs, FPGAs, DSPs.) Difficult to Integrate, No Visibility No Universal Tool Exists for Integration
4 4 The Solution: Visual System Integrator Rapid, visual application development: Describe the hardware platform. Develop the application by importing C/C++/RTL blocks and interconnecting them Automatic code generation for the complete system: software/hardware projects, drivers, DMAs Get unprecedented transaction-level visibility at runtime through the trace function. Focus on your application, not the platform & firmware!
5 Visual System Integrator: Work Flow 5 Compile Platform Describe Hardware Platform (Import Existing) Software Projects Eclipse, Qt, VC++, Platform Meta data Compile Generate System Runtime, Drivers & OS Configurations Import Platform Develop Application System FPGA Projects
6 Development Context Platform Defines what Chips/Devices are used Defines how these are linked Builds the basis of your system/application Can be reused for different applications System 6 The place where you actually develop your application/system No need to think about links between devices
7 Application Development : Example 7 Import Platform Develop Application TCP SERVER User C/C++ Code Synthesizable C/C++ Function DSP Function Synthesizable C/C++ Function Software Library X86 C/C++ Functions FPGA FPGA Library
8 Platform 8 Basic structure of your project Use existing templates Reusable easily
9 MPSoC + X86 Platform 9 Contexts Connectivity Associated IP & drivers Additional Memory and/or IO X86 (Linux) TCP Server Ethernet (TCP/IP) TCP Client RPMSG Driver Cortex-R5 (FreeRTOS) Shared Memory VirtIO/RPMSG RPMSG Driver Cortex A53 (Linux) DMA Driver AXI DMA IPs Memory UltraScale FPGA Fabric GPIO
10 Supported Platforms 10 Xilinx FPGA and MPSoC Zynq 7000 Ultrascale+ Ultrascale Artix-7 Kintex-7 CPUs ARM ARM64 Linux x86 Roadmap Windows x86 Also runs in the Amazon EC2 F1 cloud!
11 Interconnectivity 11 AXI FPGA Ethernet (TCP/IP) PCIe Shared Memory
12 System 12 The place where your applications is developed. Add blocks using drag-and-drop. Change execution context of a block easily.
13 MPSoC + X86 Application 13 Application TCP Server X86 (Linux) converter control 1 Second Timer Driven Command I/O Driver Compute Block Cortex-R5 (FreeRTOS) Cortex A53 (Linux) UltraScale FPGA Fabric
14 Supported Languages for CPUs 14 C/C++ Java Python
15 Supported Languages for FPGA/SoC 15 Xilinx IPs Synthesizable C/C++ Code Custom VHDL/Verilog Blocks AXI memory mapped AXI streaming interface
16 What VSI does for you 16 Generating FPGA Bitstream Generating Software executables Creating the linux driver with device-tree entry if necessary Script to load the driver with parameters
17 Distribution Problem 17 Pay attention on how to distribute processing across platforms Performance Resources Blocks can be moved per drag-and-drop Measure the performance with Built-in tool
18 System Level Verification - Trace Application 18 detail overview
19 VSI: System Design Life Cycle 19 Define Abstract Platform Create Blocks with interfaces Represent external interfaces Functional system integration Performance analysis Formalize Platform Groups are assigned to tasks External dependencies formalized Blocks moved across Contexts Functional Debug, Co-Simulation Performance analysis Stimulus generation Platform becomes concrete Block designs are completed External interfaces frozen
20 Current Status: 20 Release 1.0 (2017.1) User Interface Platform canvas System canvas Run Time & Transports Road Map Partial Reconfiguration
21 Examples of Applications 21 Network inline processing Deep Packet Inspection at line speed Industrial Control Robotic ARM Accelerator Offload SORT offloaded to FPGA
22 Tool DEMO 22 Show how a basic application Receive values Sort them Return the values to the sender
23 Accelerator Offload 23 TCP Server Stream Block RAM Synthesizable Sort Function ARM Zynq - Fabric
24 Create Platform 24
25 Platform 25
26 Compile Platform 26
27 Import Platform 27
28 Import the first Block: TCP Server 28
29 Software import Wizard 29
30 Configure Call Parameters 30
31 Connect Blocks 31
32 VSI System Canvas 32 CPU Hardware
33 VSI System Canvas 33 CPU Hardware
34 Use trace to measure the performance 34 Trace enable
35 Sort Demo 35 EB1 ZX2 Linux PC x86 PL PS Bitstream AXI Linux Driver Software Executable Ethernet GUI
36 36 Mandelbrot Demo Linux PC x86 PE1 KX1 Bitstream FPGA Calculation PCIe PCIe Driver Software Executable Local Socket GUI CPU Calculation
37
38 Evaluate Visual System Integrator today! 90 days for free!
39 Everything FPGA.
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