Input & Output. Lecture 16. James Goodman (revised by Robert Sheehan) Computer Science 210 s1c Computer Systems 1 Lecture Notes

Transcription

1 Computer Science 210 s1c Computer Systems 1 Lecture Notes Lecture 16 Input & Output James Goodman (revised by Robert Sheehan) Credits: Slides prepared by Gregory T. Byrd, North Carolina State University 1

2 Synchronisation What happens if you try to print a file on a printer already in use? What happens if your programme tries to read a character before it s typed? What happens to a sequence of characters you ve type in before you read them? What happens if you send characters to a printer faster than it can accept them? 2

3 I/O Devices are Cantankerous Many I/O devices have a mechanical component They are very slow relative to electronic speeds They respond when they re ready, not necessarily when it s convenient They may not be willing to wait forever for their input (overrun) The CPU is the slave?: it must synchronize 3

4 Chapter 8 I/O

5 I/O: Connecting to the Outside World So far, we ve learned how to: compute with values in registers load data from memory to registers store data from registers to memory But where does data in memory come from? And how does data get out of the system so that humans can use it? 5

6 I/O: Connecting to the Outside World Types of I/O devices characterized by: behavior: input, output, storage input: keyboard, motion detector, network interface output: monitor, printer, network interface storage: disk, solid state data rate: how fast can data be transferred? Latency: how long to get the first byte Bandwidth: rate that data is received 6

7 I/O Device Examples Device Behavior Partner Data Rate (KB/sec) Keyboard Input Human 0.01 Mouse Input Human 0.02 Laser Printer Output Human 1,000 Graphics Display Output Human 30,000 Network-LAN Input or Output Machine ,000 Internet Input or Output Machine 1,o00-100,000 DVD-ROM (8x) Storage Machine 10,000 Magnetic Disk Storage Machine 100,000 Flash Memory Storage-read Machine 100,000-1,000,000 Storage-write Machine 50, ,000 7

8 I/O Controller Control/Status Registers CPU tells device what to do -- write to control register CPU checks whether task is done -- read status register Data Registers CPU transfers data to/from device CPU Control/Status Output Data Graphics Controller Electronics Device electronics performs actual operation pixels to screen, bits to/from disk, characters from keyboard display 8

9 Programming Interface How are device registers identified? Memory-mapped vs. special instructions How is timing of transfer managed? Asynchronous vs. synchronous Who controls transfer? CPU (polling) vs. device (interrupts) 9

10 Memory-Mapped vs. I/O Instructions Instructions designate opcode(s) for I/O register and operation encoded in instruction Memory-mapped assign a memory address to each device register use data movement instructions (LD/ST) for control and data transfer 10

11 Transfer Timing I/O events generally happen much slower than CPU cycles. Synchronous data supplied at a fixed, predictable rate CPU reads/writes every X cycles Asynchronous data rate less predictable CPU must synchronize with device, so that it doesn t miss data or write too quickly 11

12 Transfer Control Who determines when the next data transfer occurs? Polling CPU keeps checking status register until new data arrives OR device ready for next data Are we there yet? Are we there yet? Are we there yet? Interrupts Device sends a special signal to CPU when new data arrives OR device ready for next data CPU can be performing other tasks instead of polling device. Wake me when we get there. 12

13 LC-3 Memory-mapped I/O (Table A.3) Asynchronous devices synchronized through status registers Polling and Interrupts the details of interrupts will be discussed shortly 13

14 Input from Keyboard When a character is typed: its ASCII code is placed in bits [7:0] of KBDR (bits [15:8] are always zero) the ready bit (KBSR[15]) is set to one keyboard is disabled -- any typed characters will be ignored ready bit When KBDR is read: KBSR[15] is set to zero keyboard is enabled KBDR KBSR keyboard data 14

15 Basic Input Routine Polling NO new char? read character YES POLL LDI R0, KBSRP BRzp POLL LDI R0, KBDRP... KBSRP.FILL xfe00 KBDRP.FILL xfe02 Why LDI and not LD? 15

16 Simple Implementation: Memory- Mapped Input Address Control Logic determines whether MDR is loaded from Memory or from KBSR/KBDR. 16

17 Output to Monitor When Monitor is ready to display another character: the ready bit (DSR[15]) is set to one ready bit DDR DSR output data When data is written to Display Data Register: DSR[15] is set to zero character in DDR[7:0] is displayed any other character data written to DDR is ignored (while DSR[15] is zero) 17

18 Basic Output Routine Polling NO screen ready? write character YES POLL DSRP DDRP LDI R1, DSRP BRzp POLL STI R0, DDRP....FILL xfe04.fill xfe

19 Simple Implementation: Memory- Mapped Output Sets LD.DDR or selects DSR as input. 19

20 Keyboard Echo Routine Usually, input character is also printed to screen. User gets feedback on character typed and knows its ok to type the next character. POLL1 POLL2 LDI R0, KBSRP BRzp POLL1 LDI R0, KBDRP LDI R1, DSRP BRzp POLL2 STI R0, DDRP NO new char? YES read character KBSRP KBDRP DSRP DDRP....FILL xfe00.fill xfe02.fill xfe04.fill xfe06 NO screen ready? YES write character 20

21 Full Implementation of LC-3 Memory-Mapped I/O Because of interrupt enable bits, status registers (KBSR/DSR) must be written, as well as read. 21

22 Review Questions What is the danger of not testing the DSR before writing data to the screen? What is the danger of not testing the KBSR before reading data from the keyboard? What if the Monitor were a synchronous device, e.g., we know that it will be ready 1 microsecond after character is written. Can we avoid polling? How? What are advantages and disadvantages? 22

23 Review Questions Do you think polling is a good approach for other devices, such as a disk or a network interface? What is the advantage of using LDI/STI for accessing device registers? 23

24 Computer Science 210 s1c Computer Systems 1 Lecture Notes Lecture 17 Interrupts James Goodman (revised by Robert Sheehan) Credits: Slides prepared by Gregory T. Byrd, North Carolina State University 24

25 Interrupt-Driven I/O External device can: (1) Force currently executing program to stop; (2)Have the processor satisfy the device s needs; and (3)Resume the stopped program as if nothing happened. Why? Polling consumes a lot of cycles, especially for rare events these cycles can be used for more computation. Example: Process previous input while collecting current input. (See Example 8.1 pg 211 in text.) 25

26 Interrupt-Driven I/O To implement an interrupt mechanism, we need: A way for the I/O device to signal the CPU that an interesting event has occurred. A way for the CPU to test whether the interrupt signal is set and whether its priority is higher than the current program. Generating Signal Software sets interrupt enable bit in device register. When ready bit is set and IE bit is set, interrupt is signaled. interrupt enable bit ready bit KBSR interrupt signal to processor 26

27 Priority Every instruction executes at a stated level of urgency. LC-3: 8 priority levels (PL0-PL7) Example: Payroll program runs at PL0. Nuclear power correction program runs at PL6. It s OK for PL6 device to interrupt PL0 program, but not the other way around. Priority encoder selects highest-priority device, compares to current processor priority level, and generates interrupt signal if appropriate. 27

28 Testing for Interrupt Signal CPU looks at signal between STORE and FETCH phases. If not set, continues with next instruction. If set, transfers control to interrupt service routine (ISR). F NO D Transfer to ISR YES interrupt signal? EA OP EX S 28

29 Interrupt-Driven I/O Interrupts 1. External device signals a need to be serviced. 2. Processor saves state and starts service routine. 3. When finished, processor restores state and resumes program. Interrupt is an unscripted subroutine call, triggered by an external event. How does the CPU get the address of the correct interrupt service routine? How do (2) and (3) occur? 29

30 Location of the ISR (Interrupt Service Routine) Very similar to the TRAP mechanism. The interrupt provides two types of information the priority of the interrupt and a number identifying which interrupt. The interrupt provides a value from 00 to FF which identifies an interrupt vector in the range from x0100 to x01ff. The value stored at the interrupt vector is loaded into the PC and we have jumped to the interrupt handling routine. But before then 30

31 Processor State What state is needed to completely capture the state of a running process? Processor Status Register (PSR) Privilege [15], Priority Level [10:8], Condition Codes [2:0] Program Counter (PC) Pointer to next instruction to be executed. Registers All temporary state of the process that s not stored in memory. We know NZP are stored separately but the PSR includes them. 31

32 Where to Save Processor State? Can t use registers. Programmers doesn t know when interrupt might occur, so they can t prepare by saving critical registers. When resuming, need to restore state exactly as it was. Memory allocated by service routine? Must save state before invoking routine, so we wouldn t know where. Also, interrupts may be nested that is, an interrupt service routine might also get interrupted! Use a stack! Location of stack hard-wired. Push state to save, pop to restore. 32

33 Chapter 10 The Stack

34 Stack: An Abstract Data Type An important abstraction that you will encounter in many applications. We will describe four uses: Interrupt-Driven I/O The rest of the story Activation Records Calling conventions in C (more in the second half) Evaluating arithmetic expressions Store intermediate results on stack instead of in registers Data type conversion 2 s comp binary to ASCII strings 10-34

35 Stacks A LIFO (last-in first-out) storage structure. The first thing you put in is the last thing you take out. The last thing you put in is the first thing you take out. This means of access is what defines a stack, not the specific implementation. Two main operations: PUSH: add an item to the stack POP: remove an item from the stack 10-35

36 A Physical Stack Coin holder in the armrest of an automobile Initial State After One Push After Three More Pushes First coin out is the last quarter in. After One Pop 10-36

37 A Software Implementation Data items don't move in memory, just our idea about there the TOP of the stack is. Low memory (small address) High memory (large address) / / / / / / / / / / / / #12 TOP #12 / / / / / / / / / / / / #5 #5 / / / / / / / / / / / / #31 #31 TOP / / / / / / #18 TOP #18 #18 / / / / / / TOP / / / / / / / / / / / / / / / / / / x4000 R6 x3fff R6 x3ffc R6 x3ffe R6 Initial State After One Push After Three More Pushes By convention, R6 holds the Top of Stack (TOS) pointer. After Two Pops

38 Basic Push and Pop Code For our implementation, stack grows downward (when item added, TOS moves closer to 0) Push ADD R6, R6, #-1 ; decrement stack ptr STR R0, R6, #0 ; store data (R0) Pop LDR R0, R6, #0 ; load data from TOS ADD R6, R6, #1 ; decrement stack ptr 10-38

39 Pop with Underflow Detection If we try to pop too many items off the stack, an underflow condition occurs. Check for underflow by checking TOS before removing data. Return status code in R5 (0 for success, 1 for underflow) POP LD R1, EMPTY ; EMPTY = -x4000 ADD R2, R6, R1 ; Compare stack pointer BRz FAIL ; with x4000 LDR R0, R6, #0 ADD R6, R6, #1 AND R5, R5, #0 ; SUCCESS: R5 = 0 RET FAIL AND R5, R5, #0 ; FAIL: R5 = 1 ADD R5, R5, #1 RET EMPTY.FILL xc

40 Push with Overflow Detection If we try to push too many items onto the stack, an overflow condition occurs. Check for overflow by checking TOS before adding data. Return status code in R5 (0 for success, 1 for overflow) PUSH LD R1, MAX ; MAX = -x3ffb ADD R2, R6, R1 ; Compare stack pointer BRz FAIL ; with x3fff ADD R6, R6, #-1 STR R0, R6, #0 AND R5, R5, #0 ; SUCCESS: R5 = 0 RET FAIL AND R5, R5, #0 ; FAIL: R5 = 1 ADD R5, R5, #1 RET MAX.FILL xc

41 Supervisor Stack A special region of memory used as the stack for interrupt service routines. Want to use R6 as stack pointer. This means R6 is used for both the user and supervisor stacks. Plus two new registers for saving stack pointers Supervisor Stack Pointer (SSP) stored in Saved.SSP. Another register for storing User Stack Pointer (USP): Saved.USP. When switching from User mode to Supervisor mode (as result of interrupt), save R6 to Saved.USP. 41

42 Invoking the Service Routine The Details 1. If Privilege mode PSR[15] = 1 (user), Saved.USP = R6, then R6 = Saved.SSP. 2. Push PSR and PC to Supervisor Stack. 3. Set PSR[15] = 0 (supervisor mode). 4. Set PSR[10:8] = priority of interrupt being serviced. 5. Set PSR[2:0] = 0. Clear NZP bits (because they are meaningless, but will be restored later) this means none are set!!!! 6. Set MAR = x01vv, where vv = 8-bit interrupt vector provided by interrupting device (e.g., keyboard = x80). 7. Load memory location (M[x01vv]) into MDR. 8. Set PC = MDR; now first instruction of ISR will be fetched. See Fig. C.7 and C.8 in appendix C Note: This all happens between the STORE RESULT of the last user instruction and the FETCH of the first ISR instruction. 42

43 Returning from Interrupt Special instruction RTI that restores state. 1. Pop PC from supervisor stack. (PC = M[R6]; R6 = R6 + 1) 2. Pop PSR from supervisor stack. (PSR = M[R6]; R6 = R6 + 1). This means the NZP values are restored. 3. If PSR[15] = 1, R6 = Saved.USP. (If going back to user mode, need to restore User Stack Pointer.) RTI is a privileged instruction. Can only be executed in Supervisor Mode. If executed in User Mode, causes an exception. (an exception causes error code to run just like calling an interrupt, in fact exceptions can be thought of as synchronous interrupts) 43

44 Example (1) Saved.SSP / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / x3006 Program A ADD PC x3006 Executing ADD at location x3006 when Device B interrupts. 44

45 Example (2) / / / / / / Program A x6200 ISR for Device B R6 / / / / / / x3007 PSR for A / / / / / / x3006 ADD x6210 RTI PC x6200 Saved.USP = R6. R6 = Saved.SSP. Push PSR and PC onto stack, then transfer to Device B service routine (at x6200; better if it was below x3000). 45

46 Example (3) R6 / / / / / / / / / / / / x3007 PSR for A / / / / / / x3006 Program A ADD x6200 x6202 ISR for Device B AND x6210 RTI PC x6203 Executing AND at x6202 when Device C interrupts. 46

47 Example (4) R6 x6203 PSR for B x3007 PSR for A / / / / / / x3006 Program A ADD x6200 x6202 ISR for Device B AND x6210 RTI x6300 ISR for Device C PC x6300 x6315 RTI Push PSR and PC onto stack, then transfer to Device C service routine (at x6300). 47

48 Example (5) R6 x6203 PSR for B x3007 PSR for A / / / / / / x3006 Program A ADD x6200 x6202 ISR for Device B AND x6210 RTI x6300 ISR for Device C PC x6203 x6315 RTI Execute RTI at x6315; pop PC and PSR from stack. 48

49 Example (6) Saved.SSP x6203 PSR for B x3007 PSR for A / / / / / / x3006 Program A ADD x6200 x6202 ISR for Device B AND x6210 RTI x6300 ISR for Device C PC x3007 x6315 RTI Execute RTI at x6210; pop PSR and PC from stack. Restore R6. Continue Program A as if nothing happened. 49

50 Exception: Internal Interrupt When something unexpected happens inside the processor, it may cause an exception. Examples: Privileged operation (e.g., RTI in user mode) Executing an illegal opcode Divide by zero (not on the LC-3 ) Accessing an illegal address (e.g., protected system memory, not on the LC-3 either) Handled just like an interrupt Vector is determined internally by type of exception Priority remains the same as running program 50

51 Can we build a robust OS on the LC-3? We have seen that the LC-3 has two privilege modes (user and supervisor). This is required to provide a robust operating system. Unfortunately because there are no areas of memory which are only addressable when in supervisor mode we can t guarantee that an ordinary user level program does not mess with memory and corrupt the operating system code. The Java version of the simulator does appear to have MPR memory protection register and provides extra instructions. More on this in the COMPSCI 340 course. 51

52 Preview of C: Stack Frames Major support issues posed by subroutines Linkage (how to get there and back) Passing parameters (where are they) Providing storage for local use (finding unique space for each invocation) An activation record is a memory template of fixed size, allocated atomically as part of invoking a subroutine It allocates space to save parameters It provides storage for variables defined in the subroutine It provides a place for saving the return path. A stack of activation records is an efficient way to address all three issues 52

53 First in Python Simple Recursion # recursion demo for 210 def countdown(ch): print(ch) if ch > "a": countdown(chr(ord(ch) - 1)) countdown("a") countdown("b") countdown("z") 53

54 Then in LC-3 assembly - 1 ; recursive count down ; For the entire program: ; r7 is used for return addresses ; r6 is used as the stack pointer (sp).orig 0x3000 lea r6,tos ; set up the stack ld r0,char_a jsr count ; count( a ) ld r0,char_a add r0,r0,#1 jsr count ; count( b ) ld r0,char_z jsr count ; count( z ) halt 54

55 Then in LC-3 assembly 2 (setup and pulldown) ; r0 is used for the char parameter ; Callee saves all other used registers (good form) count add r6,r6,#-1 str r7,r6,#0 ; return address onto stack add r6,r6,#-1 str r1,r6,#0 ; save r1 on the stack add r6,r6,#-1 str r0,r6,#0 ; save char on the stack (code for function goes here) finished add r6,r6,#1 ; why? ldr r1,r6,#0 ; restore r1 add r6,r6,#1 ldr r7,r6,#0 ; r7 = return address add r6,r6,#1 ret 55

56 Then in LC-3 assembly 3 (function body) putc ; print(ch) ld r0,newline putc ldr r0,r6,#0 ; r0 = char ld r1,char_a not r1,r1 add r1,r1,#1 add r1,r1,r0 ; r1 = char - "a" brnz finished add r0,r0,#-1 ; r0 = char - 1 jsr count ; recursive call 56

57 Then in LC-3 assembly 4 (data incl. the stack) char_a.fill 97 char_z.fill 123 newline.fill 10 bos.blkw 100 ; what can go wrong here? tos.fill 0.end 57

58 Full LC-3 Data Path 58