Chapter 8 Input/Output

Transcription

1 Lecture on Introduction to Computing Systems Chapter 8 Input/Output An Hong han@ustc.edu.cn 0 Fall School of Computer Science and Technology 0/11/3 1

2 Review So far, we ve learned how to: compute with values in registers load data from memory to registers store data from registers to memory MEMORY MAR MDR INPUT Keyboard Mouse Scanner Disk PROCESSING UNIT ALU TEMP OUTPUT Monitor Printer LED Disk CONTROL UNIT PC IR 0/11/3

3 Review: LC-3 Data Path GateMAR MAR GatePC LD.PC PC PC +1 DR LD.REG 3 REG FILE LD.IR IR [7:0] Control Unit ADDR [10:0] [8:0] [5:0] [4:0] + N Z P LOGIC LD.CC ADDR1 FINITE STATE MACHINE SR SR1 Processing SR SR1 3 OUT OUT 3 ALUK Unit SR A ALU B RUN GateALU GateMDR LD.MDR Memory MDR Unit MEMORY MAR MEM.EN,R,W LD.MAR INPUT OUTPUT 3

4 Need for I/O But where does data in memory come from? And how does data get out of the system so that humans can use it? Computer systems are useless unless they can process information from outside of the computer and output results outside of the computer I/O is effectively the communication with outside of the computer I/O device itself communicates with outside world E.g., keyboard takes input from user Computer needs to communicate with I/O device E.g., computer takes input from keyboard Communication through shared memory locations Processor and I/O can read/write those memory locations Sometimes, data in memory locations can be set/cleared automatically (by hardware) depending on a read/write 0/11/3 4

5 I/O: Connecting to the Outside World Examples Keyboard/mouse input, video output on a standard computer Network input/output that enables web surfing Information from an engine of a car that a computer uses to determine how to tune the engine (output from computer tunes the engine) Requests for airline reservations and replies that service those requests Types of I/O devices characterized by: behavior: input, output, storage - input: keyboard, motion detector, network interface - output: display screen(monitor), printer, network interface - storage: disk, CD-ROM data rate: how fast can data be transferred? - keyboard: 100 bytes/sec - disk: 30 MB/s - network: 1 Mb/s - 1 Gb/s 0/11/3 5

6 I/O Controller Control/Status Registers CPU tells device what to do -- write to control register CPU checks whether task is done -- read status register Data Registers CPU transfers data to/from device Control/Status Graphics Controller CPU Output Data Electronics display Device electronics performs actual operation - pixels to screen, bits to/from disk, characters from keyboard 0/11/3 6

7 Programming Interface How are device registers identified? Memory-mapped vs. special instructions How is timing of transfer managed? Asynchronous vs. synchronous Who controls transfer? CPU (polling) vs. device (interrupts) 0/11/3 7

8 Memory-Mapped vs. I/O Instructions Instructions designate opcode(s) for I/O register and operation encoded in instruction Memory-mapped assign a memory address to each device register use data movement instructions (LD/ST) for control and data transfer 0x FE00 0/11/3 8

9 Transfer Timing I/O events generally happen much slower than CPU cycles. If : CPU 300MHz, 10clocks/character,6characters/word Then: typing speed (1/(300x10 6 ))x10x6=5x10 6 words/s Synchronous data supplied at a fixed, predictable rate CPU reads/writes every X cycles Asynchronous data rate less predictable CPU must synchronize with device, so that it doesn t miss data or write too quickly 0/11/3 9

10 Transfer Control Who determines when the next data transfer occurs? CPU vs. I/O device Polling is explicitly looking/examining CPU keeps checking status register until new data arrives OR device ready for next data Are you there yet? Are you there yet? Are you there yet? Interrupts is a nudge, knock on the door, loud noise, which forces you to pay attention Device sends a special signal to CPU when new data arrives OR device ready for next data CPU can be performing other tasks instead of polling device. Wake me when you get there. 0/11/3 10

11 LC-3 Memory-mapped I/O (Table A.1) Location I/O Register Function xfe00 xfe0 xfe04 xfe06 Keyboard Status Reg (KBSR) Keyboard Data Reg (KBDR) Display Status Register (DSR) Display Data Register (DDR) Bit [15] is one when keyboard has received a new character. Bits [7:0] contain the last character typed on keyboard. Bit [15] is one when device ready to display another char on screen. Character written to bits [7:0] will be displayed on screen. Asynchronous devices synchronized through status registers Polling and Interrupts the details of interrupts will be discussed in Chapter 10 0/11/3 11

12 Memory map of the LC-3 0x0000 0x00FF 0x0100 0x01FF 0x000 0xFFF 0x3000 Trap Vector Table Interrupt Vector Table Operating System and Supervisor Stack Program Text PC Global data section Heap (for dynamically allocated memory) R4(Global pointer) Function1 Function R6 R5 R6 R5 0xFDFF 0xFE00 0xFFFF Run-time stack Device Register Addresses R6 (stack pointer) R5 (frame pointer) Function3 0/11/3 1 R6 R5

13 Example: Processor Input from Keyboard When a character is typed: its ASCII code is placed in bits [7:0] of KBDR (bits [15:8] are always zero) the ready bit (KBSR[15]) is set to one keyboard is disabled -- any typed characters will be ignored ready bit KBDR KBSR keyboard data When KBDR is read: KBSR[15] is set to zero, meaning no keyboard key is pending keyboard is enabled 0/11/3 13

14 Memory-mapped Operations How do we read ready bit? How do we test whether the bit is one? How do we read keyboard data? 0/11/3 14

15 Basic Input Routine Polling NO new char? YES read character POLL KBSR KBDR LDI R0, KBSR BRzp POLL LDI R0, KBDR....FILL xfe00.fill xfe0 0/11/3 15

16 IN Memory-mapped I/O GateMDR MAR LD.MAR MDR LD.MDR MEM.R,W INPUT OUTPUT MEMORY ADDR.CTL LOGIC KBDR KBSR LD.DDR DDR DSR MEM.EN, READ/WRITE 0/11/3

17 LDI (Indirect) F D EA OP EX S GateMAR MAR GatePC LD.PC PC PC +1 DR LD.REG 3 REG FILE [7:0] + SR 3 SR SR1 OUT OUT 3 SR1 ADDR ADDR1 LD.IR [10:0] [8:0] [5:0] [4:0] IR LD.CC N Z P LOGIC FINITE STATE MACHINE SR ALUK A ALU B RUN GateALU GateMDR LD.MDR MDR MAR LD.MAR MEMORY INPUT OUTPUT MEM.EN,R,W 17

18 LDI (Indirect) F D EA OP EX S GateMAR MAR GatePC LD.PC PC PC +1 DR LD.REG 3 REG FILE [7:0] + SR 3 SR SR1 OUT OUT 3 SR1 ADDR ADDR1 LD.IR [10:0] [8:0] [5:0] [4:0] IR LD.CC N Z P LOGIC FINITE STATE MACHINE SR ALUK A ALU B RUN GateALU GateMDR LD.MDR MDR MAR LD.MAR MEMORY INPUT OUTPUT MEM.EN,R,W 18

19 RUN LD.CC MEM.EN,R,W MAR LD.MAR PC GatePC 19 ALU A B SR INPUT OUTPUT MEMORY FINITE STATE MACHINE N Z P LOGIC + DR LD.REG SR SR1 ALUK REG FILE SR1 OUT SR OUT GateALU ADDR PC +1 MAR [10:0] [8:0] [5:0] [4:0] [7:0] GateMAR LD.PC ADDR LD.IR IR MDR LD.MDR GateMDR LDI (Indirect) EA OP EX S F D

20 LDI (Indirect) F D EA OP EX S GateMAR MAR GatePC LD.PC PC PC +1 DR LD.REG 3 REG FILE [7:0] + SR 3 SR SR1 OUT OUT 3 SR1 ADDR ADDR1 LD.IR [10:0] [8:0] [5:0] [4:0] IR LD.CC N Z P LOGIC FINITE STATE MACHINE SR ALUK A ALU B RUN GateALU GateMDR LD.MDR MDR MAR LD.MAR MEMORY INPUT OUTPUT MEM.EN,R,W 0

21 LDI (Indirect) F D EA OP EX S GateMAR MAR GatePC LD.PC PC PC +1 DR LD.REG 3 REG FILE [7:0] + SR 3 SR SR1 OUT OUT 3 SR1 ADDR ADDR1 LD.IR [10:0] [8:0] [5:0] [4:0] IR LD.CC N Z P LOGIC FINITE STATE MACHINE SR ALUK A ALU B RUN GateALU GateMDR LD.MDR MDR MAR LD.MAR MEMORY INPUT OUTPUT MEM.EN,R,W 1

22 LDI (Indirect) F D EA OP EX S GateMAR MAR GatePC LD.PC PC PC +1 DR LD.REG 3 REG FILE [7:0] + SR 3 SR SR1 OUT OUT 3 SR1 ADDR ADDR1 LD.IR [10:0] [8:0] [5:0] [4:0] IR LD.CC N Z P LOGIC FINITE STATE MACHINE SR ALUK A ALU B RUN GateALU GateMDR LD.MDR MDR MAR LD.MAR MEMORY INPUT OUTPUT MEM.EN,R,W

23 IN Memory-mapped I/O: LDI R0, KBSR GateMDR MAR LD.MAR MDR LD.MDR MEM.R,W INPUT OUTPUT MEMORY ADDR.CTL LOGIC KBDR KBSR LD.DDR DDR DSR MEM.EN, READ/WRITE 0/11/3 3

24 IN Memory-mapped I/O: LDI R0, KBDR GateMDR MAR LD.MAR MDR LD.MDR MEM.R,W INPUT OUTPUT MEMORY ADDR.CTL LOGIC KBDR KBSR LD.DDR DDR DSR MEM.EN, READ/WRITE 0/11/3 4

25 LD.IR MEM.EN,R,W MAR LD.MAR MEMORY 3 SR1 SR 3 SR [10:0] [8:0] [5:0] [4:0] INPUT PC GatePC 5 OUTPUT + ADDR1 PC +1 MAR [7:0] GateMAR LD.PC ADDR LD.MDR ALU A B ALUK GateALU DR LD.REG REG FILE SR1 OUT SR OUT 3 FINITE STATE MACHINE N Z P RUN LOGIC LD.CC IR MDR GateMDR LDI (Indirect) EA OP S D F EX

26 Example: Processor Output to Screen When Display device is ready to display another character: the ready bit (DSR[15]) is set to one, indicating that processor can write a character for display ready bit DDR DSR output data When data is written to the Display data register: DSR[15] automatically set to 0 character in DDR[7:0] is displayed any other character data written to DDR is ignored (while DSR[15] is zero) 0/11/3 6

27 Basic Output Routine Polling NO screen ready? YES write character POLL DSR DDR LDI R1, DSR BRzp POLL STI R0, DDR....FILL xfe04.fill xfe06 0/11/3 7

28 STI (Indirect) F D EA OP EX S GateMAR MAR GatePC LD.PC PC PC +1 DR LD.REG 3 REG FILE [7:0] + SR 3 SR SR1 OUT OUT 3 SR1 ADDR ADDR1 LD.IR [10:0] [8:0] [5:0] [4:0] IR LD.CC N Z P LOGIC FINITE STATE MACHINE SR ALUK A ALU B RUN GateALU GateMDR LD.MDR MDR MAR LD.MAR MEMORY INPUT OUTPUT MEM.EN,R,W 8

29 STI (Indirect) F D EA OP EX S GateMAR MAR GatePC LD.PC PC PC +1 DR LD.REG 3 REG FILE [7:0] + SR 3 SR SR1 OUT OUT 3 SR1 ADDR ADDR1 LD.IR [10:0] [8:0] [5:0] [4:0] IR LD.CC N Z P LOGIC FINITE STATE MACHINE SR ALUK A ALU B RUN GateALU GateMDR LD.MDR MDR MAR LD.MAR MEMORY INPUT OUTPUT MEM.EN,R,W 9

30 RUN LD.CC MEM.EN,R,W MAR LD.MAR PC GatePC 30 ALU A B SR INPUT OUTPUT MEMORY FINITE STATE MACHINE N Z P LOGIC + DR LD.REG SR SR1 ALUK REG FILE SR1 OUT SR OUT GateALU ADDR PC +1 MAR [10:0] [8:0] [5:0] [4:0] [7:0] GateMAR LD.PC ADDR LD.IR IR MDR LD.MDR GateMDR STI (Indirect) EA OP EX S F D

31 STI (Indirect) F D EA OP EX S GateMAR MAR GatePC LD.PC PC PC +1 DR LD.REG 3 REG FILE [7:0] + SR 3 SR SR1 OUT OUT 3 SR1 ADDR ADDR1 LD.IR [10:0] [8:0] [5:0] [4:0] IR LD.CC N Z P LOGIC FINITE STATE MACHINE SR ALUK A ALU B RUN GateALU GateMDR LD.MDR MDR MAR LD.MAR MEMORY INPUT OUTPUT MEM.EN,R,W 31

32 STI (Indirect) F D EA OP EX S GateMAR MAR GatePC LD.PC PC PC +1 DR LD.REG 3 REG FILE [7:0] + SR 3 SR SR1 OUT OUT 3 SR1 ADDR ADDR1 LD.IR [10:0] [8:0] [5:0] [4:0] IR LD.CC N Z P LOGIC FINITE STATE MACHINE SR ALUK A ALU B RUN GateALU GateMDR LD.MDR MDR MAR LD.MAR MEMORY INPUT OUTPUT MEM.EN,R,W 3

33 STI (Indirect) F D EA OP EX S GateMAR MAR GatePC LD.PC PC PC +1 DR LD.REG 3 REG FILE [7:0] + SR 3 SR SR1 OUT OUT 3 SR1 ADDR ADDR1 LD.IR [10:0] [8:0] [5:0] [4:0] IR LD.CC N Z P LOGIC FINITE STATE MACHINE SR ALUK A ALU B RUN GateALU GateMDR LD.MDR MDR MAR LD.MAR MEMORY INPUT OUTPUT MEM.EN,R,W 33

34 STI (Indirect) F D EA OP EX OP GateMAR MAR GatePC LD.PC PC PC +1 LD.REG DR 3 REG FILE [7:0] + SR 3 SR SR1 OUT OUT 3 SR1 ADDR ADDR1 LD.IR [10:0] [8:0] [5:0] [4:0] IR LD.CC N Z P LOGIC FINITE STATE MACHINE SR ALUK A ALU B RUN GateALU GateMDR LD.MDR MDR MAR LD.MAR MEMORY INPUT OUTPUT MEM.EN,R,W 34

35 IN Memory-mapped I/O: STI R0, DDR? GateMDR MAR LD.MAR MDR LD.MDR MEM.R,W INPUT OUTPUT MEMORY ADDR.CTL LOGIC KBDR KBSR LD.DDR DDR DSR MEM.EN, READ/WRITE 0/11/3 35

36 Keyboard Echo Routine Usually, input character is also printed to screen. User gets feedback on character typed and knows its ok to type the next character. POLL1 POLL LDI R0, KBSR BRzp POLL1 LDI R0, KBDR LDI R1, DSR BRzp POLL STI R0, DDR NO new char? YES read character KBSR KBDR DSR DDR....FILL xfe00.fill xfe0.fill xfe04.fill xfe06 NO screen ready? YES write character 0/11/3 36

37 Interrupt-Driven I/O To implement an interrupt mechanism, we need: A way for the I/O device to signal the CPU that an interesting event has occurred. A way for the CPU to test whether the interrupt signal is set. Generating Signal Software sets "interrupt enable(ie)" bit in device register. When ready bit is set and IE bit is set, interrupt is signaled. interrupt enable bit ready bit KBSR interrupt signal to processor 0/11/3 37

38 Interrupt-Driven I/O Testing for Interrupt Signal CPU looks at signal between STORE and FETCH phases If not set, continues with next instruction If set, transfers control to Interrupt Service Routine(ISR) F NO D Transfer to ISR YES interrupt signal? EA OP EX More details in Chapter 10. S 0/11/3 38

39 Review Questions What is the danger of not testing the DSR before writing data to the Display screen? What is the danger of not testing the KBSR before reading data from the keyboard? What if the Display were a synchronous device, e.g., we know that it will be ready 1 microsecond after character is written. Can we avoid polling? How? What are advantages and disadvantages? 0/11/3 39

40 Review Questions Do you think polling is a good approach for other devices, such as a disk or a network interface? What is advantage of using LDI/STI for accessing device registers? 0/11/3 40