Input/Output Interfaces: Ch

Transcription

1 Input/Output Interfaces: Ch hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 1

2 Recall von Neumann model MEMORY MAR MDR INPUT Keyboard Mouse Scanner Disk PROCESSING UNIT ALU TEMP OUTPUT Monitor Printer LED Disk CONTROL UNIT PC IR 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 2

3 Instruction Sets and von Neumann model Processing unit Computation Instructions Memory unit Accessed in Instruction fetch And load/store instructions Control unit Controls phases of instruction cycle (fetch, decode.. etc) Control transfer instructions How does program interact with input/output (I/O) components? 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 3

4 Special Characteristics of I/O I/O devices allow data to be input/output between computer and outside world Like memory, we need to read from and write to I/O devices For memory, we provide address and read or write Similarly for I/O, we need to identify which device and what operation There is only one memory, so there is no need to specify which memory (but only which address) But there are many I/O devices so we need to say which device To make it manageable, there is a uniform interface for all I/O devices: each I/O device is identified by a bunch of device registers 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 4

5 I/O Device Registers Each I/O device has some number of device registers Control register: for CPU to specify what operation to do Read or write or some other (for certain I/O devices) For disk (permanent memory with storage of large amounts of data), we specify address but keyboard handles only one character at a time so no address Data register: for holding data to/from CPU Status register: for showing status of the I/O device Is the device still busy with the previous operation? Is there some input for CPU? Is it safe for CPU to send the next output data or is the previous output data not done yet? 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 5

6 I/O Device Registers Control and Data registers are analogous to memory where we specified read or write and the data to be transferred But what is this status business? We did not have this for memory I/O devices are millions of times slower than CPU And the I/O device speed varies (keyboard typing) So it is best to have I/O device go on its own speed and not be lock-stepped with the CPU clock Lock-stepping with CPU clock would mean waiting for millions of cycles which is silly, cumbersome, and wasteful (to use extra hardware to wait for millions of cycles ) 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 6

7 I/O Device Registers So we use asynchronous interaction between CPU and I/O Using CPU clock would be synchronous Asynchronous means CPU and I/O work independently When data needs to be sent between CPU and I/O they do handshaking (aka protocol) Needed because not lock-stepped with CPU Handshaking works by I/O device making its status known to the CPU (status as in I have a new input for CPU, or I am done with outputting previous data, etc) This status is shown in the status register (1-bit keyboard status to show if there is a new character and 1-bit monitor status to show if monitor is done displaying last character) 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 7

8 I/O Device registers Example: LC3 keyboard (input) and monitor (output) KBSR keyboard status register: is there a key ready? KBDR keyboard data register: what is the key value? CRTSR CRT status register: ready to accept output CRTDR CRT data register: write data here for display Device registers are different from General Purpose Registers Not in processing unit Not used for ordinary instructions So, how do we get access to these device registers? 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 8

9 When should we access device? Synchronous Device always becomes ready after a fixed number of processor clock cycles; processor should read/write periodically Asynchronous No guarantees of device timing Instead, device has status registers to indicate readiness Requires processor to do some synchronization task to determine when device is ready Asynchronous is far more common 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 9

10 Accessing Device Registers Option 1: Special instructions I/O opcode; operands include device number and some command I / O 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 10

11 Accessing Device Registers Option 2: Memory-mapped I/O Device registers accessed through regular load and store operations to some specific memory addresses These addresses are set aside and are not part of memory In LC3, xfe00 to xffff are for I/O device registers For read/write to these addresses, memory does not do anything and the specific I/O device register is read/written Memory-mapped I/O far more common 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 11

12 Memory Mapped I/O in LC3 (Page 543) Location xfe04 xfe06 xfe00 xfe02 I/O Register Display Status Register (DSR) Display Data Register (DDR) Keyboard Status Reg (KBSR) Keyboard Data Reg (KBDR) Function Bit [15] is one when device ready to display another char on screen. ASCII character written to bits [7:0] will be displayed on screen. Bit [15] is one when keyboard has received a new character Vijaykumar ECE495K Lecture Notes: Chapter 8 12

13 Example: Input from Keyboard When user types a character: Keyboard places ASCII code in KBDR[7:0] (high bits 0) Keyboard sets KBSR[15] to 1 (no guarantee on other bits) How to test if highest bit is 1? KBSR[15] being 1 disables keyboard for a very short time where further key strokes are highly unlikely but if they occur are ignored keyboard data KBDR ready bit KBSR When program loads KBDR: Program sets KBSR[15] to 0 which automatically re-enables Keyboard 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 13

14 How do we synchronize with device? Polling Keep checking status register until new data available or device ready to accept new data Are we there yet? Are we there yet? Are we there yet? Bart Simpson Interrupts Device sends a special signal called interrupt to CPU which drops what it is doing, handles the interrupt, goes back to what it was doing Wake me when we get there. Sleep-loving teenager interrupt disrupts ordinary flow of instruction cycle 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 14

15 How do we synchronize with device? Polling Because most I/O devices are much slower than CPU, polling checks result in not ready yet CPU wastes many clock cycles checking unnecessarily when it could be doing other useful work Interrupts CPU pays attention to I/O device only when there is something so no wastage of CPU But interrupts are not free they do incur some overhead but much less than polling especially for slow I/O devices Interrupts occur any time in the middle of an instruction, CPU hardware to handle interrupts is complex (ECE437) 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 15

16 Example: Basic Polling Terminal Program INPOLL LDI R0, KBSRlabel BRzp INPOLL LDI R0, KBDRlabel OUTPOLL LDI R1, DSRlabel BRzp OUTPOLL STI R0, DDRlabel... KBSRlabel.FILL xfe00 KBDRlabel.FILL xfe02 DSRlabel.FILL xfe04 DDRlabel.FILL xfe06 Why LDI/STI? Why BRzp? What does this program do? What could happen if we read KBDR without checking KBSR? What could happen if we write DDR without checking DSR? Recall Ch.6 character count eg where input came from keyboard 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 16

17 More on Interrupt-driven I/O Two parts: Generate the interrupt signal In hardware A little bit of details now Perform service for the interrupt In software Details in later courses In 495k, we cover and a little bit of 8.5 Read pages (pages will be covered later) 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 17

18 Generating Interrupt signal Program running on CPU may be doing higher priority work and not want to be interrupted So each I/O device has a interrupt enable (IE) bit in device status register program clears this bit if it wants I/O device to shut up If IE is clear device ready bit does not matter When ready bit and IE bit set, device interrupts CPU interrupt enable bit ready bit KBSR interrupt signal to processor 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 18

19 Generating Interrupt signal I/O devices and their interrupts are prioritized by their urgency Internet Explorer vs. missile control Details can be complex ( we won't go into page 213) CPU must test whether interrupt signal has been set, and respond accordingly Modify instruction cycle 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 19

20 Interrupt-Aware Instruction Cycle 1. Fetch instruction from memory 2. Decode instruction 3. Evaluate memory address if needed 4. Fetch operands for computation 5. Execute instruction using operands 6. Store result into specified destination 7. Check if interrupt signal set If not, go to step #1 for next PC If so, save aside PC and CCRs; transfer to interrupt service routine. More detail in Chapter Vijaykumar ECE495K Lecture Notes: Chapter 8 20

21 How is data transferred? For small data, load/store from CPU, for large data 2 options Programmed I/O (PIO) Computer uses load/store instructions to transfer data between memory-mapped device data registers and memory via GPRs Wastes CPU to do lowly work of transferring data Direct Memory Access (DMA) Device directly transfers data from/to specified regions in memory without CPU intervention, so saves CPU time adds complexity to memory system design Typically used for bulk data transfers from devices like disks, network interfaces, etc Vijaykumar ECE495K Lecture Notes: Chapter 8 21

22 Where are we headed? Ch hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 2009 Vijaykumar ECE495K Lecture Notes: Chapter 8 22