Converting.srec Files to.flash Files for Nios Embedded Processor Applications
|
|
- Ashlie Harmon
- 5 years ago
- Views:
Transcription
1 White Paper Converting.srec Files to.flash Files for Nios Embedded Processor Applications Introduction The Excalibur Development Kit, featuring the Nios embedded processor, includes the software, hardware, accessories, and documentation necessary to create embedded processor designs and complete system projects. In a typical development flow, the designer creates an embedded software application and then uses the nios-build utility to create a Motorola s-record (.srec) file format of the application. Next, the designer downloads the.srec file to the Nios development board using the GERMS monitor. The application code usually runs from the on-board SRAM. When developing applications, the designer may want to store the embedded software application and the PLD image in the flash memory in the Nios development board. In this case, the PLD image and the embedded application load each time the power is cycled or the system is reset. You can convert the.srec file into a flash boot image (.flash) file, which can be downloaded into the flash memory on the Nios development board. The.flash file includes the GERMS monitor commands to erase the flash memory and relocate s-records to the erased location. This file also contains initialization code that copies your embedded application code from the flash to the SRAM. When copying is complete, the embedded application executes. If your design has the same memory map as the Nios 32-bit reference design provided in the Excalibur Development Kit, featuring the Nios embedded processor, you can create.flash files by using the Altera-provided srec2flash utility. For applications that are not designed for the Nios development board or for systems that have a custom memory map, you can create the.flash file using the procedure described in Creating.flash Files for Custom memory Maps on page 5. This white paper describes the srec2flash utility, how to create.flash files from.srec files, and how to create a.flash file using a custom memory map. Before You Begin The instructions in this document assume that you are familiar with: Designing Nios-based systems Compiling embedded software applications for Nios-based systems Using the GERMS monitor 1 To use the srec2flash utility or to use a custom.flash file, your Nios system design must include the GERMS monitor. f Refer to the Nios documentationfor more information about the hardware and software elements of the Excalibur Development Kit, featuring the Nios embedded processor. The documentation is installed into the \Altera\Excalibur\nios_documentation directory. A-WP-NIOSFLASH-1.0 OCtober 2001, ver
2 The srec2flash Utility The srec2flash utility converts.srec files to.flash files. This section describes the utility. When to Use the srec2flash Utility Use srec2flash if you want to: Store your application code in the flash memory on the Nios development board so that the application executes when the board is powered up or after a hardware or software reset. Execute the application code from the SRAM not from the flash. Use the same memory map as the defined by the 32-bit reference design included with the kit. How the srec2flash Utility Works The srec2flash utility adds the GERMS monitor commands and initialization code in s-record format (see Figure 1) to the beginning of the specified.srec file, <my program>.srec. In Figure 1, comment lines begin with a character. Figure 1. GERMS Monitor Commands in the srec2flash Utility Reset the relocation offset to 0 r0 Erase flash sector This address is checked by the GERMS monitor at startup e S DC07F00304E696F E1165 S F524A005A E E27EF F9 S A CC07F00302E Main program Ser the relocation offset for ro (flash) r End of GERMS monitor commands Begin user.srec file Table 1 describes the functionality of the code. Table 1. srec2flash GERMS Monitor Commands r0 e Command Code Description This command resets the relocation offset to zero. The GERMS monitor treats all addresses as absolute addresses. This command directs the GERMS monitor to erase the block of flash starting at address 0x Each block in the code section of the flash is 64 KBytes. If your program is larger than 64 KBytes, you must erase more than one block of flash. S2xxx The 3 lines beginning with S2 are the s-records that copy the application code from the flash to the SRAM. Altera created these s-records by compiling the file flashcopy.s (see Generating S-Records for Use with the srec2flash Utility on page 3). r This command instructs the GERMS monitor to relocate any s-records that follow this command by an offset of 0x (from to ). During normal compilation of Nios embedded applications, the nios-build utility maps the resultant binary code into SRAM memory space with the first instruction of the application above the interrupt vector table. The default address for this action is 0x The relocate command adjusts the s-record addresses such that the GERMS monitor stores the data in flash starting at address 0x
3 The command syntax for the srec2flash utility is: srec2flash <my program>.srec The utility outputs the file <my program>.flash, which you can download into the Nios development board using the command: nios-run <my program>.flash Generating S-Records for Use with the srec2flash Utility The s-records in the srec2flash utility copy the application from the flash to the SRAM and start execution of the application from the SRAM. The s-records included with the srec2flash utility were generated by compiling an assembly language program named flash_copy.s (see Figure 2). The flash_copy.s program uses the registers %l0, %l1, %l2, and %g0: %l0 Source memory start address. %l1 Source memory end address. %l2 Destination memory start address. %g0 Temporary register for holding the memory contents you want to copy. 1 In the following code, comment lines begin with the ; character. Figure 2. flash_copy.s Assembly Language Program ; file: flash_copy.s.include "nios.s".global _start _start: MOVIP %l0,0x ; flash (source) starting adddress MOVIP %l1,0x ; flash (source) ending address MOVIP %l2,na_ext_ram ; SRAM (destination) address start ; location, which is defined in ; nios_macros.s flash_copier_loop: LD %g0,[%l0] ; get current word ADDI %l0,4 ; bump source to next word ST [%l2],%g0 ; store word ADDI %l2,4 ; bump destination to next word CMP %l0,%l1 ; are we there yet? IFS cc_ne BR flash_copier_loop NOP ; Jump to the program stored at nasys_program_mem, which is defined in nios_map.s. The divides by 2 so that the address is a valid one for a subroutine. MOVIA %g0,nasys_program_mem@h JMP %g0 NOP ; End of file 3
4 The flash_copier_loop routine copies a block of memory from flash into SRAM. The flash block that is copied has starting and ending addresses stored in registers %10 and %11, respectively. This block is copied to SRAM starting at the address stored in %12. The program then jumps to the starting program memory address stored in the variable nasys_program_mem. The variable is offset from the beginning of the SRAM by the size of the interrupt vector table 0x100 bytes for the 32-bit reference design. Compiling the flash_copy.s program using the nios-build utility generates the s-records. The command to compile is: nios-build b 0x flash_copy.s This command generated the file flash_copy.srec, which contains the lines: S C F636F E S DC07F00304E696F E1165 S F524A005A E E27EF F9 S A CC07F00302E S D7 The srec2flash utility only uses the middle three s-record lines. The first line, which starts with S0, is optional. It contains no executable code; therefore, it was not included. The next 3 lines, which start with S2, are the SREC format of the actual executable code. These lines are 24-bit address records with 0x19, 0x19, and 0x10 bytes of information, respectively, with the first line starting at address 0x The last line, which starts with S8, contains the s-record with the executable address for this program. Because the srec2flash utility is designed to execute the designer s application after copying to the SRAM, this line is not included. On power-up, the GERMS monitor checks address xC for the characters Nios. If these characters are found, the application jumps to and begins execution. The GERMS monitor also checks the state of SW4 on the development board. If you press the button during this startup period, the GERMS monitor does not jump to 0x14010C; instead, it terminates to a command prompt. f Refer to S-Record File Format on page 6 for additional information on the s-record format. 4
5 Creating.flash Files for Custom memory Maps If your Nios design does not use the memory map of the 32-bit reference design, you should not use the srec2flash utility to convert your.srec file to a.flash file. Instead, follow the instructions in this section to create the.flash file. 1 Read How the srec2flash Utility Works on page 2 and Generating S-Records for Use with the srec2flash Utility on page 3 to become familiar with the basic concepts before creating your own.flash file. To create a.flash file, perform the following steps: 1. Compile the embedded application source code, <my program>.c using the normal Nios build process to output the file <my program>.srec. Note the start and end addresses for the executable code in the custom memory map. 2. Create a custom flash_copy.s program, using Figure 2 on page 3 as a template. Change the flash source memory start and end addresses and set the SRAM memory start address. a. Change the first two MOVIP commands in the flash_copy.s program to the flash start and end addresses in which the executable code that will be copied to the SRAM resides. The end address is determined by the size of the code that is stored in the flash. In the flash_copy.s example, the start and end addresses span the full 256K of SRAM (less the first 0x100 bytes that are used for the interrupt vector table). b. Change the third MOVIP command in the flash_copy.s program to point to the SRAM start address location. 3. Compile the flash_copy.s program using the nios-build utility to output the file flash_copy.srec. Use the -b option to specify a base address in the flash in which to store the application code. For example, the srec2flash utility is compiled to begin at 0x To compile flash_copy.s for a specified address, use the command: nios-build -b <base address> flash_copy.s 4. Open the <my program>.srec file in a text editor and save it as <my program>.flash. 5. Add the following lines to the beginning of the <my program>.flash file (refer back to Figure 1 on page 2 for an example): r0 e<flash block in which your application will reside> <3 middle lines (s-records) from the flash_copy.srec file you created in step 3> r<executable memory address> - <flash memory address> 1 Typically, flash memory must be erased in blocks and the block size varies according to the flash device used. Include enough erase commands in the.flash file so that sufficient flash space is erased before the application code is downloaded. 6. Save <my program>.flash. The <my program>.flash is now set to use a custom system memory map. Send the.flash file to the GERMS monitor running on the Nios development board using the following command: nios-run <my program>.flash The command stores your program, combined with the flash copy routine, into the flash location you designated. 5
6 S-Record File Format S-records are an industry-standard format for transmitting binary files to target systems and PROM programmers. The S-record format is as follows: S<type><length><address><data><checksum> where: <type> is a number from 0 to 9 where: 0 starting record (optional) 1 data record with 16-bit address 2 data record with 24-bit address 3 data record with 32-bit address 4 (special extension for symbol records) 5 number of data records in preceding block 6 unused 7 ending record for S3 records giving executable address 8 ending record for S2 records giving executable address 9 ending record for S1 records giving executable address <length> is two hex characters. <length> defines the length of the record in bytes and includes the address, data, and checksum fields. <address> is 4, 6, or 8 characters corresponding to a 16-, 24-, or 32-bit address. The address field for S4 records is always 32 bits. <data> are the data bytes. Each pair of hex characters represents one byte in memory. <checksum> is the one s complement of the 8-bit checksum. 101 Innovation Drive San Jose, CA (408) Copyright Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. All rights reserved. 6
DSP Development Kit, Stratix II Edition
DSP Development Kit, Stratix II Edition August 2005, Development Kit version 1.1.0 Errata Sheet This document addresses known errata and documentation changes the DSP Development Kit, Stratix II Edition
More informationActive Serial Memory Interface
Active Serial Memory Interface October 2002, Version 1.0 Data Sheet Introduction Altera Cyclone TM devices can be configured in active serial configuration mode. This mode reads a configuration bitstream
More informationWhite Paper Configuring the MicroBlaster Passive Serial Software Driver
White Paper Configuring the MicroBlaster Passive Serial Software Driver Introduction The MicroBlaster TM software driver is designed to configure Altera programmable logic devices (PLDs) through the ByteBlasterMV
More informationExcalibur Solutions DPRAM Reference Design
Excalibur Solutions DPRAM Reference Design August 22, ver. 2.3 Application Note 173 Introduction The Excalibur devices are excellent system development platforms, offering flexibility, performance, and
More informationNios Soft Core Embedded Processor
Nios Soft Core Embedded Processor June 2000, ver. 1 Data Sheet Features... Preliminary Information Part of Altera s Excalibur TM embedded processor solutions, the Nios TM soft core embedded processor is
More informationEstimating Nios Resource Usage & Performance
Estimating Nios Resource Usage & Performance in Altera Devices September 2001, ver. 1.0 Application Note 178 Introduction The Excalibur Development Kit, featuring the Nios embedded processor, includes
More informationDecember 2002, ver. 1.3 Application Note 191. Six individual interrupts Six-bit priority scheme Five-bit priority scheme plus one individual interrupt
Excalibur Solutions Using the Interrupt Controller December 22, ver..3 Application Note 9 Introduction This document describes the operation of the interrupt controller for the Excalibur devices, particularly
More informationAN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current
AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current January 2009 AN-547-10 Introduction To save power, the MAX II CPLD can be completely powered down into hibernation mode
More informationEnhanced Configuration Devices
Enhanced Configuration Devices October 2007, Version 1.2 Errata Sheet Introduction Intel-Flash- Based EPC Device Protection f This errata sheet provides updated information on enhanced configuration devices
More informationFPGA Design Security Solution Using MAX II Devices
White Paper FPGA Solution Using MAX II Devices Introduction SRAM-based FPGAs are volatile devices. They require external memory to store the configuration data that is sent to them at power up. It is possible
More informationUsing the Nios Development Board Configuration Controller Reference Designs
Using the Nios Development Board Controller Reference Designs July 2006 - ver 1.1 Application Note 346 Introduction Many modern embedded systems utilize flash memory to store processor configuration information
More informationWhite Paper Using the MAX II altufm Megafunction I 2 C Interface
White Paper Using the MAX II altufm Megafunction I 2 C Interface Introduction Inter-Integrated Circuit (I 2 C) is a bidirectional two-wire interface protocol, requiring only two bus lines; a serial data/address
More informationAN 549: Managing Designs with Multiple FPGAs
AN 549: Managing Designs with Multiple FPGAs October 2008 AN-549-1.0 Introduction Managing designs that incorporate multiple FPGAs raises new challenges that are unique compared to designs using only one
More informationNios II Embedded Design Suite 6.1 Release Notes
December 2006, Version 6.1 Release Notes This document lists the release notes for the Nios II Embedded Design Suite (EDS) version 6.1. Table of Contents: New Features & Enhancements...2 Device & Host
More informationSimple Excalibur System
Excalibur Solutions Simple Excalibur System August 2002, ver. 1.0 Application Note 242 Introduction This application note describes a simple Excalibur system design that consists of software running on
More informationWhite Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices
Introduction White Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices One of the challenges faced by engineers designing communications equipment is that memory devices
More informationNios Embedded Processor Development Board
Nios Embedded Processor Development Board July 2003, ver. 2.2 Data Sheet Introduction Development Board Features Functional Overview This data sheet describes the features and functionality of the Nios
More informationTable 1 shows the issues that affect the FIR Compiler v7.1.
May 2007, Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the Altera, v7.1. Errata are functional defects or errors, which may cause an Altera MegaCore function
More informationAN423: Configuring the MicroBlaster Passive Serial Software Driver
AN423: Configuring the MicroBlaster Passive Serial Software Driver June 2008, version 1.1 Introduction The MicroBlaster TM software driver configures Altera programmable logic devices (PLDs) in passive
More informationNios DMA. General Description. Functional Description
Nios DMA January 2003, Version 1.1 Data Sheet General Functional The Nios DMA module is an Altera SOPC Builder library component included in the Nios development kit. The DMA module allows for efficient
More informationSimulating the PCI MegaCore Function Behavioral Models
Simulating the PCI MegaCore Function Behavioral Models August 2001, ver. 1.0 Application Note 169 Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera,
More informationSimulating Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators
White Paper Simulating Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators You can use the Visual IP software from Innoveda with Altera-provided models to simulate Altera
More informationWhite Paper AHB to Avalon & Avalon to AHB Bridges
White Paper AHB to & to AHB s Introduction For years, system designers have been manually connecting IP peripheral functions to embedded processors, taking anywhere from weeks to months to accomplish.
More informationHPS SoC Boot Guide - Cyclone V SoC Development Kit
2014.07.03 AN-709 Subscribe Introduction This document describes the available boot stages and source modes for both the HPS and FPGA fabric. The boot sequence is a multi-stage process, where each stage
More informationIntroduction. Design Hierarchy. FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow
FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow February 2002, ver. 2.0 Application Note 171 Introduction To maximize the benefits of the LogicLock TM block-based design methodology in the
More informationSimulating the PCI MegaCore Function Behavioral Models
Simulating the PCI MegaCore Function Behavioral Models February 2003, ver. 1.2 Application Note 169 Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera,
More informationUsing MAX 3000A Devices as a Microcontroller I/O Expander
Using MAX 3000A Devices as a Microcontroller I/O Expander August 2003, Ver 1.0 Application Note 265 Introduction Advantages of Using MAX 3000A Devices Many microcontrollers and microprocessors limit I/O
More informationPractical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim
Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim Ray Duran Staff Design Specialist FAE, Altera Corporation 408-544-7937
More informationSimulating the Reed-Solomon Model
July 2000, ver. 1 Simulating the Reed-Solomon Model with the Visual IP Software User Guide Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera, and
More informationLaboratory Exercise 6
Laboratory Exercise 6 Using C code with the Nios II Processor This is an exercise in using C code with the Nios II processor in a DE-Series computer system. We will use the Intel FPGA Monitor Program software
More informationSimultaneous Multi-Mastering with the Avalon Bus
Simultaneous Multi-Mastering with the Avalon Bus April 2002, ver. 1.1 Application Note 184 Introduction The Excalibur Development Kit, featuring the Nios embedded processor version 2.1 supports an enhanced
More informationExcalibur Solutions Using the Expansion Bus Interface. Introduction. EBI Characteristics
Excalibur Solutions Using the Expansion Bus Interface October 2002, ver. 1.0 Application Note 143 Introduction In the Excalibur family of devices, an ARM922T processor, memory and peripherals are embedded
More informationToolflow for ARM-Based Embedded Processor PLDs
Toolflow for ARM-Based Embedded Processor PLDs December 2000, ver. 1 Application Note Introduction The Excalibur embedded processor devices achieve a new level of system integration from the inclusion
More informationUsing the Serial FlashLoader With the Quartus II Software
Using the Serial FlashLoader With the Quartus II Software July 2006, ver. 3.0 Application Note 370 Introduction Using the Joint Test Action Group () interface, the Altera Serial FlashLoader (SFL) is the
More informationExercise 1 In this exercise you will review the DSSS modem design using the Quartus II software.
White Paper DSSS Modem Lab Background The direct sequence spread spectrum (DSSS) digital modem reference design is a hardware design that has been optimized for the Altera APEX DSP development board (starter
More informationWhite Paper. Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core. Introduction. Parameters & Ports
White Paper Introduction Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core The floating-point fast fourier transform (FFT) processor calculates FFTs with IEEE 754 single precision (1
More informationEnhanced Configuration Devices
Enhanced Configuration Devices July 2008, Version 1.3 Errata Sheet Introduction Intel-Flash- Based EPC Device Protection f This errata sheet provides updated information on enhanced configuration devices
More informationUsing MAX II & MAX 3000A Devices as a Microcontroller I/O Expander
Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander March 2004, ver 2.0 Application Note 265 Introduction Advantages of Using MAX II & MAX 3000A Devices Many microcontroller and microprocessors
More informationGraduate Institute of Electronics Engineering, NTU Advanced VLSI SOPC design flow
Advanced VLSI SOPC design flow Advisor: Speaker: ACCESS IC LAB What s SOC? IP classification IP reusable & benefit Outline SOPC solution on FPGA SOPC design flow pp. 2 What s SOC? Definition of SOC Advantage
More informationNios PIO. General Description. Functional Description
Nios PIO January 2003, Version 3.1 Data Sheet General Description Functional Description The Nios parallel input/output (PIO) module is an Altera SOPC Builder library component included in the Nios development
More informationUTOPIA Level 2 Slave MegaCore Function
UTOPIA Level 2 Slave MegaCore Function October 2005, Version 2.5.0 Release Notes These release notes for the UTOPIA Level 2 Slave MegaCore function contain the following information: System Requirements
More informationIntroduction to the Altera SOPC Builder Using Verilog Design
Introduction to the Altera SOPC Builder Using Verilog Design This tutorial presents an introduction to Altera s SOPC Builder software, which is used to implement a system that uses the Nios II processor
More informationDebugging Nios II Systems with the SignalTap II Logic Analyzer
Debugging Nios II Systems with the SignalTap II Logic Analyzer May 2007, ver. 1.0 Application Note 446 Introduction As FPGA system designs become more sophisticated and system focused, with increasing
More informationDisassemble the machine code present in any memory region. Single step through each assembly language instruction in the Nios II application.
Nios II Debug Client This tutorial presents an introduction to the Nios II Debug Client, which is used to compile, assemble, download and debug programs for Altera s Nios II processor. This tutorial presents
More informationIntroduction to the Altera SOPC Builder Using Verilog Designs. 1 Introduction
Introduction to the Altera SOPC Builder Using Verilog Designs 1 Introduction This tutorial presents an introduction to Altera s SOPC Builder software, which is used to implement a system that uses the
More informationDSP Builder. DSP Builder v6.1 Issues. Error When Directory Pathname is a Network UNC Path
March 2007, Version 6.1 Errata Sheet This document addresses known errata and documentation changes for DSP Builder version 6.1. Errata are functional defects or errors which may cause DSP Builder to deviate
More informationImplementing LED Drivers in MAX Devices
Implementing LE rivers in MAX evices ecember 2002, ver. 1.0 Application Note 286 Introduction Commercial LE river Chips iscrete light-emitting diode (LE) driver chips are common on many system boards.
More informationFFT/IFFT Block Floating Point Scaling
FFT/IFFT Block Floating Point Scaling October 2005, ver. 1.0 Application Note 404 Introduction The Altera FFT MegaCore function uses block-floating-point (BFP) arithmetic internally to perform calculations.
More informationRLDRAM II Controller MegaCore Function
RLDRAM II Controller MegaCore Function November 2006, MegaCore Version 1.0.0 Errata Sheet This document addresses known errata and documentation issues for the RLDRAM II Controller MegaCore function version
More informationFPGAs Provide Reconfigurable DSP Solutions
FPGAs Provide Reconfigurable DSP Solutions Razak Mohammedali Product Marketing Engineer Altera Corporation DSP processors are widely used for implementing many DSP applications. Although DSP processors
More informationVideo and Image Processing Suite
Video and Image Processing Suite December 2006, Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the MegaCore functions in the Video and Image Processing Suite,
More informationDDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler May 2006, Compiler Version 3.3.1 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 3.3.1.
More informationTable 1 shows the issues that affect the FIR Compiler, v6.1. Table 1. FIR Compiler, v6.1 Issues.
December 2006, Version 6.1 Errata Sheet This document addresses known errata and documentation issues for the Altera FIR Compiler, v6.1. Errata are functional defects or errors, which may cause an Altera
More informationRapidIO Physical Layer MegaCore Function
RapidIO Physical Layer MegaCore Function April 2005, MegaCore version 2.2.1 Errata Sheet Introduction This document addresses known errata and documentation changes for version 2.2.1 of the RapidIO Physical
More informationMatrices in MAX II & MAX 3000A Devices
Crosspoint Switch Matrices in MAX II & MAX 3000A Devices March 200, ver. 2.0 Application Note 29 Introduction With a high level of flexibility, performance, and programmability, you can use crosspoint
More informationImplementing LED Drivers in MAX and MAX II Devices. Introduction. Commercial LED Driver Chips
Implementing LE rivers in MAX and MAX II evices October 2008 AN-286-2.3 Introduction iscrete LE driver chips are common on many system boards. Altera MAX II, MAX 7000B, MAX 7000A, MAX 3000A, and MAX 7000S
More informationLaboratory Exercise 8
Laboratory Exercise 8 Introduction to Graphics and Animation The purpose of this exercise is to learn how to display images and perform animation. We will use the Nios II processor, in the pre-build DE-series
More informationSimulating Nios II Embedded Processor Designs
Simulating Nios II Embedded Processor Designs May 2004, ver.1.0 Application Note 351 Introduction The increasing pressure to deliver robust products to market in a timely manner has amplified the importance
More informationMAX 10 User Flash Memory User Guide
MAX 10 User Flash Memory User Guide Subscribe Last updated for Quartus Prime Design Suite: 16.0 UG-M10UFM 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents MAX 10 User Flash Memory
More informationLaboratory Exercise 7
Laboratory Exercise 7 Using Interrupts with C code The purpose of this exercise is to investigate the use of interrupts for the Nios II processor, using C code. To do this exercise you need to have a good
More informationDDR & DDR2 SDRAM Controller
DDR & DDR2 SDRAM Controller October 2005, Compiler Version 3.3.0 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.0 contain the following information: System
More informationRemote Drive. Quick Start Guide. System Level Solutions, Inc. (USA) Murphy Avenue San Martin, CA (408) Version : 0.1.
Remote Drive Quick Start Guide, Inc. (USA) 14100 Murphy Avenue San Martin, CA 95046 (408) 852-0067 http://www.slscorp.com Version : 0.1.1 Date : July 17, 2007 Copyright 2007,.All rights reserved. SLS,
More informationBooting Excalibur Devices
Booting Excalibur Devices March 2003, ver. 1.2 Application Note 187 Introduction The Altera Excalibur devices combines an unparalleled degree of integration and programmability on a single chip. The advantages
More informationPCI Express Compiler. System Requirements. New Features & Enhancements
April 2006, Compiler Version 2.1.0 Release Notes These release notes for the PCI Express Compiler version 2.1.0 contain the following information: System Requirements New Features & Enhancements Errata
More informationIncreasing Productivity with Altera Quartus II to I/O Designer/DxDesigner Interface
Increasing Productivity with Altera Quartus II to I/O Designer/DxDesigner Interface Steven Strell Senior Applications Engineer, Altera Corporation (408) 544-7624 sstrell@altera.com 1 Abstract Today s high-speed,
More informationSimulating the ASMI Block in Your Design
2015.08.03 AN-720 Subscribe Supported Devices Overview You can simulate the ASMI block in your design for the following devices: Arria V, Arria V GZ, Arria 10 Cyclone V Stratix V In the Quartus II software,
More informationLegacy SDRAM Controller with Avalon Interface
Legacy SDRAM Controller with Avalon Interface January 2003, Version 1.0 Data Sheet Introduction PTF Assignments SDRAM is commonly used in cost-sensitive applications requiring large amounts of memory.
More informationPCI Express Multi-Channel DMA Interface
2014.12.15 UG-01160 Subscribe The PCI Express DMA Multi-Channel Controller Example Design provides multi-channel support for the Stratix V Avalon Memory-Mapped (Avalon-MM) DMA for PCI Express IP Core.
More informationNIOS II Processor Booting Methods In MAX 10 Devices
2015.01.23 AN-730 Subscribe MAX 10 device is the first MAX device series which supports Nios II processor. Overview MAX 10 devices contain on-chip flash which segmented to two types: Configuration Flash
More informationDDR & DDR2 SDRAM Controller
DDR & DDR2 SDRAM Controller December 2005, Compiler Version 3.3.1 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.1 contain the following information: System
More informationByteBlaster II Parallel Port Download Cable
ByteBlaster II Parallel Port Download Cable December 2002, Version 1.0 Data Sheet Features Allows PC users to perform the following functions: Program MAX 9000, MAX 7000S, MAX 7000AE, MAX 7000B, MAX 3000A,
More informationPOS-PHY Level 4 MegaCore Function
POS-PHY Level 4 MegaCore Function November 2004, MegaCore Version 2.2.2 Errata Sheet Introduction This document addresses known errata and documentation changes for version v2.2.2 of the POS-PHY Level
More informationStratix II vs. Virtex-4 Performance Comparison
White Paper Stratix II vs. Virtex-4 Performance Comparison Altera Stratix II devices use a new and innovative logic structure called the adaptive logic module () to make Stratix II devices the industry
More informationPOS-PHY Level 4 POS-PHY Level 3 Bridge Reference Design
Level 4 Bridge Reference Design October 2001; ver. 1.02 Application Note 180 General Description This application note describes how the Level 4 Bridge reference design can be used to bridge packet or
More informationNios II Embedded Design Suite 7.1 Release Notes
Nios II Embedded Design Suite 7.1 Release Notes May 2007, Version 7.1 Release Notes This document contains release notes for the Nios II Embedded Design Suite (EDS) version 7.1. Table of Contents: New
More informationNios Embedded Processor UART Peripheral
Nios Embedded Processor UART Peripheral March 2001, ver. 1.1 Data Sheet General Description The Nios universal asynchronous receiver/transmitter UART implements simple RS-232 asynchronous transmit and
More informationBoard Update Portal based on Nios II Processor with EPCQ (Arria 10 GX FPGA Development Kit)
Board Update Portal based on Nios II Processor with EPCQ (Arria 10 GX FPGA Development Kit) Date: 1 December 2016 Revision:1.0 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY,
More informationSupporting Custom Boards with DSP Builder
Supporting Custom Boards with DSP Builder April 2003, ver. 1.0 Application Note 221 Introduction As designs become more complex, verification becomes a critical, time consuming process. To address the
More informationUsing MicroC/OS-II RTOS with the Nios II Processor Tutorial Preliminary Information
Using MicroC/OS-II RTOS with the Nios II Processor Tutorial Preliminary Information 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Copyright 2004 Altera Corporation. All rights
More informationError Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide
Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide 11 Innovation Drive San Jose, CA 95134 www.altera.com Software Version 8. Document Version: 2. Document Date: June 28
More informationWhite Paper Understanding 40-nm FPGA Solutions for SATA/SAS
White Paper Understanding 40-nm Solutions for /SAS This white paper describes the and SAS protocols, how the protocols are used, explains the value and SAS in terms of usage in an, and illustrates how
More informationFor Quartus II Software. This Quick Start Guide will show you how to set up a Quartus
Quick Start Guide For Quartus II Software This Quick Start Guide will show you how to set up a Quartus II project, enter timing requirements, and compile the design into an Altera device. 1 Three-Step
More informationWhite Paper Performing Equivalent Timing Analysis Between Altera Classic Timing Analyzer and Xilinx Trace
Introduction White Paper Between Altera Classic Timing Analyzer and Xilinx Trace Most hardware designers who are qualifying FPGA performance normally run bake-off -style software benchmark comparisons
More informationArria II GX FPGA Development Board
Arria II GX FPGA Development Board DDR2 SODIMM Interface 2011 Help Document DDR2 SODIMM Interface Measurements were made on the DDR2 SODIMM interface using the Board Test System user interface. The Address,
More informationCORDIC Reference Design. Introduction. Background
CORDIC Reference Design June 2005, ver. 1.4 Application Note 263 Introduction The co-ordinate rotation digital computer (CORDIC) reference design implements the CORDIC algorithm, which converts cartesian
More informationRapidIO MegaCore Function
March 2007, MegaCore Function Version 3.1.1 Errata Sheet This document addresses known errata and documentation issues for the Altera RapidIO MegaCore function version 3.1.1. Errata are functional defects
More informationSONET/SDH Compiler. Introduction. SONET/SDH Compiler v2.3.0 Issues
January 2005, Compiler Version 2.3.0 Errata Sheet Introduction This document addresses known errata and documentation changes for version 2.3.0 of the SONET/SDH Compiler. Errata are design functional defects
More informationDDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler march 2007, Compiler Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 7.0.
More informationUsing the SDRAM on Altera s DE1 Board with Verilog Designs. 1 Introduction. For Quartus II 13.0
Using the SDRAM on Altera s DE1 Board with Verilog Designs For Quartus II 13.0 1 Introduction This tutorial explains how the SDRAM chip on Altera s DE1 Development and Education board can be used with
More informationLogic Optimization Techniques for Multiplexers
Logic Optimiation Techniques for Multiplexers Jennifer Stephenson, Applications Engineering Paul Metgen, Software Engineering Altera Corporation 1 Abstract To drive down the cost of today s highly complex
More informationCyclone II FPGA Family
ES-030405-1.3 Errata Sheet Introduction This errata sheet provides updated information on Cyclone II devices. This document addresses known device issues and includes methods to work around the issues.
More informationDDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler August 2007, Compiler Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version
More informationReal-Time ISP and ISP Clamp for Altera CPLDs
Real-Time ISP and ISP Clamp for Altera CPLDs AN-630-1.0 Application Note This application note describes the real-time in-system programmability (ISP) and ISP Clamp programming modes and their usage in
More informationNios Soft Core. Development Board User s Guide. Altera Corporation 101 Innovation Drive San Jose, CA (408)
Nios Soft Core Development Board User s Guide Altera Corporation 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Nios Soft Core Development Board User s Guide Version 1.1 August
More informationDesign Verification Using the SignalTap II Embedded
Design Verification Using the SignalTap II Embedded Logic Analyzer January 2003, ver. 1.0 Application Note 280 Introduction The SignalTap II embedded logic analyzer, available exclusively in the Altera
More informationZBT SRAM Controller Reference Design
ZBT SRAM Controller Reference Design for APEX II Devices December 2001, ver. 1.0 Application Note 183 Introduction As communication systems require more low-latency, high-bandwidth interfaces for peripheral
More informationNios II Performance Benchmarks
Subscribe Performance Benchmarks Overview This datasheet lists the performance and logic element (LE) usage for the Nios II Classic and Nios II Gen2 soft processor, and peripherals. Nios II is configurable
More informationTransient Voltage Protection for Stratix GX Devices
White Paper Devices Introduction This document addresses the phenomenon known as transient voltage in a system using Stratix GX devices. Hot socketing is identified as the major source of transient voltage.
More informationByteBlaster II Download Cable User Guide
ByteBlaster II Download Cable User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com UG-BBII81204-1.1 P25-10324-00 Document Version: 1.1 Document Date: December 2004 Copyright
More informationQuad-Serial Configuration (EPCQ) Devices Datasheet
2016.05.30 CF52012 Subscribe This datasheet describes quad-serial configuration (EPCQ) devices. EPCQ is an in-system programmable NOR flash memory. Supported Devices Table 1: Supported Altera EPCQ Devices
More information