Graduate Institute of Electronics Engineering, NTU Advanced VLSI SOPC design flow
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1 Advanced VLSI SOPC design flow Advisor: Speaker: ACCESS IC LAB
2 What s SOC? IP classification IP reusable & benefit Outline SOPC solution on FPGA SOPC design flow pp. 2
3 What s SOC? Definition of SOC Advantage of SOC IP classification IP reusable & benefit Outline SOPC solution on FPGA SOPC design flow pp. 3
4 System-on on-a-chip 1. Use standard bus, to transfer data among blocks. 2. For bus IO, block reusable is benefit. 3. IO pad of chip is the limit of freq. But freq. in the same chip can be higher. pp. 4
5 Changes in the Nature of IC Design pp. 5
6 Ex: JPEG video system pp. 6
7 SOC pp. 7
8 System-level IC Development pp. 8
9 What s SOC? IP classification Soft IP Firm IP Hard IP IP reusable & benefit Outline SOPC solution on FPGA SOPC design flow pp. 9
10 1. Soft IP: ( Code ) Types of IP 1. Synthesizable HDL description at RTL level 2. Flexible: can be changed to suit an application 3. Technology independent: may be re-synthesized across process 4. Significant IP protection risk pp. 10
11 Types of IP 1. Firm IP: ( synthesizable netlist + structure ) 1. Gate-level netlist optimized structurally and topologically for performance and size 2. Floorplanning or placement without routing pp. 11
12 Types of IP (cont.) 3. Hard IP: ( physical ) 1. Ready for drop in 2. Include layout and timing information 3. Optimized for performance, size, and power 4. IP is easily protected pp. 12
13 Categorizing Reusable Blocks pp. 13
14 Tradeoffs among types of blocks pp. 14
15 What s SOC? IP classification Outline IP reusable & benefit SOPC solution on FPGA SOPC design flow pp. 15
16 Engineering Productivity Gap 1. Engineering productivity has not been keeping up with silicon gate capacity for several years. 2. Companies have been using larger design teams, making engineers work longer hours, etc., but clearly the limit is being reached. pp. 16
17 Why must IP Reuse? pp. 17
18 What s SOC? IP classification IP reusable & benefit Outline SOPC solution on FPGA SOPC design flow pp. 18
19 What is SOPC? Processor Embedded Processor Memory Complete SOPC Solution FPGAHigh- (System-On-a- Programmable- Chip) Logic Performance I/O pp. 19
20 Introduce to SOPC solution Soft embedded processor design & prototyping environment pp. 20
21 Introduce to SOPC solution Hard embedded processor design & prototyping environment pp. 21
22 Excalibur Nios Device Support Performance (MIPS) Future PLD Architectures TM Embedded Core Excalibur MIPS Excalibur ARM Mercury Devices APEX Devices FLEX 10K Devices ACEX Devices 0 pp. 22
23 Flexibility & Scalability Low-Cost High-Performance Embedded Processor Custom DSP Multi-Processor System DSP ESB ESB ESB ESB 75K Gates Available ACEX EP1K K Gates Available ESB ESB ESB ESB ESB ESB ESB ESB APEX EP20K200E 500K Gates Available Excalibur ARM Stripe Excalibur XA10 pp. 23
24 Nios 32-Bit and 16-Bit RISC CPU Peripherals Development Board Development Tools Nios Development Kit pp. 24
25 Nios Embedded Processor Core Configurable Soft Core Processor 32-Bit Pipelined RISC Architecture Large Internal Register File Fully synchronous interface Configurable Data Path 30 to 80 MIPS Performance Dynamic Bus Sizing SRAM FLASH Serial Port Altera PLD PBM CPU Timer UART IRQ Your Design Here 12% of EP20K200E pp. 25
26 What s SOC? IP classification IP reusable & benefit Outline SOPC solution on FPGA SOPC design flow pp. 26
27 Nios System Overview A complete Nios system module contains a Nios embedded processor and its associated system peripherals. The SOPC Builder helps you easily specify options for the Nios system module. Nios system module contains hardware and software sections pp. 27
28 Nios System Overview(cont.) Peripheral components Memory Interface RAM, ROM Serial I/O UART PIO(parallel IO) Seven Segment LED, LCD User defined Interface Timer pp. 28
29 Nios System Overview(cont.) The SOPC builder let NIOS module easy specified by using wizard Almost constraint can be changed to fit our own design, such as peripheral library. pp. 29
30 Nios System Overview(cont.) Hardware & Software generation Nios system module contains: Hardware : (HDL code) describe the hardware module -download by QuartsII Software : (header file) define c program library to develop your own program -download by NIOS SDK pp. 30
31 Tool Design Flow Configure Processor Peripheral Library Hardware Processor Design Simulation Test Bench Synthesis Place & Route User Design Purchased IP Hardware Configuration File Select Peripherals Generate JTAG Serial Download & Debug Altera PLD Executable Code Software C Header files Custom Library Boot monitor Cygnus/Red Hat GNUPro User Code S/W Libraries RTOS pp. 31
32 Create your design Create project file Create *.BDF file Steps Add SOPC into your design Connect your own block & IO pad to Nios CPU Compile & Pin Assignment Software development Download your design pp. 32
33 Select File => New Project Wizard Create a new project Working Directory Project name Top-level design name Create a new project in the path C:\AVLSI\<your id>\lab2 Click finish pp. 33
34 Create a new schematic Create a *.bdf file, for placing SOPC system, include NIOS CPU & other block Block design file pp. 34
35 Steps Create your design Add SOPC into your design Create CPU Add peripherals Generate hardware & software design Connect your own block & IO pad to Nios CPU Compile & Pin Assignment Software development Download your design pp. 35
36 Create NIOS32 CPU Select symbol from tool menu bar, And click Mega Wizard Plug-In Manager pp. 36
37 Create megafunction SOPC is one block of megafunction Create a new megafunction, to familiar with it s content pp. 37
38 Select Altera SOPC Builder 2.5 and Use SOPC Builder Choose Verilog HDL to perform the soft core CPU pp. 38
39 Double click the component list for adding it into your design Add Components pp. 39
40 Current List of Peripherals UART PIO Timer SPI PWM IDE Keyboard PS2 Mouse VGA Ethernet PCI SRAM SDRAM Flash Compact Flash On-chip RAM On-chip ROM User-Defined pp. 40
41 PIO Peripheral PIO Peripheral 1 to 32-bit Parallel I/O Port Input Only Output Only Bi-directional Port Edge Detection on Inputs Interrupt Generation Mask-able IRQ Source pp. 41
42 User-Defined Interface Interface to Other Peripherals Configures Busses and Timing Adds Port Signals to Design Altera PLD Nios CPU Avalon Bus I/O I/O I/O I/O Nios System Module User I/F External Device pp. 42
43 Addon Component Peripheral components Altera PLD Memory Interface RAM, ROM, flash Serial I/O UART PIO(parallel IO) Seven Segment Nios CPU Avalon Bus I/O I/O I/O I/O LED, LCD User defined Interface Nios System Module User I/F External Device Timer pp. 43
44 The demo board pp. 44
45 Add CPU Choose 32 bit RISC CPU, then click Finish Click finish pp. 45
46 Steps Create your design Add SOPC into your design Create CPU Add peripherals Generate hardware & software design Connect your own block & IO pad to Nios CPU Compile & Pin Assignment Software development Download your design pp. 46
47 Choose On-chip Memory pp. 47
48 GERMS Monitor UART Monitor Program Runs from On-Chip ROM Debugger Runs on Host PC or UNIX Platform Basic Development Facilities: Download Code Burn Flash Examine/Modify Memory Run Programs Debug Monitor pp. 48
49 GERMS G Go E Erase Flash R Relocate M Memory S Motorola S record : Intel Hex record CR show next 64 Bytes of memory Escape Restart GERMS monitor pp. 49
50 Flash memory setting Simulate by Quarts II pp. 50
51 Steps Create your design Add SOPC into your design Create CPU Add peripherals Generate hardware & software design Connect your own block & IO pad to Nios CPU Compile & Pin Assignment Software development Download your design pp. 51
52 SOPC Setup Choose verilog and APEX 20KE in HDL generation pp. 52
53 Generate System Module Software Development Kit (SDK) Hardware Design Synthesis pp. 53
54 What happen after Generate Software nios.h :define the peripheral address :define the memory map Hardware A NIOS CPU module constructed by verilog code pp. 54
55 IO have their addr. Software Generation /* * File: nios.h * * This file is a machine generated address map * for a Nios cpu named cpu. * f:/ /avlsi/r /lab2/nios32.ptf * Generated: :29:11 */ // The Memory Map #define na_uart_1_debug ((np_uart *) 0x ) #define na_uart_1_debug_irq 17 #define na_timer_0 ((np_timer *) 0x ) #define na_timer_0_irq 18 #define na_led_pio ((np_pio *) 0x ) #define na_button_pio ((np_pio *) 0x ) #define na_button_pio_irq 19 #define na_ext_ram ((void *) 0x ) #define na_ext_ram_end ((void *) 0x ) #define na_ext_ram_size ((void *) 0x ) #define na_ext_flash ((void *) 0x ) pp. 55
56 Hardware Genereation After generation, a NIOS module appears in Symbol pp. 56
57 Create your design Steps Add SOPC into your design Connect your own block & IO pad to Nios CPU Compile & Pin Assignment Software development Download your design pp. 57
58 Add IO Pad Use add symbol to add IO pad to schematic. pp. 58
59 Create your design Steps Add SOPC into your design Connect your own block & IO pad to Nios CPU Pin Assignment & Compile Download your design pp. 59
60 Assign Pins Compile first Assign the IO pins to the I/O Interface on develop board Compile then pp. 60
61 Create your design Steps Add SOPC into your design Connect your own block & IO pad to Nios CPU Compile & Pin Assignment Software development Download your design pp. 61
62 Software Develop CPU contains hardware part and software part Hardware part was created above Software part is written in c or c++ language, then compiled into assembly code Take an example for writing c++ program to control CPU change light when press switch pp. 62
63 How to write code Define memory map & peripheral addr led button 0: input 1:output 2:bidrection pp. 63
64 How to write code(cont.) Get data Change led light Write data pp. 64
65 Create your design Steps Add SOPC into your design Connect your own block & IO pad to Nios CPU Compile & Pin Assignment Software development Download your design pp. 65
66 Memory Usage *.srec is downloaded into SRAM, can t still exist after reset Flash memory store the data executed automatically when boot 1Mb Flash Factory APEX Image User APEX Image User Software Data Address APEX SRAM 256Kb ROM pp. 66
67 NIOS SDK UNIX like environment Open from Start Menu/program files/altera/excalibur NIOS 2.0/NIOS SDK Shell pp. 67
68 NIOS Command nios-build: Compile, Assemble & Link Transpose c program into <program>.srec nios-run: Download Executable & Run burn flash with <project>.hexout(hardware) or <program>.flash(software) Download *.srec to SRAM srec2flash: Create Flash-bootable Code Convert <program>.srec to <program>.flash pp. 68
69 Nios Routines nios-build hello.c (nb hello.c) Builds program including compile, link and convert to SREC nios-run hello.srec (nr hello.srec) Downloads using com1 and enters terminal mode nr p com2 hello.srec Downloads using com2 nr x hello.srec Downloads without entering terminal mode nr t Enters terminal mode without download (Ctrl + C to exit) pp. 69
70 Download routine nr <project>.hexout -download hardware design nr <program>.srec design -download software pp. 70
71 NIOS Tutorial LAB Have a C code to generate sine wave and display to 7-segment LED. Program should read data from DIP SW as a value of delay loop. ( pi / 10) pp. 71
72 Homework Use Mega Plug-In Manager to generate NIOS with DIP SW and necessary peripheral device. Use Mega Plug-In Manager to generate a 4 by 4 multiplier. Have a verilog code to decode 8 bit binary to 7- segment. Have a C code to read two 4-bit data from DIP SW and send data to 4 by 4 multiplier. The multiplier output should connect to decoder directly to display answer. Use LA to read answer-data to verify, too. pp. 72
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