MDP Based Face Detection Demonstration User Guide
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1 FPGA-UG Version 1.0 May 2018
2 Contents Acronyms in This Document Introduction Functional Description Demo Setup Programming the Face Detection Demo Running the Face Detection Demo Technical Support Revision History Figures Figure 2.1. Face Detection Demo Diagram... 4 Figure 3.1. MDP Board with Configuration Locations Highlighted... 5 Figure 4.1. Create a New Blank Project... 7 Figure 4.2. Bitstream File Settings... 8 Figure 4.3. Binary Firmware File Settings... 9 Figure 5.1. Camera and LED Location Tables Table 3.1. MDP Board Configuration Details FPGA-UG
3 Acronyms in This Document A list of acronyms used in this document. Acronym Definition BNN FPGA LED MDP SOIC SPI USB Binary Neural Network Field-Programmable Gate Array light-emitting diode Mobile Development Platform Small Outline Integrated Circuit Serial Peripheral Interface Universal Serial Bus FPGA-UG
4 1. Introduction This document describes how to operate the Face Detection demo on the ice40 UltraPlus Mobile Development Platform (MDP) board. The design features a Binary Neural Network (BNN) soft IP which is used in face detection. 2. Functional Description There are four ice40 UltraPlus devices on the MDP board. The ice40up5k_d (U4 on the MDP board) device is used to run this demo. In this demo, an LED indicates when a face is detected. When the camera detects the face, the LED indicator turns ON. When the camera does not detect a face, the LED stays OFF. Figure 2.1 shows the diagram of the Face Detection demo. The camera captures the image data and sends it to the ice40 device. ice40 then uses the image data with the firmware file from the external SPI Flash to determine if the face is detected. Figure 2.1. Face Detection Demo Diagram 4 FPGA-UG
5 3. Demo Setup Before running the demo, the MDP board must be configured by setting the switches and jumpers as shown in Figure 3.1. Note: Figure 3.1 is a default image of the MDP board and the switch/jumper configurations shown here are wrong. The orange rectangles are provided only to help you locate the correct locations of the switches/jumpers. Be sure to read the information in Error! Reference source not found. for the correct configuration settings. Figure 3.1. MDP Board with Configuration Locations Highlighted FPGA-UG
6 Table 3.1 provides detailed information on the MDP switch and jumper configuration. Table 3.1. MDP Board Configuration Details Items Configuration Description J17,J26 Shunt pin 9-10 Disable ICE40UP5K_A/C devices. J25 Shunt pin Disable ICE40UP5K_B device. J27 Shunt pin 1-2 Enable ICE40UP5K_D device. J27 Shunt pin 3-4 Provide power supply to camera sensor from USB cable. J28 Shunt pin 1-2 Board control, for programming SPI Flash. J19 Shunt pin 1-3,2-4 (vertical) Enable programming SPI Flash. J23 Shunt pin 2-3 Use Xtal U14 as clock source. SW2 Set to ON Power switch, slide down for power-on. SW5 All set to ON Slide right to select ICE40UP5K_D as target device. *Important: Make sure that the protective film is removed from the camera sensor U39. If using Rev C MDP board, check the MDP Revision Guide to ensure that your MDP board has the correct resistor series. The MDP Revision Guide is provided in the Documentation folder of MDP Based Face Detection Demonstration Bitstream. 6 FPGA-UG
7 4. Programming the Face Detection Demo This section provides the procedure for programming the SPI Flash on the MDP Board Two different files should be programmed into the SPI Flash. These files are programmed to the same SPI Flash but at different addresses: bitstream file firmware file To program the SPI Flash in Radiant Programmer: 1. Connect the MDP board to the PC using a USB cable and power ON the MDP board. 2. Start Radiant Programmer. In the Radiant Programmer Getting Started dialog box, select Create a new blank project as shown in Figure Click OK. Figure 4.1. Create a New Blank Project 4. In the Radiant Programmer main interface, set Device Family to ice40 UltraPlus and Device to ice40up5k. 5. Click the ice40 UltraPlus row and select Edit > Device Properties. 6. In the Device Properties dialog box, apply the settings below that are common to the two files to program. a. Under Device Operation, select the options below: Target Memory: External SPI Flash Memory Port Interface: SPI Access Mode: Direct Programming Operation: Erase, Program, Verify b. Under SPI Flash Options, select the options below: Family: SPI Serial Flash Vendor: Micron Device: SPI-M25P80 Package: 8-pin SOIC 7. To program the bitstream file, select the options below as shown in Figure 4.2. a. Under Programming Options, select the bitstream file FaceDetection_bitstream.bin in Programming file b. Click Load from File to update the Data file size (Bytes) value. c. Ensure that the following addresses are correct: FPGA-UG
8 Start Address (Hex): 0x End Address (Hex): 0x d. Click OK. Figure 4.2. Bitstream File Settings e. In the main interface, click Program Device to program the bitstream file FaceDetection_bitstream.bin. 8. To program the binary firmware file, select the options below as shown in Figure 4.3. a. Under Programming Options, select the binary file FaceDetection_firmware.bin in Programming file b. Click Load from File to update the Data file size (Bytes) value. Ensure that Data file size is If not, manually change the value to c. Ensure that the following addresses are correct: Start Address (Hex): 0x End Address (Hex): 0x d. Click OK. 8 FPGA-UG
9 Figure 4.3. Binary Firmware File Settings e. In the main interface, click Program Device to program the binary file FaceDetection_firmware.bin. 9. After programming the files, perform a power cycle in order to start observing the demo. FPGA-UG
10 5. Running the Face Detection Demo To run the basic demo and observe results on the board: 1. Power ON the MDP board. 2. Position a face in front of the camera on the board. 3. When the face is detected, LED D14 turns ON. If the face is not detected LED D14 stays OFF. Refer to Figure 5.1 for the location of LED D14 and camera (U39) Figure 5.1. Camera and LED Location 10 FPGA-UG
11 Technical Support For assistance, submit a technical support case at Revision History Date Version Change Summary May Initial release. FPGA-UG
12
13 7 th Floor, 111 SW 5 th Avenue Portland, OR 97204, USA T
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