Corona (MAXREFDES12#) Nexys 3 Quick Start Guide
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1 Corona (MAXREFDES12#) Nexys 3 Quick Start Guide Rev 0; 4/13 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated 160 Rio Robles, San Jose, CA USA Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2 Table of Contents 1. Required Equipment Overview Included Files Procedure Code Documentation Appendix A: Project Structure and Key Filenames Trademarks Revision History
3 1. Required Equipment PC with Windows OS with Xilinx ISE /SDK version 13.4 or later and one USB port License for Xilinx EDK/SDK version 13.4 or later Corona (MAXREFDES12#) board Nexys 3 development kit One 24V 1A DC power supply 2. Overview Below is a high-level overview of the steps required to quickly get the Corona design running by downloading and running the FPGA project. Detailed instructions for each step are provided in the following pages. The Corona (MAXREFDES12#) subsystem reference design will be referred to as Corona throughout this document. 1) Connect the Corona board to the JA1 port of a Nexys 3 development kit as shown in Figure 1. Ensure the connector is aligned as shown in Figure 2. 2) Download the latest RD12V01_00.ZIP file located at the Corona page. 3) Extract the RD12V01_00.ZIP file to a directory on your PC. 4) Open the Xilinx SDK. 5) Download the bitstream (.BIT) file to the board. This bitstream contains the FPGA hardware design and software bootloader. 6) Use Xilinx SDK to download and run the executable file (.ELF) on the MicroBlaze. 3
4 Figure 1. Corona Board Connected to Nexys 3 Development Kit Figure 2. Pmod Connector Alignment 4
5 3. Included Files The top level of the hardware design is a Xilinx ISE Project Navigator Project (.XISE) for Xilinx ISE version The Verilog-based HDL design instantiates the MicroBlaze core, the support hardware required to run the MicroBlaze, and the peripherals that interface to the Pmod ports. This is supplied as a Xilinx software development kit (SDK) project that includes a demonstration software application to evaluate the Corona subsystem reference design. The lower level c-code driver routines are portable to the user s own software project. Figure 3. Block Diagram of FPGA Hardware Design 5
6 4. Procedure 1. Connect the Corona board to the JA1 port of a Nexys 3 development kit as shown in Figure Connect the 24V DC power-supply positive terminal to the TP3 connector on the Corona board. Connect the 24V DC power-supply ground terminal to the TP4 connector on the Corona board. 3. Power up the Nexys 3 development kit by sliding the SW8 switch on the Nexys 3 board to the ON position. 4. Download the latest RD12V01_00.ZIP file at All files available for download are available at the bottom of the page. 5. Extract the RD12V01_00.ZIP file to a directory on your PC. The location is arbitrary but the maximum path length limitation in Windows (260 characters) should not be exceeded. In addition, the Xilinx tools require the path to not contain any spaces. C:\Do Not Use Spaces In The Path\RD12V01_00.ZIP (This path has spaces.) For the purposes of this document, it will be C:\designs\maxim\RD12V01_00\. See Appendix A: Project Structure and Key Filenames in this document for the project structure and key filenames. 6
7 6. Open the Xilinx Software Development Kit (SDK) from the Windows Start menu. 7. SDK will prompt for a workspace directory, which is the location where the software project is located. For this example, it is: C:\designs\maxim\RD12V01_00\RD12_NEXYS3_V01_00\Design_Files\sdkWorkspace Click OK and SDK will open. The Xilinx SDK is based on an Eclipse -based IDE, so it will be a familiar flow for many software developers. 7
8 8. Review the SDK IDE. The Project Explorer in the upper left tab should have three components as shown in the image below. If all three subfolders are present, you can skip the next step. 8
9 9. If the Project Explorer does not contain these three subfolders, launch the File Import menu, expand the General folder, and select Existing Projects into Workspace. Click Next. Set the root directory to: C:\designs\maxim\RD12V01_00\RD12_NEXYS3_V01_00\Design_Files\sdkWorkspace and the missing projects should appear in SDK Project Explorer with their checkboxes checked. Click Finish to import the projects. 9
10 10. To download the bitstream (.BIT) file to the board, click on the Program FPGA icon (which looks like a green chain of devices). The Program FPGA dialog box appears. From here, an FPGA bitstream (.BIT) file is selected as well as an FPGA BMM (.BMM) file. Be sure to select the.bit file and the.bmm by using the paths below. Bitstream: C:\designs\maxim\RD12V01_00\RD12_NEXYS3_V01_00\Design_Files\ sdkworkspace\system_hw_platform\system.bit BMM File: C:\designs\maxim\RD12V01_00\RD12_NEXYS3_V01_00\Design_Files\ sdkworkspace\system_hw_platform\system_bd.bmm 10
11 Additionally, make sure bootloop is selected as shown, then press Program. It takes approximately 10 seconds to download the FPGA, then a message box indicating FPGA configuration complete appears. 11
12 11. Use the Xilinx SDK to download and run the executable ELF (.ELF) file on the MicroBlaze using the following steps. Right-click the mouse while the MAXREFDES12 C project is selected, choose the Run As menu, and then Run Configurations menu as shown below. 12
13 Next, double-click the mouse on the Xilinx C/C++ ELF menu. 13
14 Next, press the Search Project button. 14
15 Double-click on the MAXREFDES12.elf binary. 15
16 Verify the application is selected and press the Run button. Once the Debug/MAXREFDES12 configuration is set up once, you just need to press the Run button if you ever want to run the program again. At this point, the application is running on the MicroBlaze. The LEDs LD7 LD0 on the Nexys 3 development board indicate the voltage levels of the digital input channels IN8 IN0, respectively. LED ON indicates a high-voltage input, LED OFF indicates a low-voltage input. At the same time, the 7-segment LED panel on the Nexys 3 development board displays the MAX bit register value in HEX format. Change the digital input voltages to verify the register value follows the changes properly. 16
17 5. Code Documentation Code documentation can be found at: C:\...\RD12V01_00\RD12_NEXYS3_V01_00\Code_Documentation\ To view the code documentation in HTML format with a browser, open the MainPage.html file. To view the code documentation in.pdf format with a PDF reader, open the MAXREFDES12_Code_Documentation.pdf file. 17
18 6. Appendix A: Project Structure and Key Filenames 7. Trademarks Eclipse is a trademark of Eclipse Foundation, Inc. ISE is a registered trademark of Xilinx, Inc. MicroBlaze is a trademark of Xilinx, Inc. Nexys is a trademark of Digilent Inc. Pmod is a trademark of Digilent Inc. Spartan is a registered trademark of Xilinx, Inc. Windows is a registered trademark and registered service mark and Windows XP is a registered trademark of Microsoft Corporation. Xilinx is a registered trademark and registered service mark of Xilinx, Inc. 18
19 8. Revision History REVISION REVISION PAGES DESCRIPTION NUMBER DATE CHANGED 0 4/13 Initial release 19
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Guide Opal Kelly XEM6110 Thank You! Thank you for purchasing an Opal Kelly PCI Express product. We ve included this printed guide to help you start using the module and FrontPanel software. Much more documentation