AC 97 SoundMAX Codec AD1981BL

Transcription

1 AC COPATIBLE FEATURES S/PDIF output, 20-bit data format, supporting 48 khz and 44. khz sample rates Integrated stereo headphone amplifier Variable sample rate audio External audio power-down control >90 db dynamic range Stereo full-duplex codec 20-bit PC DAC 3 analog line-level stereo inputs for line-in, AUX, and CD ono line-level phone input Dual IC input with built-in programmable preamplifier High quality CD input with ground sense ono output for speakerphone or internal speaker power management support 48-lead LQFP package, Pb-free available FUNCTIONAL BLOCK DIAGRA V REFOUT V REF AC 97 SoundAX Codec AD98BL ENHANCED FEATURES Stereo IC preamplifier support Built-in digital equalizer function for optimized speaker sound Full-duplex variable sample rates from 7040 Hz to 48 khz with Hz resolution Jack sense pins for automatic output switching Software-programmed VREFOUT output for biasing microphone and external power amplifier Low power 3.3 V operation for analog and digital supplies ultiple codec configuration options XTL_OUT XTL_IN SPDIF AD98BL G VOLTAGE REFERENCE IC IC2 PHONE_IN CD_L CD_GND CD_R AUX_L AUX_R LINE_IN_L LINE_IN_R ONO_OUT S CD DIFF AP A IX IC PREAP G G 2CIC RECORD SELECTOR G G G G PC L/R ADC RATE 6-BIT Σ- ADC 6-BIT Σ- ADC 6-BIT Σ- ADC 6-BIT Σ- ADC CODEC CORE PLL ADC AND DAC SLOT LOGIC SPDIF TX AC '97 INTERFACE ID0 ID RESET SYNC BIT_CLK HP_OUT_L LINE_OUT_L LINE_OUT_R HP Z Z A A A OUTPUT SELECTOR GA GA GA GA GA GA GA GA GA GA G = GAIN A = ATTENUATION = UTE Z = HIGH Z 20-BIT Σ- DAC 20-BIT Σ- DAC PC FRONT DAC RATE BYPASS BYPASS EQ EQ EQ CORE STORAGE AC '97 CONTROL REGISTERS SDATA_OUT SDATA_IN HP_OUT_R HP A ANALOG IXING CONTROL LOGIC EAPD JS0 JS EAPD Figure. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, A , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Specifications... 3 Test Conditions... 3 General Specifications... 3 Power-Down States... 5 Timing Parameters... 5 Absolute aximum Ratings... 9 Environmental Conditions... 9 Pin Configuration and Function Descriptions... 0 Indexed Control Registers... 2 Control Register Details... 3 Reset Register... 3 aster Volume Register... 3 Headphone Volume Register... 4 ono Volume Register... 5 Phone Volume Register... 5 IC Volume Register... 6 Line-In Volume Register... 6 CD Volume Register... 7 AUX Volume Register... 7 PC-Out Volume Register... 8 Record Select Control Register... 9 Record Gain Register... 9 General-Purpose Register Power-Down Control/Status Register... 2 Extended Audio ID Register Extended Audio Status and Control Register PC Front DAC Rate Register PC ADC Rate Register SPDIF Control Register EQ Control Register EQ Data Register ixer ADC, Input Gain Register Jack Sense/Audio Interrupt/Status Register Serial Configuration Register iscellaneous Control Bit Register Vendor ID Registers... 3 Outline Dimensions Ordering Guide REVISION HISTORY /05 Rev. 0 to Rev. A Updated Format...Universal Changes to Ordering Guide /04 Revision 0: Initial Version Rev. A Page 2 of 32

3 SPECIFICATIONS TEST CONDITIONS Standard test conditions, unless otherwise noted. Table. Parameter Test Condition Temperature 25 C Digital Supply (DVDD) 3.3 V Analog Supply (AVDD) 3.3 V Sample Rate (fs) 48 khz Input Signal 008 Hz Analog Output Pass Band 20 Hz to 20 khz DAC Calibrated 3 db Attenuation Relative to Full Scale 0 db Input 0 kω Output Load (LINE_OUT) 32 Ω Output Load (HP_OUT) ADC Calibrated 0 db Gain Input 3.0 db Relative to Full Scale GENERAL SPECIFICATIONS Table 2. Parameter in Typ ax Unit ANALOG INPUT Input Voltage (RS Values Assume Sine Wave Input) LINE_IN, AUX, CD, PHONE_IN V rms 2.0 V p-p IC_IN with 20 db Gain V rms 0.2 V p-p IC_IN with 0 db Gain.707 V rms 2.0 V p-p Input Impedance 20 kω Input Capacitance pf ASTER VOLUE Step Size (0 db to 46.5 db): LINE_OUT_L, LINE_OUT_R.5 db Output Attenuation Range 46.5 db Step Size (0 db to 46.5 db): ONO_OUT.5 db Output Attenuation Range 46.5 db Step Size (0 db to 46.5 db): HP_OUT_R, HP_OUT_L.5 db Output Attenuation Range Span 46.5 db ute Attenuation of 0 db Fundamental 80 db PROGRAABLE GAIN APLIFIER ADC Step Size (0 db to 22.5 db).5 db PGA Gain Range 22.5 db ANALOG IXER INPUT GAIN/APLIFIERS/ATTENUATORS Signal-to-Noise Ratio (SNR) CD to LINE_OUT 90 db Other to LINE_OUT 90 db Rev. A Page 3 of 32

4 Parameter in Typ ax Unit Step Size (+2 db to 34.5 db) (All Steps Tested): IC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC.5 db Input Gain/Attenuation Range: IC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC 46.5 db DIGITAL DECIATION AND INTERPOLATION FILTERS Pass Band fs Hz Pass-Band Ripple ±0.09 db Transition Band 0.4 fs 0.6 fs Hz Stop Band 0.6 fs Hz Stop-Band Rejection 74 db Group Delay 6/fS sec Group Delay Variation over Pass Band 0 µs ANALOG-TO-DIGITAL CONVERTERS Resolution 6 Bits Total Harmonic Distortion (THD) 87 db Dynamic Range ( 60 db Input THD + N Referenced to Full Scale, A-Weighted) db Signal-to-Intermodulation Distortion CCIF ethod) 85 db ADC Crosstalk Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) 80 db Line_In to Other db Gain Error 2 (Full-Scale Span Relative to Nominal Input Voltage) ±0 % Interchannel Gain ismatch (Difference of Gain Errors) ± 0.5 db ADC Offset Error ±5 mv DIGITAL-TO-ANALOG CONVERTERS Resolution 20 Bits Total Harmonic Distortion (THD) LINE_OUT 88 db Total Harmonic Distortion (THD) HP_OUT 8 db Dynamic Range ( 60 db Input THD + N Referenced to Full Scale, A-Weighted) db Signal-to-Intermodulation Distortion (CCIF ethod) 00 db Gain Error 2 (Output FS Voltage Relative to Nominal Output FS Voltage) ±0 % Interchannel Gain ismatch (Difference of Gain Errors) ±0.7 db DAC Crosstalk (Input L, Zero R, easure R_OUT; Input R, Zero L, easure 80 db L_OUT) ANALOG OUTPUT Full-Scale Output Voltage; LINE_OUT and ONO_OUT V rms 2.0 V p-p Output Impedance 800 Ω External Load Impedance 0 kω Output Capacitance 5 pf External Load Capacitance 00 pf Full-Scale Output Voltage; HP_OUT (0 db Gain) V rms External Load Impedance 32 Ω VREF V VREFOUT 2.25 V VREFOUT Current Drive 5 ma ute Click (uted Output inus Unmuted idscale DAC Output) ±5 mv STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH): Digital Inputs 0.65 DVDD V Low Level Input Voltage (VIL) 0.35 DVDD V High Level Output Voltage (VOH), IOH = 2 ma 0.9 DVDD V Rev. A Page 4 of 32

5 Parameter in Typ ax Unit Low Level Output Voltage (VOL), IOL = 2 ma 0. DVDD V Input Leakage Current 0 +0 µa Output Leakage Current 0 +0 µa POWER SUPPLY Power Supply Range (AVDD and DVDD) V Power Dissipation 2.87 mw Analog Supply Current 3.3 V (AVDD) 39 ma Digital Supply Current 3.3 V (DVDD) 48 ma Power Supply Rejection (00 mv p-p Signal at khz) 40 db (At Both Analog and Digital Supply Pins, Both ADCs and DACs) CLOCK SPECIFICATIONS Input Clock Frequency Hz Recommended Clock Duty Cycle % Guaranteed but not tested. 2 easurements reflect main ADC. POWER-DOWN STATES Values presented with VREFOUT not loaded. Table 3. Parameter Set Bits DVDD Typ AVDD Typ Unit Fully Active No Bits Value ma ADC PR ma DAC PR ma ADC + DAC PR, PR ma ixer PR ma ADC + ixer PR2, PR ma DAC + ixer PR2, PR ma ADC + DAC + ixer PR2, PR, PR ma Standby PR5, PR4, PR3, PR2, PR, PR0 0 0 ma Headphone Standby PR ma TIING PARAETERS Guaranteed over operating temperature range. Table 4. Parameter Symbol in Typ ax Unit RESET Active Low Pulse Width trst_low.0 ms RESET Inactive to BIT_CLK Start-Up Delay trst2clk 62.8 ns SYNC Active High Pulse Width tsync_high.3 µs SYNC Low Pulse Width tsync_low 9.5 µs SYNC Inactive to BIT_CLK Start-Up Delay tsync2clk 62.8 ns BIT_CLK Frequency Hz BIT_CLK Frequency Accuracy ± ppm BIT_CLK Period tclk_period 8.4 ns BIT_CLK Output Jitter, ps BIT_CLK High Pulse Width tclk_high ns BIT_CLK Low Pulse Width tclk_low ns SYNC Frequency 48.0 khz Rev. A Page 5 of 32

6 Parameter Symbol in Typ ax Unit SYNC Period tsync_period 20.8 ms Setup to Falling Edge of BIT_CLK tsetup ns Hold from Falling Edge of BIT_CLK thold 5 ns BIT_CLK Rise Time triseclk ns BIT_CLK Fall Time tfallclk ns SYNC Rise Time trisesync ns SYNC Fall Time tfallsync ns SDATA_IN Rise Time trisedin ns SDATA_IN Fall Time tfalldin ns SDATA_OUT Rise Time trisedout ns SDATA_OUT Fall Time tfalldout ns End of Slot 2 to BIT_CLK, SDATA_IN Low ts2_pdown 0.0 ms Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) tsetup2rst 5 ns Rising Edge of RESET to High Z Delay toff 25 ns Propagation Delay 5 ns RESET Rise Time 50 ns Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid 5 ns Guaranteed but not tested. 2 Output jitter is directly dependent on crystal input jitter. 3 aximum jitter specification is for noncrystal operation only. Crystal operation maximum is much lower. t RST_LOW t RST2CLK RESET BIT_CLK t TRI2ACTV SDATA_IN t TRI2ACTV Figure 2. Cold Reset Timing (Codec is Supplying the BIT_CLK Signal) t SYNC_HIGH t SYNC2CLK SYNC BIT_CLK Figure 3. Warm Reset Timing Rev. A Page 6 of 32

7 t CLK_LOW BIT_CLK t CLK_HIGH t CLK_PERIOD t SYNC_LOW SYNC t SYNC_HIGH tsync_period Figure 4. Clock Timing BIT_CLK t RISECLK t FALLCLK SYNC t RISESYNC t FALLSYNC SDATA_IN t RISEDIN t FALLDIN SDATA_OUT t RISEDOUT t FALLDOUT Figure 5. Signal Rise and Fall Times SYNC SLOT SLOT 2 BIT_CLK SDATA_OUT WRITE TO 0x20 DATA PR4 t S2_PDOWN SDATA_IN BIT_CLK NOT TO SCALE Figure 6. AC-Link Low Power ode Timing Rev. A Page 7 of 32

8 t CO t SETUP BIT_CLK V IH V IL SDATA_OUT SDATA_IN V OH SYNC V OL t HOLD Figure 7. AC-Link Low Power ode Timing, SYNC and BIT_CLK Chopped RESET SDATA_OUT SDATA_IN, BIT_CLK, EAPD, SPDIF_OUT AND DIGITAL I/O t OFF t SETUP2RST HIGH Z Figure 8. ATE Test ode Rev. A Page 8 of 32

9 ABSOLUTE AXIU RATINGS TA = 25 C, unless otherwise noted. Table 5. Parameter Power Supplies Digital (DVDD) Analog (AVDD) Input Current (Except Supply Pins) Signals Pins Digital Input Voltage Analog Input Voltage Ambient Temperature Range (Operating) Rating 0.3 V to +3.6 V 0.3 V to +6.0 V ±0 ma 0.3 V to DVDD V 0.3 V to AVDD V 0 C to 70 C Stresses greater than those listed under Absolute aximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ENVIRONENTAL CONDITIONS Ambient Temperature Rating (LQFP Package) TCASE = Case Temperature in C PD = Power Dissipation in W θja Thermal Resistance (Junction to Ambient) θjc Thermal Resistance (Junction to Case) Table 6. Thermal Resistance Package θja θjc LQFP 50. C/W 7.8 C/W ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A Page 9 of 32

10 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SPDIF PHONE_IN EAPD ID ID0 AV SS 3 AV DD 3 NC HP_OUT_R AV SS 2 HP_OUT_L AV DD 2 ONO_OUT DV DD 36 LINE_OUT_R XTL_IN 2 35 LINE_OUT_L XTL_OUT 3 34 AV DD 4 DV SS 4 33 AV SS 4 SDATA_OUT BIT_CLK DV SS AD98BL TOP VIEW (Not to Scale) AFILT4 AFILT3 AFILT2 SDATA_IN 8 29 AFILT DV DD V REFOUT SYNC 0 RESET NC V REF AV SS AV DD AUX_L NC = NO CONNECT AUX_R JS JS0 CD_L CD_GND_REF CD_R IC IC2 LINE_IN_L LINE_IN_R Figure Lead LQFP Pin Configuration Table 7. Pin Function Descriptions Pin No. nemonic I/O Description DIGITAL I/O 2 XTL_IN I Crystal Input ( Hz) or External Clock Input. 3 XTL_OUT O Crystal Output. 5 SDATA_OUT I AC-Link Serial Data Output, AD98BL Data Input Stream. 6 BIT_CLK O/I AC-Link Bit Clock Output (2.288 Hz) or Bit Clock Input, if Secondary ode Selected. 8 SDATA_IN O AC-Link Serial Data Input, AD98BL Data Output Stream. 0 SYNC I AC-Link Frame Sync. RESET I AC-Link Reset, AD98BL aster Hardware Reset. 48 SPDIF O S/PDIF Output. CHIP SELECTS 45 ID0 I Chip Select Input 0 (Active Low). This pin can also be used as the chain input from a secondary codec. 46 ID I Chip Select Input (Active Low). JACK SENSE AND EAPD 7 JS0 I Jack Sense 0 Input. 6 JS I Jack Sense Input. 47 EAPD O External Amp Power-Down Control. ANALOG I/O 3 PHONE_IN I Phone Input. ono input from telephony subsystem speaker phone or handset. 4 AUX_L I Auxiliary Input Left Channel. 5 AUX_R I Auxiliary Input Right Channel. 8 CD_L I CD Audio Left Channel. 9 CD_GND_REF I CD Audio Analog Ground Reference for Differential CD Input. 20 CD_ R I CD Audio Right Channel. 2 IC I icrophone Input (ono) or Left Channel when 2-Channel ode Selected (Stereo IC). Rev. A Page 0 of 32

11 Pin No. nemonic I/O Description 22 IC2 I icrophone 2 Input (ono) or Right Channel when 2-Channel ode Selected (Stereo IC). 23 LINE_IN_L I Line-In Left Channel. 24 LINE_IN_R I Line-In Right Channel. 35 LINE_OUT_L O Line-Out (Front) Left Channel. 36 LINE_OUT_R O Line-Out (Front) Right Channel. 37 ONO_OUT O onaural Output to Telephony Subsystem Speaker Phone. 39 HP_OUT_L O Headphone Left-Channel Output. 4 HP_OUT_R O Headphone Right-Channel Output. FILTER/REFERENCE 2 27 VREF O Voltage Reference Filter. 28 VREFOUT O Voltage Reference Output 5 ma Drive (Intended for IC Bias and Power Amp Bias). 29 AFILT O Antialiasing Filter Capacitor ADC Right Channel. 30 AFILT2 O Antialiasing Filter Capacitor ADC Left Channel. 3 AFILT3 O Antialiasing Filter Capacitor ixer ADC Right Channel. 32 AFILT4 O Antialiasing Filter Capacitor ixer ADC Left Channel. POWER AND GROUND SIGNALS DVDD I Digital VDD, 3.3 V. 4 DVSS I Digital GND. 7 DVSS2 I Digital GND. 9 DVDD2 I Digital VDD, 3.3 V. 25 AVDD I Analog VDD, 3.3 V. 26 AVSS I Analog GND. 38 AVDD2 I Analog VDD, 3.3 V. 40 AVSS2 I Analog GND. 43 AVDD3 I Analog VDD, 3.3 V. 44 AVSS3 I Analog GND. 34 AVDD4 I Analog VDD, 3.3 V. 33 AVSS4 I Analog GND. NO CONNECTS 2 NC No Connect. 42 NC No Connect. These pins can also be used to select an external clock. See Table These signals are connected to resistors, capacitors, or specific voltages. Rev. A Page of 32

12 INDEXED CONTROL REGISTERS Table 8. Reg Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x00 Reset X SE4 SE3 SE2 SE SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID ID0 0x0090 0x02 0x04 0x06 0x0C aster Volume Headphone Volume ono Volume Phone Volume X X LV4 LV3 LV2 LV LV0 R X X RV4 RV3 RV2 RV RV0 0x8000 HP X X LHV4 LHV3 LHV2 LHV LHV0 R X X RHV4 RHV3 RHV2 RHV RHV0 0x8000 V X X X X X X X X X X V4 V3 V2 V V0 0x8000 PH X X X X X X X X X X PHV4 PHV3 PHV2 PHV PHV0 0x8008 0x0E IC Volume C X X X X X X X X 20 X CV4 CV3 CV2 CV CV0 0x8008 0x0 Line-In Volume LV X X LLV4 LLV3 LLV2 LLV LLV0 R X X RLV4 RLV3 RLV2 RLV RLV0 0x8808 0x2 CD Volume CV X X LCV4 LCV3 LCV2 LCV LCV0 R X X RCV4 RCV3 RCV2 RCV RCV0 0x8808 0x6 AUX Volume A X X LAV4 LAV3 LAV2 LAV LAV0 R X X RAV4 RAV3 RAV2 RAV RAV0 0x8808 0x8 0xA PC-Out Volume Record Select O X X LOV4 LOV3 LOV2 LOV LOV0 R X X ROV4 ROV3 ROV2 ROV ROV0 0x8808 X X X X X LS2 LS LS0 X X X X X RS2 RS RS0 0x0000 0xC Record Gain I X X X LI3 LI2 LI LI0 R X X X RI3 RI2 RI RI0 0x8000 0x20 0x26 0x28 0x2A 0x2C 0x32 0x3A General- Purpose Power-Down Ctrl/Stat Ext d Audio ID Ext d Audio Stat/Ctrl PC Front DAC Rate PC L/R ADC Rate SPDIF Control 0x60 EQ Ctrl EQ AD LBEN X X X X X X IX S LPBK X X X X X X X 0x0000 EAPD PR6 PR5 PR4 PR3 PR2 PR PR0 X X X X REF ANL DAC ADC 0x000X IDC IDC0 X X REVC REVC0 AAP X X X DSA DSA0 X SPDIF X VRAS 0xX605 VFORCE X X X X SPCV X X X X SPSA SPSA0 X SPDIF X VRA 0x0000 SRF5 SRF4 SRF3 SRF2 SRF SRF0 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF SRF0 0xBB80 SRA5 SRA4 SRA3 SRA2 SRA SRA0 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA SRA0 0xBB80 V X SPSR SPSR0 L CC6 CC5 CC4 CC3 CC2 CC CC0 PRE COPY /AUD PRO 0x2000 X X X X X X SY CHS BCA5 BCA4 BCA3 BCA2 BCA BCA0 0x8080 0x62 EQ Data CFD5 CFD4 CFD3 CFD2 CFD CFD0 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD CFD0 0x0000 0x64 ixer ADC, Volume X X X X LG3 LG2 LG LG0 R X X X RG3 RG2 RG RG0 0x8000 0x72 Jack Sense X X X JS T2 JS T JS T0 JS EQB 0x74 Serial Config SLOT 6 REG 2 REG REG 0 X X X CHEN X X X INTS X SPAL SPDZ SPLNK 0x700 0x76 isc Control DACZ X SPLT LODIS DA X FXE X AD 2CIC X AD VREFH VREFD BG BG0 0x0000 Bit PD ST 0x7C Vendor ID F7 F6 F5 F4 F3 F2 F F0 S7 S6 S5 S4 S3 S2 S S0 0x444 0x7E Vendor ID2 T7 T6 T5 T4 T3 T2 T T0 REV7 REV6 REV5 REV4 REV3 REV2 REV REV0 0x5374 All registers are not shown. Bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written. Zeros should be written to reserved bits. For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. JS0 EQB JS TR JS0 TR JS D JS0 D JS ST JS0 ST JS INT JS0 INT 0x0000 Rev. A Page 2 of 32

13 CONTROL REGISTER DETAILS RESET REGISTER Index 0x00 Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x00 Reset X SE4 SE3 SE2 SE SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID ID0 0x0090 X is a wild card, and has no effect on the value. Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 0x74, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement. ID[9:0] Identify Capability. The ID decodes the capabilities of AD98BL based on the functions listed in Table 9. Table 9. ID Bits Bit Function AD98B ID0 Dedicated IC PC in Channel 0 ID odem Line Codec Support 0 ID2 Bass and Treble Control 0 ID3 Simulated Stereo (ono to Stereo) 0 ID4 Headphone Out Support ID5 Loudness (Bass Boost) Support 0 ID6 8-Bit DAC Resolution 0 ID7 20-Bit DAC Resolution ID8 8-Bit ADC Resolution 0 ID9 20-Bit ADC Resolution 0 ASTER VOLUE REGISTER Index 0x02 This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each volume subregister contains five bits, generating 32 volume levels with 3 steps of.5 db each. Because AC 97 defines 6-bit volume registers, to maintain compatibility whenever the D5 or D3 bits are set to, their respective lower five volume bits are automatically set to by the codec logic. On readback, all lower five bits read s whenever these bits are set to. Refer to Table 2 for examples. Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x02 aster X X LV4 LV3 LV2 LV LV0 R X X RV4 RV3 RV2 RV RV0 0x8000 Volume For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Table 0. RV [4:0] Right aster Volume Control The least significant bit represents.5 db. This register controls the output from 0 db to a maximum attenuation of 46.5 db. R Right-Channel ute Once enabled by the SPLT bit in Register 0x76, this bit mutes the right channel separately from the bit. Otherwise, this bit always reads 0 and has no effect when set to. LV [4:0] Left aster Volume Control The least significant bit represents.5 db. This register controls the output from 0 db to a maximum attenuation of 46.5 db. aster Volume ute When this bit is set to, both the left and right channels are muted, unless the SPLT bit in Register 0x76 is set to, in which case this mute bit affects only the left channel. Rev. A Page 3 of 32

14 HEADPHONE VOLUE REGISTER Index 0x04 This register controls the headphone volume controls for both stereo channels and the mute bit. Each volume subregister contains five bits, generating 32 volume levels with 3 steps of.5 db each. Because AC 97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 or D3 bits are set to, their respective lower five volume bits are automatically set to by the codec logic. On readback, all lower five bits read s whenever these bits are set to. Refer to Table 2 for examples. Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x04 Headphone Volume HP X X LHV4 LHV3 LHV2 LHV LHV0 R X X RHV4 RHV3 RHV2 RHV RHV0 0x8000 For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Table. RHV [4:0] Right Headphone Volume Control The least significant bit represents.5 db. This register controls the output from 0 db to a maximum attenuation of 46.5 db. R Right-Channel ute Once enabled by the SPLT bit in Register 0x76, this bit mutes the right channel separately from the HP bit. Otherwise, this bit always reads 0 and has no effect when set to. LHV [4:0] Left Headphone Volume Control The least significant bit represents.5 db. This register controls the output from 0 db to a maximum attenuation of 46.5 db. HP Headphone Volume ute When this bit is set to, both the left and right channels are muted, unless the SPLT bit in Register 0x76 is set to, in which case this mute bit affects only the left channel. Table 2. Volume Settings for aster and Headphone Reg. 0x76 Control Bits aster Volume (0x02) and Headphone Volume (0x04) Left-Channel Volume D [3:8] Right-Channel Volume D [5:0] SPLT D5 Write Readback Function D7 Write Readback Function db Gain X db Gain db Gain X db Gain db Gain X db Gain 0 0 X XXXX db Gain X X XXXX db Gain 0 XX XXXX XX XXXX db Gain, uted X XX XXXX XX XXXX db Gain, uted 0 X XXXX db Gain XX XXXX XX XXXX db Gain, Right Only uted XX XXXX XX XXXX db Gain, Left Only uted 0 XX XXXX XX XXXX 46.5 db Gain XX XXXX XX XXXX db Gain, Left uted XX XXXX XX XXXX db Gain, Right uted For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. X is a wild card, and has no effect on the value. Rev. A Page 4 of 32

15 ONO VOLUE REGISTER Index 0x06 This register controls the mono output volume and mute bit. The volume register contains five bits, generating 32 volume levels with 3 steps of.5 db each. Because AC 97 defines 6-bit volume registers, to maintain compatibility, whenever the D5 bit is set to, their respective lower five volume bits are automatically set to by the codec logic. On readback, all lower five bits read s whenever this bit is set to. Refer to Table 4 for examples. Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x06 ono Volume V X X X X X X X X X X V4 V3 V2 V V0 0x8000 All registers are not shown, and bits containing an X are assumed to be reserved. Table 3. V [4:0] ono Volume Control The least significant bit represents.5 db. This register controls the output from 0 db to a maximum attenuation of 46.5 db. V ono Volume ute When this bit is set to, the channel is muted. Table 4. Volume Settings for ono Control Bits D [4:0] for ono (0x06) D5 Write Readback Function db Gain db Gain db Gain X XXXX X XXXX db Gain, uted An X is a wild card, and has no effect on the value. PHONE VOLUE REGISTER Index 0x0C Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x0C Phone Volume PH X X X X X X X X X X PHV4 PHV3 PHV2 PHV PHV0 0x8008 All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 7 for examples. Table 5. PHV [4:0] Phone Volume Allows setting the phone volume attenuator in 32 volume levels with 3 steps of.5 db each. The LSB represents.5 db, and the gain range is +2 db to 34.5 db. The default value is 0 db, with the mute bit enabled. PH Phone ute When this bit is set to, the phone channel is muted. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 7 for examples. Rev. A Page 5 of 32

16 IC VOLUE REGISTER Index 0x0E Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x0E IC Volume C X X X X X X X X 20 X CV4 CV3 CV2 CV CV0 0x8008 All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 7 for examples. Table 6. CV [4:0] IC Volume Gain Allows setting the phone volume attenuator in 32 volume levels with 3 steps of.5 db each. The LSB represents.5 db, and the gain range is +2 db to 34.5 db. The default value is 0 db, with the mute bit enabled. 20 IC Gain Boost This bit allows setting additional IC gain to increase the microphone sensitivity. The nominal gain boost by default is 20 db; however, Bits D0 and D (BG [:0]) on the miscellaneous control bits register (0x76) allow changing the gain boost to 0 db or 30 db, if necessary. 0 = Disabled; Gain = 0 db = Enabled; Default Gain = 20 db (see Register 0x76, Bits D0, D) C IC ute When this bit is set to, the IC channel is muted. Table 7. Volume Settings for Phone and IC Control Bits D [4:0] Phone (0x0C) and IC (0x0E) D5 Write Readback Function db Gain db Gain db Gain X XXXX X XXXX db Gain, uted X is a wild card, and has no effect on the value. LINE-IN VOLUE REGISTER Index 0x0 Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x0 Line-In Volume LV X X LLV4 LLV3 LLV2 LLV LLV0 R X X RLV4 RLV3 RLV2 RLV RLV0 0x8808 For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Ta ble 22 for examples. Table 8. RLV [4:0] Line-In Volume Right Allows setting the line-in right-channel attenuator in 32 volume levels. The LSB represents.5 db, and the range is +2 db to 34.5 db. The default value is 0 db, mute enabled. R Right-Channel ute Once enabled by the SPLT bit in Register 0x76, this bit mutes the right channel separately from the L bit. Otherwise, this bit always reads 0 and has no effect when set to. LLV [4:0] Line-In Volume Left Allows setting the line-in left-channel attenuator in 32 volume levels. The LSB represents.5 db, and the range is +2 db to 34.5 db. The default value is 0 db, mute enabled. LV Line-In ute When this bit is set to, both the left and right channels are muted, unless the SPLT bit in Register 0x76 is set to, in which case this mute bit affects only the left channel. Rev. A Page 6 of 32

17 CD VOLUE REGISTER Index 0x2 Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x2 CD Volume CV X X LCV4 LCV3 LCV2 LCV LCV0 R X X RCV4 RCV3 RCV2 RCV RCV0 0x8808 For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 22 for examples. Table 9. RCV [4:0] Right CD Volume Allows setting the CD right-channel attenuator in 32 volume levels. The LSB represents.5 db, and the gain range is +2 db to 34.5 db. The default value is 0 db, mute enabled. R Right-Channel ute Once enabled by the SPLT bit in Register 0x76, this bit mutes the right channel separately from the CV bit. Otherwise, this bit always reads 0 and has no affect when set to. LCV [4:0] Left CD Volume Allows setting the CD left-channel attenuator in 32 volume levels. The LSB represents.5 db, and the gain range is +2 db to 34.5 db. The default value is 0 db, mute enabled. CV CD Volume ute When this bit is set to, both the left and right channels are muted, unless the SPLT bit in Register 0x76 is set to, in which case this mute bit affects only the left channel. AUX VOLUE REGISTER Index 0x6 Reg No. Name D5 D4 D3 D2 D D D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x6 AUX Volume A X X LAV4 LAV3 LAV2 LAV LAV0 R X X RAV4 RAV3 RAV2 RAV RAV0 0x8808 For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Ta ble 22 for examples. Table 20. RAV [4:0] Right AUX Volume Allows setting the AUX right-channel attenuator in 32 volume levels. The LSB represents.5 db, and the gain range is +2 db to 34.5 db. The default value is 0 db, mute enabled. R Right-Channel ute Once enabled by the SPLT bit in Register 0x76, this bit mutes the right channel separately from the A bit. Otherwise, this bit always reads 0 and has no affect when set to. LAV [4:0] Left AUX Volume Allows setting the AUX left-channel attenuator in 32 volume levels. The LSB represents.5 db, and the gain range is +2 db to 34.5 db. The default value is 0 db, mute enabled. A AUX Volume ute When this bit is set to, both the left and right channels are muted, unless the SPLT bit in Register 0x76 is set to, in which case this mute bit affects only the left channel. Rev. A Page 7 of 32

18 PC-OUT VOLUE REGISTER Index 0x8 Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x8 PC-Out Volume O X X LOV4 LOV3 LOV2 LOV LOV0 R X X ROV4 ROV3 ROV2 ROV ROV0 0x8808 For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Ta ble 22 for examples. Table 2. ROV [4:0] Right PC-Out Volume Allows setting the PC right-channel attenuator in 32 volume levels. The LSB represents.5 db, and the range is +2 db to 34.5 db. The default value is 0 db, mute enabled. R Right-Channel ute Once enabled by the SPLT bit in Register 0x76, this bit mutes the right channel separately from the O bit. Otherwise, this bit always reads 0 and has no effect when set to. LOV [4:0] Left PC-Out Volume Allows setting the PC left-channel attenuator in 32 volume levels. The LSB represents.5 db, and the range is +2 db to 34.5 db. The default value is 0 db, mute enabled. O PC-Out Volume ute When this bit is set to, both the left and right channels are muted unless the SPLT bit in Register 0x76 is set to, in which case this mute bit affects only the left channel. Table 22. Volume Settings for Line-In, CD Volume, AUX, and PC-Out Control Bits Reg. 0x76 Line-In (0x0), CD (0x2), AUX (0x6), and PC-Out (0x8) Left-Channel Volume D [2:8] Right-Channel Volume D [4:0] SPLT D5 Write Readback Function D7 Write Readback Function db Gain X db Gain db Gain X db Gain db Gain X 34.5 db Gain 0 X XXXX X XXXX db Gain, uted X X XXXX X XXXX db Gain, uted db Gain X XXXX X XXXX db Gain, Left Only uted X XXXX X XXXX db Gain, Left uted X XXXX X XXXX db Gain, Right Only uted db Gain X XXXX X XXXX db Gain, Right uted For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. X is a wild card, and has no effect on the value. Rev. A Page 8 of 32

19 RECORD SELECT CONTROL REGISTER Index 0xA Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0xA Record Select X X X X X LS2 LS LS0 X X X X X RS2 RS RS0 0x0000 Used to select the record source independently for right and left. The default value is 0x0000, which corresponds to IC In. Refer to Table 24 for examples. All registers are not shown, and bits containing an X are assumed to be reserved. Table 23. Bit RS [2:0] LS [2:0] Function Right Record Select Left Record Select Table 24. Settings for Record Select Control LS [0:8] Left Record Source RS [2:0] Right Record Source 000 IC 000 IC 00 CD_L 00 CD_R 00 uted 00 uted 0 AUX_L 0 AUX_R 00 LINE_IN_L 00 LINE_IN_R 0 Stereo ix (L) 0 Stereo ix (R) 0 ono ix 0 ono ix PHONE_IN PHONE_IN RECORD GAIN REGISTER Index 0xC Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0xC Record Gain I X X X LI3 LI2 LI LI0 R X X X RI3 RI2 RI RI0 0x8000 For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 24 for examples. Table 25. RI [3:0] Right Input ixer Gain Each LSB represents.5 db, 0000 = 0 db, and the gain range is 0 db to 22.5 db. Control R Right-Channel ute Once enabled by the SPLT bit in Register 0x76, this bit mutes the right channel separately from the I bit. Otherwise, this bit always reads 0 and has no affect when set to. LI [3:0] Left Input ixer Gain Each LSB represents.5 db, 0000 = 0 db, and the gain range is 0 db to 22.5 db. Control I Input ute When this bit is set to, both the left and right channels are muted, unless the SPLT bit in Register 0x76 is set to, in which case this mute bit affects only the left channel. Rev. A Page 9 of 32

20 Table 26. Settings for Record Gain Register Reg. 0x76 Control Bits Record Gain (Channel) Left-Channel Input ixer D [:8] Right-Channel Input ixer D [3:0] SPLT D5 Write Readback Function D7 Write Readback Function db Gain X 22.5 db Gain db Gain X db Gain 0 XXXX XXXX db Gain, uted X XXXX XXXX db Gain, uted db Gain XXXX XXXX db Gain, Right Only uted XXXX XXXX db Gain, Left Only uted db Gain XXXX XXXX db Gain, Left uted XXXX XXXX db Gain, Right uted For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. X is a wild card, and has no effect on the value. GENERAL-PURPOSE REGISTER Index 0x20 Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x20 General-Purpose X X X X X X IX S LPBK X X X X X X X 0x0000 This register should be read before writing to generate a mask for only the bit(s) that need to be changed. All registers are not shown, and bits containing an X are assumed to be reserved. Table 27. LPBK Loopback Control ADC/DAC Digital Loopback ode. 0 = No Loopback (default). = Loopback PC Digital Data from ADC Output to DAC. S IC Select Selects mono IC input. 0 = Select IC. = Select IC2. See the 2CIC bit in Register 0x76 to enable stereo microphone recording. IX ono Output Select Selects mono output audio source. 0 = ixer ono Output (reset default). = IC Channel. Rev. A Page 20 of 32

21 POWER-DOWN CONTROL/STATUS REGISTER Index 0x26 Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x26 Power-Down Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR PR0 X X X X REF ANL DAC ADC 0x000X The ready bits are read-only; writing to REF, ANL, DAC, ADC has no effect. These bits indicate the status for the AD98BL subsections. If the bit is a, that subsection is ready. Ready is defined as the subsection able to perform in its nominal state. All registers are not shown, and bits containing an X are assumed to be reserved. Table 28. ADC ADC Sections Ready to Transmit Data. DAC DAC Sections Ready to Accept Data. ANL Analog Amplifiers, Attenuators, and ixers Ready. REF Voltage References, VREF and VREFOUT, Up to Nominal Level. PR [6:0] EAPD Codec Power- Down odes External Audio Power-Down Control The first three bits are to be used individually rather than in combination with each other. PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is powered up. PR5 has no effect unless all ADCs, DACs, and the ac-link are powered down. The reference and the mixer can be either powered up or powered down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple codec systems, the master codec s PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec, if the master s PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5. Controls the state of the EAPD pin. EAPD = 0 sets the EAPD pin low, enabling an external power amplifier (reset default). EAPD = sets the EAPD pin high, shutting the external power amplifier off. Table 29. Power-Down State Set Bits PR [6:0] ADCs and Input UX Power-Down PR0 [ ] DACs Power-Down PR [ ] Analog ixer Power-Down (VREF and VREFOUT On) PR, PR2 [000 00] Analog ixer Power-Down (VREF and VREFOUT Off) PR0, PR, PR3 [000 0] AC-Link Interface Power-Down PR4 [ ] Internal Clocks Disabled PR0, PR, PR4, PR5 [0 00] ADC and DAC Power-Down PR0, PR [000 00] VREF Standby ode PR0, PR, PR2, PR4, PR5 [0 0] Total Power-Down PR0, PR, PR2, PR3, PR4, PR5, PR6 [ ] Headphone Amp Power-In Standby PR6 [ ] Rev. A Page 2 of 32

22 EXTENDED AUDIO ID REGISTER Index 0x28 Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x28 Ext d Audio ID IDC IDC0 X X REVC REVC0 AAP X X X DSA DSA0 X SPDIF X VRAS 0xX605 The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates that one or more of the extended audio features are supported. All registers are not shown, and bits containing an X are assumed to be reserved. Table 30. VRAS Variable Rate PC Audio This bit returns a when Read To indicates that the variable rate PC audio is supported. Support (Read-Only) SPDIF SPDIF Support (Read-Only) This bit returns a when Read To indicates that the SPDIF transmitter is supported (IEC958). This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled; therefore, this bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is actually enabled. DSA [:0] DAC Slot Assignments (Read/Write) Reset default = DACs, 2 = 3 and 4. 0 DACs, 2 = 7 and 8. 0 DACs, 2 = 6 and 9. Reserved. This bit returns a when read to indicate that slot/dac mappings based on the codec ID are supported. AAP Slot DAC appings Based on Codec ID (Read-Only) REVC [:0] AC 97 Revision Compliance REVC [:0] = 0 indicates that the codec is AC 97 revision 2.2-compliant (read-only). IDC [:0] Indicates Codec 00 = Primary. Configuration (Read-Only) 0, 0, = Secondary. EXTENDED AUDIO STATUS AND CONTROL REGISTER Index 0x2A Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x2A Ext d Audio Stat/Ctrl VFORCE X X X X SPCV X X X X SPSA SPSA0 X SPDIF X VRA 0x0000 The extended audio status and control register is a read/write register that provides status and control of the extended audio features. All registers are not shown, and bits containing an X are assumed to be reserved. Table 3. VRA SPDIF SPSA [:0] Variable Rate Audio (Read/Write) SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write) SPDIF Slot Assignment Bits (Read/Write) VRA = 0 sets the fixed sample rate audio to 48 khz (reset default). VRA = enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling). SPDIF = enables the SPDIF transmitter. SPDIF = 0 disables the SPDIF transmitter (default). This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit returns a low, indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter is enabled. These bits control the SPDIF slot assignment and respective defaults, depending on the codec ID configuration. Rev. A Page 22 of 32

23 SPCV SPDIF Configuration Valid (Read-Only) This bit indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status. SPCV = 0 indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported). SPCV = indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (supported). VFORCE Validity Force Bit (Reset Default = 0) When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be controlled by the V bit (D5) in Register 0x3A (SPDIF control register). VFORCE = 0 and V = 0; the validity bit is managed by the codec error detection logic. VFORCE = 0 and V = ; the validity bit is forced high, indicating the subframe data is invalid. VFORCE = and V = 0; the validity bit is forced low, indicating the subframe data is valid. VFORCE = and V = ; the validity bit is forced high, indicating the subframe data is invalid. Table 32. AC AAP-Compliant Default SPDIF Slot Assignments Codec ID Function SPSA = 00 SPSA = 0 SPSA = 0 SPSA = 00 2-Channel Primary w/spdif 3 and 4 7 and 8 (default) 6 and 9 0 and 00 4-Channel Primary w/spdif 3 and 4 7 and 8 6 and 9 (default) 0 and 00 6-Channel Primary w/spdif 3 and 4 7 and 8 6 and 9 0 and (default) 0 +2-Channel Secondary w/spdif 3 and 4 7 and 8 6 and 9 (default) 0 +4-Channel Secondary w/spdif 3 and 4 7 and 8 6 and 9 0 and (default) 0 +2-Channel Secondary w/spdif 3 and 4 7 and 8 6 and 9 (default) 0 +4-Channel Secondary w/spdif 3 and 4 7 and 8 6 and 9 0 and (default) +2-Channel Secondary w/spdif 3 and 4 7 and 8 6 and 9 0 and (default) PC FRONT DAC RATE REGISTER Index 0x2C Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x2C PC Front DAC Rate SRF5 SRF4 SRF3 SRF2 SRF SRF0 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF SRF0 0xBB80 This read/write sample rate control register contains a 6-bit unsigned value, representing the rate of operation in Hz. Table 33. SRF [5:0] Sample Rate The sampling frequency range is from 7 khz (0xB58) to 48 khz (0xBB80) in Hz increments. If 0 is written to VRA, the sample rate is reset to 48 khz. PC ADC RATE REGISTER Index 0x32 Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x32 PC L/R ADC Rate SRA5 SRA4 SRA3 SRA2 SRA SRA0 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA SRA0 0xBB80 This read/write sample rate control register contains a 6-bit unsigned value, representing the rate of operation in Hz. Table 34. SRA [5:0] Sample Rate The sampling frequency range is from 7 khz (0xB58) to 48 khz (0xBB80) in Hz increments. If 0 is written to VRA, the sample rate is reset to 48 khz. Rev. A Page 23 of 32

24 SPDIF CONTROL REGISTER Index 0x3A Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x3A SPDIF Control V X SPSR SPSR0 L CC6 CC5 CC4 CC3 CC2 CC CC0 PRE COPY AUD PRO 0x2000 Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the exception of V, this register should be written to only when the SPDIF transmitter is disabled (SPDIF bit in Register 0x2A is 0). This ensures that control and status information start up correctly at the beginning of SPDIF transmission. Table 35. PRO Professional = Professional use of channel status. 0 = Consumer. AUD Nonaudio = Data is non-pc format. 0 = Data is PC format. COPY Copyright = Copyright is asserted. 0 = Copyright is not asserted. PRE Pre-emphasis = Filter pre-emphasis is 50 µs/5 µs. 0 = Pre-emphasis is none. CC [6:0] Category Code Programmed according to IEC standards, or as appropriate. L Generation Level Programmed according to IEC standards, or as appropriate. SPSR [:0] SPDIF Transmit Sample Rate SPSR [:0] = 00: Transmit sample rate is 44. khz. SPSR [:0] = 0: Reserved. SPSR [:0] = 0: Transmit sample rate is 48 khz (reset default). SPSR [:0] = : Not supported. V Validity This bit affects the validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain connection during error or mute conditions. V = : Each SPDIF subframe (L + R) has Bit 28 set to. This tags both samples as invalid. V = 0: Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and for invalid data (error condition). When V = 0, asserting the VFORCE bit (D5) in Register 0x2A (Ext d Audio Stat/Ctrl) forces the validity flag low, marking both samples as valid. EQ CONTROL REGISTER Index 0x60 Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x60 EQ Ctrl EQ AD LBEN X X X X X X SY CHS BCA5 BCA4 BCA3 BCA2 BCA BCA0 0x8080 Register 0x60 is a read/write register that controls the equalizer functionality and data setup. This register contains the biquad and coefficient address pointer, which is used in conjunction with the EQ data register (0x78) to set up the equalizer coefficients. The reset default disables the equalizer function until the coefficients can be properly set up by the software and sets the symmetry bit to allow equal coefficients for left and right channels. All registers are not shown, and bits containing an X are assumed to be reserved. Table 36. BCA [5:0] Biquad and Coefficient Address Pointer biquad 0 coef a0 BCA[5:0] = 00 biquad 0 coef a BCA[5:0] = 000 biquad 0 coef a2 BCA[5:0] = 000 biquad 0 coef b BCA[5:0] = 00 biquad 0 coef b2 BCA[5:0] = 000 biquad coef a0 BCA[5:0] = biquad coef a BCA[5:0] = 0 Rev. A Page 24 of 32

25 biquad coef a2 BCA[5:0] = 00 biquad coef b BCA[5:0] = 0000 biquad coef b2 BCA[5:0] = 0000 biquad 2 coef a0 BCA[5:0] = 000 biquad 2 coef a BCA[5:0] = 0000 biquad 2 coef a2 BCA[5:0] = 000 biquad 2 coef b BCA[5:0] = 00 biquad 2 coef b2 BCA[5:0] = 000 biquad 3 coef a0 BCA[5:0] = 000 biquad 3 coef a BCA[5:0] = 000 biquad 3 coef a2 BCA[5:0] = 0000 biquad 3 coef b BCA[5:0] = 000 biquad 3 coef b2 BCA[5:0] = 00 biquad 4 coef a0 BCA[5:0] = 0 biquad 4 coef a BCA[5:0] = 00 biquad 4 coef a2 BCA[5:0] = 00 biquad 4 coef b BCA[5:0] = 000 biquad 4 coef b2 BCA[5:0] = 0000 biquad 5 coef a0 BCA[5:0] = 000 biquad 5 coef a BCA[5:0] = 00 biquad 5 coef a2 BCA[5:0] = 000 biquad 5 coef b BCA[5:0] = 00 biquad 5 coef b2 BCA[5:0] = 00 biquad 6 coef a0 BCA[5:0] = 00 biquad 6 coef a BCA[5:0] = 000 biquad 6 coef a2 BCA[5:0] = 0 biquad 6 coef b BCA[5:0] = 0 biquad 6 coef b2 BCA[5:0] = 00 CHS Channel Select CHS = 0 selects the left-channel coefficient s data block. CHS = selects the right-channel coefficient s data block. SY Symmetry When set to, this bit indicates that the left- and right-channel coefficients are equal. This shortens the coefficients setup sequence, because only the left-channel coefficients need to be addressed and set up. The right-channel coefficients are fetched from the left-channel memory. AD LBEN ixer ADC Loopback Enable Enables mixer ADC data to be summed into the PC stream. 0 = No loopback allowed (default). = Enable loopback. EQ Equalizer ute When set to, this bit disables the equalizer function (allows all data to pass through). The reset default sets this bit to, disabling the equalizer function until the biquad coefficients can be properly set. Rev. A Page 25 of 32

26 EQ DATA REGISTER Index 0x62 Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x62 EQ Data CFD5 CFD4 CFD3 CFD2 CFD CFD0 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD CFD0 0x0000 This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the BCA bits in the EQ Cntrl Register (0x60). Data is written to memory only if the EQ bit (Register 0x60, Bit 5) is asserted. Table 37. CFD [5:0] Coefficient Data The biquad coefficients are fixed-point format values with 6 bits of resolution. The CFD5 bit is the SB, and the CFD0 bit is the LSB. IXER ADC, INPUT GAIN REGISTER Index 0x64 Reg No. Name D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Default 0x64 ixer ADC, Volume X X X X LG3 LG2 LG LG0 R X X X RG3 RG2 RG RG0 0x8000 For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 39 for examples. Table 38. RG [3:0] Right ixer Gain Control This register controls the gain into the mixer ADC from 0 db to a maximum gain of 22.5 db. The least significant bit represents.5 db. R Right-Channel ute Once enabled by the SPLT bit in Register 0x76, this bit mutes the right channel separately from the X bit. Otherwise, this bit always reads 0 and has no affect when set to. LG [3:0] Left ixer Gain Control This register controls the gain into the mixer ADC, from 0 db to a maximum gain of 22.5 db. The least significant bit represents.5 db. X ixer Gain Register ute 0 = Unmuted. = uted (reset default). Table 39. Settings for ixer ADC, Input Gain Reg. 0x76 Control Bits ixer ADC, Input Gain (0x64) Left-Channel ixer Gain D [:8] Right-Channel ixer Gain D [3:0] SPLT D5 Write Readback Function D7 Write Readback Function db Gain X 22.5 db Gain db Gain X db Gain 0 XXXX XXXX db Gain, uted X XXXX XXXX db Gain, uted db Gain XXXX XXXX db Gain, Right Only uted XXXX XXXX db Gain, Left Only uted db Gain XXXX XXXX db Gain, Left uted XXXX XXXX db Gain, Right uted For AC 97 compatibility, Bit D7 (R) is available only by setting the SPLT bit, Register 0x76. The SPLT bit enables separate mute bits for the left and right channels. If SPLT is not set, the R bit has no effect. X is a wild card, and has no effect on the value. Rev. A Page 26 of 32