Anand Raghunathan

Transcription

1 ECE 695R: SYSTEM-ON-CHIP DESIGN Module 2: HW/SW Partitioning Lecture 2.13: HW/SW Co-Synthesis: Automatic Partitioning Anand Raghunathan Fall 2014, ME 1052, T Th 12:00PM-1:15PM 2014 Anand Raghunathan 1

2 Heuristic Approaches to HW/SW Partitioning ILP does not scale well with problem size (few tens of nodes in the task graph) Several heuristic algorithms have been used Kernighan-Lin graph partitioning Dynamic Programming Simulated Annealing Iterative Improvement Genetic Algorithms. 2

3 Heuristic Approaches to HW/SW Partitioning Hardware-oriented Start with maximum-hw solution, move functions to SW until execution time constraint is exceeded or implementation cost constraint is satisfied Software-oriented Start with full-sw solution, move functions to HW until execution time constraint is satisfied or implementation cost constraint is exceeded 3

4 Notable HW/SW Co-synthesis Systems COSYMA (TU Braunschweig) Software-oriented, starts with sequential program R. Ernst, J. Henkel, Th. Benner, W. Ye, U. Holtmann, D. Herrmann, M. Trawny, The COSYMA environment for hardware/software cosynthesis of small embedded systems, Microprocessors and Microsystems, Volume 20, Issue 3, May 1996, Pages ( K/2/4fd4715f43f871adb67f32ed927ccf08) Vulcan (Stanford) Hardware-oriented Gupta, R. K., Coelho, C. N., and De Micheli, G Synthesis and simulation of digital systems containing interacting hardware and software components. In Proceedings of the 29th ACM/IEEE Design Automation Conference, ( CHINOOK (U. Wash.) Focus on Interface Synthesis Chou, P., Ortega, R., and Borriello, G. Synthesis fo the hardware/software interface in microcontroller-based systems. In Proceedings of the 1992 IEEE/ACM international Conference on Computer-Aided Design, ( POLIS (UC Berkeley) Focus on formal specification model (CFSMs), manual partitioning with automatic HW/SW/interface generation POLIS: A Framework for Hardware-Software Co-design of Embedded Systems ( 4

5 Commercial Attempts at Automatic HW/SW Partitioning Research started in 1990s First wave of commercial efforts in early 2000s Synopsys Nimble compiler (2000) Proceler (2000) Microprocessor Report s 2001 Technology of the Year Award 5

6 Commercial Attempts at Automatic HW/SW Partitioning Recent efforts have focused on automatic implementation and integration of accelerator, leaving selection of functions to designer Synfora (spinoff from HP Labs, acquired by Synopsys) Impulse C Catapult C Altera C2H More when we talk about behavioral synthesis 6

7 7 Re-configurable Platforms: A driver for HW/SW Partitioning Numerous single-chip commercial devices with up and FPGA Triscend E5 (shown) Triscend A7 Atmel FPSLIC Xilinx Virtex II Pro Altera Excalibur Xilinx Zynq EPP (2010) Intel Stellarton (2011) Altera SoC FPGA (2013) Xilinx Zynq (2013) Effective HW/SW partitioning essential Configurable logic up and peripherals Cache/memory

8 Summary: Automatic HW/SW Partitioning 8 Automatic HW/SW partitioning has been researched extensively, but few commercial solutions exist Recent commercial efforts have focused on automation of hardware generation and interfacing process, with manual identification of functions to be accelerated

9 Lecture 2.14 (Application-specific Instruction Processors): Outline Application-specific Instruction Processors (ASIPs) ASIPs as a building block for SoCs ASIP design approaches Extensible Processors: A practical approach to ASIP design 9