ECE 448 Lecture 5. FPGA Devices
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1 ECE 448 Lecture 5 FPGA Devices George Mason University
2 Required reading Spartan-6 FPGA Configurable Logic Block: User Guide CLB Overview Slice Description 2
3 Recommended reading Highly recommended for the Wednesday lab section using Nexys 4 boards 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional Details 3
4 What is an FPGA? Configurable Logic Blocks Block RAMs Block RAMs I/O Blocks Block RAMs 4
5 Modern FPGA RAM blocks Multipliers/DSP units Logic Logic resources blocks (#Logic resources, #Multipliers/DSP units, #RAM_blocks) Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 5
6 Major FPGA Vendors SRAM-based FPGAs Xilinx, Inc. Altera Corp. ~ 51% of the market ~ 34% of the market (subsidiary of Intel since 2015) Lattice Semiconductor Atmel Achronix Tabula (went out of business in 2015) ~ 85% Flash & antifuse FPGAs Microsemi SoC Products Group (formerly Actel Corp.) Quick Logic Corp. 6
7 Xilinx u Primary products: FPGAs and the associated CAD software Programmable Logic Devices ISE Alliance and Foundation Series Design Software u Main headquarters in San Jose, CA u Fabless* Semiconductor and Software Company u UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996} u Seiko Epson (Japan) u TSMC (Taiwan) u Samsung (Korea) 7
8 Xilinx FPGA Families Technology Low-cost Mid-range Highperformance 220 nm Virtex 180 nm Spartan-II, Spartan-IIE 120/150 nm Virtex-II, Virtex-II Pro 90 nm Spartan-3 Virtex-4 65 nm Virtex-5 45 nm Spartan-6 40 nm Virtex-6 28 nm Ar<x-7 Kintex-7 Virtex-7
9 FPGA Family 9
10 Spartan-6 FPGA Family 10
11 Artix-7 FPGA Family 11
12 CLB Structure George Mason University
13 General structure of an FPGA Programmable interconnect Programmable logic blocks The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 13
14 Xilinx Spartan-6 & Artix-7 CLB 14
15 Row & Column Relationship Between CLBs & Slices 15
16 Basic Components of the Slice LUTs Storage Elements 16
17 Example of a 4-input LUT (Look-Up Table) (used in earlier families of FPGAs) x 1 x 2 x 3 x y x 1 x 2 x 3 x 4 LUT y x 1 x 2 x 3 x 4 x 1 x 2 x 3 x y Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs x 1 x 2 y y 17
18 LUT of Spartan-6 and Artix-7 18
19 19
20 Reset and Set Configurations No set or reset Synchronous set Synchronous reset Asynchronous set (preset) Asynchronous reset (clear) 20
21 Three Different Types of Slices in Spartan-6 50% 25% 25% 21
22 Two Different Types of Slices in Artix-7 22
23 SLICEX 23
24 SLICEL 24
25 Fast Carry Logic u u Each SliceL and SliceM contains separate logic and routing for the fast generation of sum & carry signals Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters Carry logic is independent of normal logic and routing resources MSB LSB Carry Logic Routing 25
26 Accessing Carry Logic u All major synthesis tools can infer carry logic for arithmetic functions Addition (SUM <= A + B) Subtraction (DIFF <= A - B) Comparators (if A < B then ) Counters (count <= count +1) 26
27 27
28 SLICEM 28
29 Xilinx Multipurpose LUT (MLUT) 16-bit 32-bit SR x 1 RAM 4-input 64 x 1 ROM LUT (logic) The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. ( 29
30 Single-port 64 x 1-bit RAM 30
31 Single-port 64 x 1-bit RAM 31
32 Memories Built of Neighboring MLUTs Memories built of 2 MLUTs: Single-port 128 x 1-bit RAM: RAM128x1S Dual-port 64 x 1-bit RAM : RAM64x1D Memories built of 4 MLUTs: Single-port 256 x 1-bit RAM: RAM256x1S Dual-port 128 x 1-bit RAM: RAM128x1D Quad-port 64 x 1-bit RAM: RAM64x1Q Simple-dual-port 64 x 3-bit RAM: RAM64x3SDP (one address for read, one address for write) 32
33 Dual-port 64 x 1 RAM Dual-port 64 x 1-bit RAM : 64x1D Single-port 128 x 1-bit RAM: 128x1S 33
34 Dual-port 64 x 1 RAM Dual-port 64 x 1-bit RAM : 64x1D Single-port 128 x 1-bit RAM: 128x1S 34
35 Total Size of Distributed RAM in Spartan-6 35
36 Total Size of Distributed RAM in Artix-7 36
37 MLUT as a 32-bit Shift Register (SRL32) 37
38 Input/Output Blocks (IOBs) George Mason University
39 Basic I/O Block Structure Three-State FF Enable Clock Set/Reset Output FF Enable D EC SR D EC SR Q Q Three-State Control Output Path Direct Input FF Enable Registered Input Q D EC SR Input Path 39
40 IOB Functionality IOB provides interface between the package pins and CLBs Each IOB can work as uni- or bi-directional I/O Outputs can be forced into High Impedance Inputs and outputs can be registered advised for high-performance I/O Inputs can be delayed 40
41 Family Attributes George Mason University
42 Spartan-6 FPGA Family 42
43 Artix-7 FPGA Family 43
44 FPGA device present on the Digilent Nexys 3 board XC6SLX16-CSG324C Spartan-6 family Logic Optimized Size 324 pins Package type (Ball Chip-Scale) Commercial temperature range 0 C 85 C 44
45 FPGA device present on the Digilent Nexys 4 DDR board XC7A100T-1CSG324C Artix-7 family Size Speed Grade 324 pins Package type (Ball Chip-Scale) Commercial temperature range 0 C 85 C 45
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