ECE 5775 (Fall 17) High-Level Digital Design Automation. Hardware-Software Co-Design

Transcription

1 ECE 5775 (Fall 17) High-Level Digital Design Automation Hardware-Software Co-Design

2 Announcements Midterm graded You can view your exams during TA office hours (Fri/Wed 11am-noon, Rhodes 312) Second paper seminar on Tuesday 10/31 Four student presentations with Q & A Final project logistics Five sample projects posted on course web Kick-off on Thursday Nov 2, 11am-1pm, Rhodes 320 A doodle poll to be posted on Piazza Regular meeting slots will be determined 1

3 Agenda More on final project Brief introduction to HW/SW co-design Midterm problems 2

4 Review: Computing Trends Post Dennard Scaling DEC Alpha MIPS R2K Intel Pentium 4 AMD 4-Core Opteron Intel 48-Core Prototype Transistors (Thousands) Parallel Proc Performance Sequential Processor Performance Frequency (MHz) More transistors, but couldn t afford bigger superscalar => Multicore era 10 2 Typical Power (Watts) 10 1 Number of Cores Data partially collected by M. Horowitz, F. Labonte, O. Shacham, K. Olukotun, L. Hammond Figure credit: Christopher Batten, Cornell 3

5 Donald Knuth on Multicore Architectures Q: Vendors of multicore processors have expressed frustration at the difficulty of moving developers to this model. As a former professor, what thoughts do you have on this transition and how to make it happen? I might as well flame a bit about my personal unhappiness with the current trend toward multicore architecture. To me, it looks more or less like the hardware designers have run out of ideas, and that they re trying to pass the blame for the future demise of Moore s Law to the software writers by giving us machines that work faster only on a few key benchmarks! I won t be surprised at all if the whole multithreading idea turns out to be a flop, worse than the "Itanium" approach that was supposed to be so terrific until it turned out that the wished-for compilers were basically impossible to write. Source:

6 Accelerator-Rich System-on-Chips (SoCs) Modern SoCs: hardware (HW), software (SW), customized for dedicated application domains Heterogeneous processors Heavily customized HW for application Embedded SW tightly coupled with HW Embracing architectural heterogeneity and hardware specialization to improve performance and energy efficiency NVDIA Tegra 2 SoC Even more challenging to design & program! 5

7 Designing Hardware/Software Architecture A significant part of the SoC design problem is deciding which parts should be in software on programmable processors and which in specialized hardware Improve Performance Improve Energy Efficiency Reduce Power Density Manage Design Complexity Reduce Design Cost Stick to Design Schedule Handle Deep Submicron Implement more in Hardware Implement more in Software Lots of issues in this decision making... 6

8 Distinction Between Hardware and Software? Hardware Software int max; int findmax(int a[10]) { unsigned i; max = a[0]; for (i=1; i<10; i++) if (a[i] > max) max = a[i]; }.text findmax: ldr r2,.l10.l10 ldr r3, [r0, #0] str r3, [r2, #0] mov ip, #1.L7: ldr r1, [r0, ip, asl #2] ldr r3, [r2, #0] add ip, ip, #1 cmp r1, r3 strgt r1, [r2, #0] cmp ip, #9 movhi pc, lr b.l7.l11:.align 2. L10:.word max 7

9 Hardware Software Co-Design HW/SW co-design investigates the concurrent design of hardware and software components of complex electronic systems Driving factors Parallel hardware architectures drive new software programming paradigms, and vice versa System-on-chip extensively integrates microprocessors and specialized hardware engines, which calls for intelligent HW/SW partitioning 8

10 Conventional Design Practice Ad hoc approaches based on earlier experience with similar products, & on manual design HW/SW partitioning decided at the beginning, and then designs proceed separately [source: J. Teich, Proc. IEEE, 2012] 9

11 Faster Turnaround Time with Co-Design Separate HW/SW design flow HW/SW co-design flow [source: J. Teich, Hardware/Software Codesign: The Past, the Present, and Predicting the Future, Proc. IEEE, 2012] 10

12 Co-Design Problems of Interest in this Course Co-design of ISAs Compiler and hardware optimization and trade-offs Application-specific instruction set processors (ASIPs) Co-design of reconfigurable systems Systems that can be customized after manufacturing for a specific application Reconfiguration can be accomplished before execution of concurrent with execution 11

13 Case Study: Xilinx Zynq SoC Architecture PS Processing system (i.e., ARM) PL Programmable logic (i.e., FPGA) HP High-performance port GP General-purpose port ACP Accelerator coherency port GP: 2 x 32 bit interfaces Optimized for access from PL to PS peripherals Optimized for access from processors to PL registers HP: 4 x 64 bit interfaces Optimized for high bandwidth access from PL to external memory ACP: 1 x 64 bit interface Optimized for access from PL to processor caches Cache coherent and low latency A compromise between bandwidth and latency Source: Xilinx, Inc., Building Zynq Accelerators with Vivado High Level Synthesis, FPGA 13 Tutorial 12

14 System-Level Considerations Which functions get accelerated in hardware? What changes are required at the macro/micro-architecture levels? How will software communication with hardware? Which interface is better to share/transfer data between CPU & accelerator? Latency or throughput? Impact on background workload? Source: Xilinx, Inc., Designing Xilinx Zynq-Based Systems using SDSoC 13

15 Accelerator with DMA Zynq Processing System Memory Interfaces HP1 Programmable Logic AXI4 interconnect Write to accelerator Processor allocates buffer Sets up scatter-gather list if needed Common Peripherals ARM Dual Cortex-A9 MPCore System AXI_DMA AXI_DMA Processor flushes cache for buffer Processor writes data into buffer HP0 GP0 Acc. 1 Acc. 2 Processor initiates DMA transfer HDMI Output Copyright 2013 Xilinx Pros: High-bandwidth communication AXI4 interconnect Cons: Complicated system architecture; High-latency communication Read from accelerator Processor allocates buffer Sets up scatter-gather list if needed Processor invalidates cache for buffer Processor initiates DMA transfer Processor waits for DMA to complete Processor reads data from buffer Source: Xilinx, Inc., Building Zynq Accelerators with Vivado High Level Synthesis, FPGA 13 Tutorial 14

16 Accelerator with Coherent DMA Zynq Processing System Common Peripherals HDMI Output HP0 Memory Interfaces ARM Dual Cortex-A9 MPCore System GP0 ACP Copyright 2013 Xilinx Programmable Logic AXI_DMA AXI4 interconnect Pros: Low latency, highbandwidth communication AXI4 interconnect AXI_DMA Acc. 1 Acc. 2 Cons: Complicated system architecture; Limited to data that fits in caches Write to accelerator Processor allocates buffer Sets up scatter-gather list if needed Processor flushes cache for buffer Processor writes data into buffer Processor initiates DMA transfer Read from accelerator Processor allocates buffer Sets up scatter-gather list if needed Processor invalidates cache for buffer Processor initiates DMA transfer Processor waits for DMA to complete Processor reads data from buffer Source: Xilinx, Inc., Building Zynq Accelerators with Vivado High Level Synthesis, FPGA 13 Tutorial 15

17 HW/SW Co-Design Tool for Zynq Xilinx SDSoC environment Invokes HLS under the hood Provides infrastructure to combine processing system, accelerators, data movers, and drivers C-callable IP } madd(ina,inb,out){ Optimized RTL IP main(){ } init(a,b,c); mmult(a,b,d); madd(c,d,e); consume(e); } mmult(ina,inb,out){ Synthesizable C/C++ HLS crosscompiled Fast performance estimation App SW SW glue code PS A,B C E PL mmult D madd OS, BSP System linker generates hardware system, software stubs, APIs and configuration Target Board Boot image incl. ELF+.BIT Platform (can incl. PL) Compiler infers data communication, uses data mover IP Source: Xilinx, Inc., Designing Xilinx Zynq-Based Systems using SDSoC 16

18 SDSoC User Development Flow C/C++ Application running on ARM Optimize data transfer and parallelism using SDSoC guidelines Optimize accelerator code User-assisted SW-HW partitioning based on profiling Configure Build to generate SW and HW Select functions to move to HW Specify platform Specify OS Specify functions to move to HW Specify monitor points Analyze performance Run fast estimation SD Card Image Boot image Linux/Standalone Application Elf file Run on the board Source: Xilinx, Inc., Designing Xilinx Zynq-Based Systems using SDSoC 17

19 Summary Modern SoCs are implemented as mixed softwarehardware systems Software is used for features and flexibility, while hardware is used for performance Growing design complexity of embedded systems require holistic system-level design methodology To improve design productivity, quality, reliability, security, and cost Advances in tools and technologies enables Programming languages for co-design High-level synthesis Field-programmable SoCs 18

20 Before Next Class Team up for final project! 3 students / group Next lecture: Student-led paper discussions 19

21 Acknowledgements These slides contain/adapt materials developed by Prof. Patrick Schaumont (Virginia Tech) 20