Dynamic Partial Reconfigurable FIR Filter Design

Transcription

1 Dynamic Partial Reconfigurable FIR Filter Design Yeong-Jae Oh, Hanho Lee, and Chong-Ho Lee School of Information and Communication Engineering Inha University, Incheon, Korea {hhlee, Abstract. This paper presents a novel partially reconfigurable FIR filter design that employs dynamic partial reconfiguration. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters using Xilinx FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This FIR filter design method shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method. 1 Introduction FIR filters are employed in the majority digital signal processing (DSP) based electronic systems. The emergence of demanding applications (image, audio/ video processing and coding, sensor filtering, etc.) in terms of power, speed, performance, system compatibility and reusability make it imperative to design the reconfigurable architectures. This paper presents a partially reconfigurable FIR filter design that targets to meet all the objectives(low-power consumption, autonomous adaptability/reconfigurability, fault-tolerance, etc.) on the FPGA. FPGAs are programmable logic devices that permit the implementation of digital systems. They provide an array of logic cells that can be configured to perform a given functionality by means of a configuration bitstream. Many of FPGA systems can only be statically configured. Static reconfiguration means to completely configure the device before system execution. If a new reconfiguration is required, it is necessary to stop system execution and reconfigure the device it over again. Some FPGAs allow performing partial reconfiguration, where a reduced bitstream reconfigures only a given subset of internal components. Dynamic Partial Reconfiguration (DPR) allows the part of FPGA device be modified while the rest of the device (or system) continues to operate and unaffected by the reprogramming [1]. Module-based partial reconfiguration was proposed by Xilinx [3][4]. And now many researchers have been proposed many partial reconfiguration methods (JBits, PARBIT, etc) [1][2]. The modular design flow allows the designer to split the whole system into modules. K. Bertels, J.M.P. Cardoso, and S. Vassiliadis (Eds.): ARC 2006, LNCS 3985, pp , c Springer-Verlag Berlin Heidelberg 2006

2 Dynamic Partial Reconfigurable FIR Filter Design 31 2 Reconfigurable FIR Filter Design The FIR filter computes an output from a set of input samples. The set of input samples is multiplied by a set of coefficients and then added together to produce the output as shown in Fig. 1. Implementation of FIR filters can be undertaken in either hardware or software [5]. A software implementation will require sequential execution of the filter functions. Hardware implementation of FIR filters allows the filter functions to be executed in a parallel manner, which makes improved filter processing speed possible but is less flexible for changes. Thus, reconfigurable FIR filter offers both the flexibility of computer software, Fig. 1. n-tap transposed FIR filter Fig. 2. Block diagram of (a) partial reconfigurable mnorder FIR filter, (b) reconfigurable multiply-accummulate (rmac) modules

3 32 Y.-J. Oh, H. Lee, and C.-H. Lee and the ability to construct custom high performance computing circuits. Fig. 2 shows the partial reconfigurable mnorder FIR filter, which consists of mn order filter modules and right side module. These FIR filter is consisted of m filter modules, which connected by bus macros on FPGA. And each filter module consists of n/2 reconfigurable multiply-accumulate (rmac) unit, which includes the serial-to-parallel register to get coefficient inputs in serial. 3 Implementation This section describes the implementation method of 20-tap FIR filter, which is reconfigured partially from 12-tap FIR filter. The whole system is implemented on a Xilinx Virtex2p30 FPGA device. 3.1 HDL Coding and Synthesis This step is composed to following two phase: Top Module Design: In this phase, designer must consider each sub-module interconnection, area assignment and bus macro assignment. Reconfigurable Sub-module Design: This phase is same to traditional HDL design method. But designer must consider input and output assign rule for partial reconfiguration. 3.2 Module-Based Design Modular Design Implementation step comprises following three phase: 1) Initial budget phase, 2) Active module implementation, 3) Final assembly. Fig. 3. PAR map of (a) 12-tap and (b) 20-tap FIR filter using DPR

4 Dynamic Partial Reconfigurable FIR Filter Design 33 Initial Budget: In this phase, the team leader assigns top-level constraints to the top-level design. Top-level constraint needs to area constraint and bus-macro assignment. This step is as sequence of top module design. In this step, designer must do bus macro manual setting, sub module area constraint by using floorplanner and top module IOB assignment. Bus macro is limited by target size. Through equation (1), designer can estimate maximum usable bus macro. Active Module Implementation: In this phase, the team members implement the reconfigurable modules. That is, partially reconfigurable sub-modules are generated by top module and.ucf file. Each sub-module generates a partial bitstream during this step. Fig. 3 shows a post-par (placement and routing) diagram. Through n-order filter module1 is reconfigured to bypass module and module2 is reconfigured to 4-tap module on 12-tap FIR filter while other module is processing, 20-tap FIR filter is composed by partial reconfiguration of module1 showing Fig. 3(b). Final Module Assmble: In the phase, designer assembles on system from partially generated modules. All partial modules generated in active module implementation step are combined to the top-level module. 4 Experiment and Result The partial reconfiguration of reconfigurable symmetric transposed FIR filters was implemented on Xilinx Virtex2pro FPGA device using test environment shown in Fig. 4[6]. XUPV2P FPGA test board and Agilent logic analyzer were used for board level verification. And configuration bitstream download is operated by Xilinx Platform Cable USB and IMPACT. For dynamic partial reconfiguration experiment, the partial reconfigurable module1 and module2 were reconfigured bypass module and 4-tap module respectively while other areas of modules remain operational. For verification, we have performed following two methods. First, 12-tap and 20-tap FIR filters before/after partial reconfiguration have been simulated to verify the output results on FPGA test board using Xilinx ChipScope Pro Analyzer. Second, each module has been assigned by identification number such as bypass=00, 2-tap=01, 4-tap=10, 6-tap=11, and then during the partial reconfiguration process the waveform of logic analyzer shows the change of identification number to verify the partial reconfiguration of FIR filter. Because most of modules are operating except reconfigured module, module identification number is changed continuously. After completing DPR, the waveform shows the output change from 3D(111101) to 31 (110001). This result shows that module2 is reconfigured partially from 6-tap module to bypass module. And measured reconfiguration time shows about ms. Otherwise, the full reconfiguration is processed after FPGA reset. Measure reconfiguration time is about 3.05 s. Thus the reconfiguration time of DPR FIR filter is reduced about 1/30 compared to full reconfiguration of FIR filter. For performance comparison, we have implemented FIR filter using variable multipliers, multiplexer

5 34 Y.-J. Oh, H. Lee, and C.-H. Lee Fig. 4. Test Environment Table 1. FPGA device utilization for several FIR filters (GF: General symmetric FIR filter, MBF: Multiplexer-based reconfigurable FIR filter, DPR: Reconfigurable FIR fiter using DPR) GF MBF DPR Slice 3,058 5,349 4,733 LUT 5,980 9,669 8,427 Equivalent N/A 76,024 68,063 Gate based reconfigurable FIR filter and reconfigurable symmetric transposed FIR filter. Table 1 shows the utilization of slice, LUT and equivalent gate count after technology mapping. The reconfigurable symmetric transposed FIR filter using DPR can save about 11.5% slice compared to the multiplexer based reconfigurable FIR filter. Compared to the general symmetric FIR filter, the number of slice increased about 54% because of adding bus macro, serial-to-parallel register and a little controller. But if we want to change one tap in general symmetric FIR filter, we must do the full reconfiguration, which requires the slow configuration time. However, reconfigurable symmetric transposed FIR filter using DPR method requires the partial reconfiguration of about 1,499 slices for one coefficient tap that adds flexibility allowing dynamically inserting and/or removing the coefficient taps.

6 Dynamic Partial Reconfigurable FIR Filter Design 35 5 Conclusion In this paper, we present a reconfigurable FIR filter design using dynamic partial reconfiguration, which has area efficiency, flexibility and configuration time advantage allowing dynamically inserting and/or removing the partial modules. The proposed method produces a reduction in hardware cost and allows performing partial reconfiguration, where a reduced bitstream reconfigures only a given subset of internal components. In the future, self-reconfigurable hardware platform using microcontroller unit and configuration memory will be promising solution for automatic partial reconfiguration of digital circuit in the run-time environment. Acknowledgement This research was supported by the MIC (Ministry of Information and Communication), Korea, under the ITRC (Information Technology Research Center) support program and supported by Inha University research grant. References 1. Mesquita, D., Moraes, F., Palma, J., Moller, L., Calazanas, N.: Remote and Partial Reconfiguration of FPGAs: tools and trends. International Parallel and Distributed Processing Symposium,(2003). 2. Raghavan, A. K., Shutton, P.: JPG-A partial bitstream generation tool to support partial reconfiguration in Virtex FPGAs. Proc. Of the International Parallel and Distributed Processing Symposium, (2002) 3. Xilinx Inc.: XAPP 290: Two flows for Partial Reconfiguration: Module Based or Difference Based. Sept. (2004) 4. Xilinx Inc.: Development System Reference Guide Meyer-Baese, U.: Digital Signal Processing with Field Programmable Gate Arrays. Springer, (2001). 6. Xilinx: Managing Partial Dynamic Reconfiguration in Virtex-II Pro FPGAs. Xcell Journal, Xilinx, Fall (2004)