Remote and Partial Reconfiguration of FPGAs: Tools and Trends

Transcription

1 Remote and Partial Reconfiguration of FPGAs: Tools and Trends Daniel Mesquita, Fernando Moraes, José palma, Leandro Moller, Ney Calazans Laboratoire de Informatique, de Robotique et de Microéletronique de Montpellier (LIRMM France) Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS - Brazil)

2 Summary Introduction State of art History and trends Related work Virtex internal organization Architecture overview Addressing elements Tools for partial and remote Conclusions Slide / 6

3 Summary Introduction State of art History and trends Related work Virtex internal organization Architecture overview Addressing elements Tools for partial and remote Conclusions Slide 3 / 6

4 Introduction Reconfigurable computing has been growing in the past two decades Sometimes there is confusion about the concept of dynamic We work with dynamic reconfigurable of-the-shelf devices, particularly Virtex family One more step towards hardware virtualization Slide 4 / 6

5 Summary Introduction State of art History and trends Related work Virtex internal organization Architecture overview Addressing elements Tools for partial and remote Conclusions Slide 5 / 6

6 State of art Reconfigurable computing evolution 1 st GENERATION nd GENERATION 3 rd GENERATION Prism DecPerle Splash Spyder Transmogrifier Problems Found Comunication bottleneck Inflexible net interconection Reconfiguration Time Solutions Proposed SoC with coarse grain SoC with fine grain External net re configuration Context switching Partial/dynamic GARP RAW XPUTER FIPSOC TRUMPET RPM SPLASH TRUMPET FPSLIC DISC VIRTEX SOCS TARGETING HARDWARE VIRTUALIZATION Methods Configuration based on computational stream Configurations Pipeline Circular Pipeline SOC w/ Partial/dynamic SCORE PIPERENCH Systolic Ring Virtex- II Pro Slide 6 / 6

7 State of art 1 st Generation Goal: to increase performance of algorithms (e.g. Cryptography) over GPPs 1 st GENERATION nd GENERATION 3 rd GENERATION Prism DecPerle Splash Spyder Transmogrifier Problems Found Comunication bottleneck Inflexible net interconection Reconfiguration Time Solutions Proposed SoC with coarse grain SoC with fine grain External net re configuration Context switching Partial/dynamic GARP RAW XPUTER FIPSOC TRUMPET RPM SPLASH TRUMPET FPSLIC DISC VIRTEX SOCS TARGETING HARDWARE VIRTUALIZATION Methods Configuration based on computational stream Configurations Pipeline Circular Pipeline SOC w/ Partial/dynamic SCORE PIPERENCH Systolic Ring Virtex- II Pro Slide 7 / 6

8 State of art 1 st Generation Main problems: 1 st GENERATION nd GENERATION 3 rd GENERATION Prism DecPerle Splash Spyder Transmogrifier Problems Found Comunication bottleneck Inflexible net interconection Reconfiguration Time Solutions Proposed SoC with coarse grain SoC with fine grain External net re configuration Context switching Partial/dynamic GARP RAW XPUTER FIPSOC TRUMPET RPM SPLASH TRUMPET FPSLIC DISC VIRTEX SOCS TARGETING HARDWARE VIRTUALIZATION Methods Configuration based on computational stream Configurations Pipeline Circular Pipeline SOC w/ Partial/dynamic SCORE PIPERENCH Systolic Ring Virtex- II Pro Slide 8 / 6

9 State of art st Generation Goal: to fix the problems from the first generation 1 st GENERATION nd GENERATION 3 rd GENERATION Prism DecPerle Splash Spyder Transmogrifier Problems Found Comunication bottleneck Inflexible net interconection Reconfiguration Time Solutions Proposed SoC with coarse grain SoC with fine grain External net re configuration Context switching Partial/dynamic GARP RAW XPUTER FIPSOC TRUMPET RPM SPLASH TRUMPET FPSLIC DISC VIRTEX SOCS TARGETING HARDWARE VIRTUALIZATION Methods Configuration based on computational stream Configurations Pipeline Circular Pipeline SOC w/ Partial/dynamic SCORE PIPERENCH Systolic Ring Virtex- II Pro Slide 9 / 6

10 State of art 3 st Generation Goal: to make possible the hardware virtualization trhough dynamic 1 st GENERATION nd GENERATION 3 rd GENERATION Prism DecPerle Splash Spyder Transmogrifier Problems Found Comunication bottleneck Trends: Reconfiguration Time Solutions Proposed SoC with coarse grain SoC with fine grain SoCs, Coarse-grain Inflexible net External net interconection re configuration architectures Context switching Partial/dynamic GARP RAW XPUTER FIPSOC TRUMPET RPM SPLASH TRUMPET FPSLIC DISC VIRTEX SOCS TARGETING HARDWARE VIRTUALIZATION Methods Configuration based on computational stream Configurations Pipeline Circular Pipeline SOC w/ Partial/dynamic SCORE PIPERENCH Systolic Ring Virtex- II Pro Slide 10 / 6

11 Summary Introduction State of art History and trends Related work Virtex internal organization Architecture overview Addressing elements Tools for partial and remote Conclusions Slide 11 / 6

12 Virtex Organization Architecture Overview Atomic reconfigurable unit: frame Regular internal structure (composed by s) Allow relocation and defragmentation It is partial or fully reconfigurable device Slide 1 / 6

13 Virtex Organization Architecture Overview Abstraction of virtex internal organization INPUT/OUTPUT IOB RESOURCES 54 FRAMES SELECT BLOCK RAM 64 FRAMES CLOCK DISTRIBUTION 8 FRAMES BLOCK RAM INTERCONNECT RESOURCES 7 FRAMES BLOCK RAM INTERCONNECT RESOURCES 7 FRAMES SELECT BLOCK RAM 64 FRAMES INPUT/OUTPUT IOB RESOURCES 54 FRAMES Number bellow columns represents the MJA major address. 48 frames by column Slide 13 / 6

14 Slide 14 / 6 Virtex Organization Addressing elements Equations

15 Virtex Organization Addressing elements Abstraction s clock s row 1 row row 3 row 17 row 18 row 19 row 0 C30 C8 C6 C5 C7 C9 Slice 1 G lut FF 1 F lut FF Slice 0 G lut FF 1 F lut FF Bit 14 of F-LUT R1C1.S0 Slide 15 / 6

16 Summary Introduction State of art History and trends Related work Virtex internal organization Architecture overview Addressing elements Tools for partial and remote Conclusions Slide 16 / 6

17 Tools for partial and remote Circuit customization tool Function: Generate a graphical interface to customize circuit parameters Parameters stored in LUTs. The circuit can be reconfigured local or remotely Benefits: FPGA architecture is hidden from designer Eliminates the need of external devices and/or the associated control logic to set parameters at run time Remarks: There are three «players» related with this process: Software developer Circuit designer Circuit user Slide 17 / 6

18 Tools for partial and remote Circuit customization tool Software developer implements the software layer, using JBITS classes, hiding the FPGA architecture details (applet) this applet is the same for all circuits being customized Circuit designer uses HTML tags to pass commands and parameters to the applet to customize his circuit <APPLET code="bitgeneric.class" width=400 height=300> <PARAM name="nbsignals" value="8"> <PARAM name="path" value="top_e1.bit"> <PARAM name="ip" value=" "> <PARAM name="port" value="5000"> <PARAM name="l[1]" value="crccontrol,bin,3,37,g,0,0,0"> <PARAM name="l[8]" value="datainsert,hex,8,37,g,0,0,15"> </APPLET> designer must indicate the physical position of the memory blocks containing parameters Slide 18 / 6

19 Tools for partial and remote Slide 19 / 6 Circuit customization tool Circuit user receives the bitstream and the HTML description in the page the values of the signals can be modified, saved and partially downloaded into the device

20 Tools for partial and remote Slide 0 / 6 Core unifier tool Function: Insert / remove partial bitstreams (hard cores) at runtime Benefits: Makes possible the hardware virtualization

21 Tools for partial and remote Slide 1 / 6 Core unifier tool Graphical interface

22 Tools for partial and remote Core unifier tool 1. Core buffer layer. Common routing wires 3. Controller buffer layer 4. External world connection Slave Core Slave Core Slave Core Controller Slide / 6

23 Tools for partial and remote Core unifier tool 1. A complete master bitstream is opened. One or more bitstreams containing slave cores to be inserted into the master bitstream are opened BITSTREAM 1 (master): Tri-state buffers Master core Arbiter Dummy cores Controller BITSTREAM n: Slave core and dummy ctrl Tri-state buffers Send and receive modules Slave Core Bitstreams merging 3. The user selects the area corresponding to one core, and all components inside this area (routing and s) are inserted into the master bitstream Final bitstream Partial Bitstream Slave Core Controller Slide 3 / 6

24 Summary Introduction State of art History and trends Related work Virtex internal organization Architecture overview Addressing elements Tools for partial and remote Conclusions Slide 4 / 6

25 Conclusion Contributions 1. State of art review, indicating trends. Tool-set for remote, partial and dynamic Remote is enabled Parameter can be used to fix/modify a circuit Virtual hardware is feasible with of-the-shelf FPGAs Future works 1. To extend the bus structure, to analyze other arbitration schemes. To develop CAD for the manual steps mentioned Slide 5 / 6

26 Conclusion «Final» conclusion The core unifier tool can be integrated with co-design tools. Currently, the hardware cores of a SOC require a programmable device having enough area to implement all cores. Another possibility is the generation of several small hardware cores by the co-design tool, with a scheduler to download these cores on-demand into the FPGA device. This can be seen as a dynamic co-design, a new concept not yet explored. Slide 6 / 6