Development of Precision-Agriculture Data Acquisition System and Xilinx ChipScope Pro Logic Analyzer based Monitoring

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1 International Journal of Electronics and Computer Science Engineering 245 Available Online at ISSN Development of Precision-Agriculture Data Acquisition System and Xilinx ChipScope Pro Logic Analyzer based Monitoring S.R. Patil 1, R.K. Kamat 2, P. K. Gaikwad Embedded System and VLSI Research Laboratory, Department of Electronics Shivaji University, Kolhapur 3 pawangaikwad2003@yahoo.co.in Abstract- The research paper focuses on the development of a data acquisition system for precision-agriculture by sensing physical parameters; associated with the farm-soil. It requires different modules to be deployed in a system to perform data acquisition process over multiple parameters. However, the prototype developed in this research work deals with an embedded system comprising the less chip-count and consequently reduce overall power utilization. The analogue multiplexer routes electrical signals produced by farm-parameter sensors. Such signals were transformed into their digital equivalents by means of a 12-bit serial Analogue to Digital Converter (ADC); which was driven by the Xilinx Field Programmable Gate Array (FPGA). The research work deals with a standardized real-time hardware-signal monitoring system using the Xilinx ChipScope Pro Logic Analyzer. Keywords FPGA, Serial ADC, Analogue Multiplexer, Xilinx ChipScope Pro, Precision Agriculture I. INTRODUCTION THE sustainability of producing technologically advanced farming becomes necessary; because the well known fact is that, basically the wealth and security of a nation materializes from its land. The precision-agriculture having precise inputs like sufficient as well as good water, fertilizer, and insecticides at the right time to the crops can help the nation to make its position in the next Green Revolution. The research paper deals with the development of a system to perform the multiplexed data acquisition system essential in precision-agriculture. The farm parameters may be sensed by different sensors, like temperature, electrical conductivity of the soil, power of hydrogen or potential of hydrogen (ph) present in the soil, soil moisture, and the percentage level of the humidity in the atmosphere around the farm. However, the upshot of this research work is to explore the practical aspects of analogue multiplexing and to digitization of electrical signals; produced from sensors. The data acquisition process was performed by the Soft Intellectual Property (IP) Core in the Field Programmable Gate Array (FPGA). To perform analogue multiplexing over the electrical signals of different sensors, and route them towards the data acquisition unit, the analogue multiplexer integrated circuit (IC) was installed on the prototype board. The instrumentation comprises of FPGA board, a serial ADC and analogue multiplexer chip. As given in [1], it shows an FPGA-based data acquisition system, utilizing the high processing speed feature of FPGA. It realizes the physical signal acquisition, analogue signal to digital signal conversion and data storage. The FPGA, as the core of the data acquisition system, collects and stores the data. The system was divided into three modules: the front-end signal processing module, FPGA data acquisition module, and data storage module. An FPGA based data acquisition system designed around XCS30 is also reported in [2]. The Feeder Terminal Unit (FTU) is used to real-timely monitor the voltages and currents of multiple lines. With the parallel processing ability of FPGA, the input signals are synchronously sampled, and then one-by-one converted from analogue to digital data and quickly transmitted. A multi-channel data collection system based on Advanced Reduced Instruction Set Computer Machines (ARM) is also presented in [3]. By combining the software and hardware technologies, eight-channel analogue signal collecting system is

2 IJECSE, Volume 4, Number 3 S.R. Patil et al 246 realized. Its experimental result show there are 14 bit collection precision and (140 KHz/s) sampling rate in system. In addition Compact Flash (CF) storage and three communication ways are attained. The FPGA designs have become increasingly dense and complex. They are difficult to debug because more and more of the relevant signals are buried deep within the logic fabric. Access to signals in the FPGA, on board or in the system is very restricted whether troubleshooting is done in the lab or in the field. The Xilinx ChipScope Pro integrated logic analyzer has solved much of the problem at the FPGA level. A research work given in [4] shows that, ChipScope has been used to test and verify a developed system that presents the digital core of a wireless sensor module and it has been implemented in (Spartan 3) based FPGA development board. To march on the similar platform, in this research work, to visualize the data acquisition process the Xilinx ChipScope Pro was deployed; instead of the traditional signal monitoring systems like Logic State Analyzers which increases the system monitoring cost. Such graphical visualization on ChipScope Pro portrays the digitized data from serial ADC, as well as the signal that generates Inter Integrated Circuit (I2C) serial communication protocol. An external hardware trigger was also provided to enable the ChipScope Pro logic analyzer window, so as to capture the signal waveforms during hardware run-time. II. BLOCK DIAGRAM OF THE SYSTEM The Fig.1 illustrates the block diagram of the system to perform multiplexed data acquisition process over various farm parameters, essential in the precision-agriculture. At present only one parameter i.e. temperature was sensed and converted into its equivalent analogue signal. For this prototype development, a simple LM35 temperature sensor was interfaced with the analogue multiplexer chip: IC4051 from ST microelectronics. The details of such multiplexer IC are given in [5]. The select lines of the multiplexer were connected to select different farm parameters (at present the I0 input) and route it towards the serial ADC input, as shown in Fig.1. The serial ADC module was embedded with a 12 bit ADC chip AD7991, which was driven by serial communication protocol (I2C) to sample analogue input voltages and convert them into their digital equivalents. The I2C serial communication protocol signals were generated by the reconfigurable device from Xilinx. A soft IP core given in [6] was implemented into the Spartan-3E FPGA: xc3s500e-4fg320. The FPGA board Nexys2, provided by Digilent Inc. [7] was deployed for this prototype instrumentation. Figure 1. Block Diagram of the Multiplexed Data Acquisition System, Monitoring Farm Parameters on Xilinx ChipScope Pro Logic Analyzer To visualize the 12 bit serial ADC output, the Xilinx ChipScope Pro tools were invoked. The Integrated Logic Analyzer (ILA) core, provided in Xilinx ChipScope Pro tools, was generated to monitor various internal signals; buried within the FPGA logic fabric. The ILA core was controlled by an Integrated Controller (ICON). A top level Hardware Description Language (HDL) module was developed to instantiate two ChipScope cores: ILA and ICON, and the serial ADC driver module. The

3 247 Development of Precision-Agricultural Data Acquisition System and Xilinx ChipScope Pro Logic Analyzer Based Monitoring analogue multiplexer has eight input signals being connected towards the serial ADC one by one. The ADC produces a 12 bit magnitude; related with the analogue input voltages. III. DEVELOPMENT OF TOP LEVEL SOFT IP CORE The top level Soft IP core was developed to integrate serial ADC module as given in [6], and the Xilinx ChipScope Pro cores: ICON and ILA were also integrated therein. These three VHDL components were interfaced using structural modeling style of the Very High Speed Integrated Circuit Hardware Description Language (VHDL) architecture. The following lines of VHDL code describes the input/output lines of the top level module developed in this research work. entity AMUX_CS is port (TRIG_COND RESET SYS_CLK :in STD_LOGIC; -- H/W Trigger : in STD_LOGIC; -- Global Reset : in STD_LOGIC; -- Generic Clock AD2_SCL : inout STD_LOGIC; AD2_SDA : inout STD_LOGIC); end AMUX_CS; Figure 2. RTL Synthesis View of the Top Level VHDL Entity AMUX_CS The VHDL entity named as AMUX_CS consist of three input mode signals. The system clock (SYS_CLK) is a generic clock input. An asynchronous RESET input resets the system, when it is asserted high. The third input signal TRIG_COND triggers the ChipScope Logic Analyzer window to capture pre-defined number of samples (1024 here). The conditional triggering was optional to select at the time of monitoring FPGA internal signal-waveforms on Logic Analyzer window. There are two special inout mode signals, driving the serial ADC chip, using serial communication protocol. These I2C communication protocol signals are AD2_SCL and AD2_SDA. The Fig. 2 shows a Register Transfer Level (RTL) synthesis view of the top level module: AMUX_CS. The Table 1 shows the synthesis report of the VHDL module developed in this research work. It reports that, the top level module including components like serial ADC driver, ChipScope modules: ILA and ICON, requires different FPGA hardware resources. Table -1 Device Utilization: Spartan 3E FPGA: XC3S500E-4FG320E Logic Utilization Used Available Utilization Total Number Slice Registers 405 9,312 4% Number used as Flip Flops 404

4 IJECSE, Volume 4, Number 3 S.R. Patil et al 248 Number used as Latches 1 Number of 4 input LUTs 375 9,312 4% Number of occupied Slices 390 4,656 8% Number of Slices containing only related logic % Number of Slices containing unrelated logic % Total Number of 4 input LUTs 491 9,312 5% Number used as logic 290 Number used as a route-thru 116 Number used as Shift registers 85 Number of bonded IOBs % Number of RAMB16s % Number of BUFGMUXs % Number of BSCANs % Number of RPM macros 12 Average Fan-out of Non-Clock Nets 2.90 A detailed view of the RTL synthesis result is also shown in Fig.3. It depicts that, three Soft IP cores have been instantiated together to form a top level VHDL module, AMUX_CS. It comprises of ChipScope soft IP modules with their instance names as CS_ICON and CS_ILA. The third component augmented in the top level module is CS_MSTRCNT. The IO lines shown in Fig.3 resembles with the top level module shown in Fig.2. Figure 3. RTL A detailed view of RTL Synthesis Result showing three Soft IP Cores instantiated together IV. XILINX CHIPSCOPE PRO BASED DIGITAL SYSTEM MONITORING The digital systems are generally monitored using logic state analyzers; having 16 or 32 bits channels. To monitor more number of signals on such analyzer, it requires the high-cost instrumentation setup. To overcome with the problem of high-

5 249 Development of Precision-Agricultural Data Acquisition System and Xilinx ChipScope Pro Logic Analyzer Based Monitoring cost monitoring system, which is based on logic state analyzer, the Xilinx ChipScope Pro plays a vital role and assists monitoring of maximum number of channels. A single ILA core available in Xilinx ChipScope Pro is capable of monitoring 32 bit signals, and the single ICON is capable of controlling 15 cores like ILA, Virtual Input/ Output (VIO) etc. The detail of generating ICON and ILA cores is as given in [9]. The Fig.4 illustrates the Xilinx ChipScope Pro Logic Analyzer window. It shows a waveform-window exploring FPGA internal signals, indicating the serial ADC 12 bit data; which is un-routed towards the FPGA I/O pads. Figure 4. A Photograph of Testing the Farm-Parameters Monitoring System using FPGA The 12-bit-resolution, four channels, Analogue to Digital device (IC AD7991) is embedded on the peripheral module: PmodAD2; which is designed and manufactured by Digilent Inc. The same is deployed in this research work. The ADC Transfer Function shows that, the output coding of the AD7991 is straight binary. The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size for the AD7991 is V REF /4096 [10]. The V REF given from the Nexys2 board to PmodAD2 was 3.3 Volts. Thus, to show a relationship between analogue voltages observed on the DMM with the output of serial ADC, the V REF (3.3V) was multiplied with the LSB size, mv. Figure 5. ChipScope Logic Analyzer Waiting for External Hardware Trigger Out of the entire bus signal, as shown in Fig. 4, only the lower order 12 bit signal is allied with the serial ADC output. The decimal equivalent of lower order 12 bit signals (152H) is 338. To calculate its analogue equivalent magnitude, the decimal number 338 was multiplied with the LSB size, 0.805mV. This results to mV. The observed reading on DMM

6 IJECSE, Volume 4, Number 3 S.R. Patil et al 250 as shown in Fig. 6 is 0.27V i.e. 270mV. This verifies that, the bus signal shown by ChipScope Logic Analyzer resembles with the analogue amplitude displayed on DMM. The Xilinx ChipScope Pro logic analyzer also facilitates triggering the capture-window using external hardware trigger. It is optional to use this kind of trigger at the time of capturing waveforms on analyzer. The core ILA was designed to have only one external 8-bit trigger bus. The top level module signal named as TRIG_COND was connected to the trigger line TRIG0[0] using a VHDL line of the source code: TRIG0(0)<=TRIG_COND;. The Fig.5 shows the application of external hardware trigger. It depicts that, TRIG0[7:0] was stimulated by value XXXX_XXX1 and verified for its equality using a function (==). It reveal that, when lower order line of TRIG0[7:0] was given a high signal, the logic analyzer captures the waveforms; only when its associated signal gets external hardware signal high. On the contrary, the logic analyzer buffer captures 0% waveforms and keeps on waiting for trigger, as shown in Fig.5. IV. RESULTS The Fig. 6 illustrates a photograph taken at the time of actual testing of the prototype; developed for testing the farm parameters. One of the farm parameters i.e. temperature, has been taken for testing of the system. It contains the interfacing of FPGA board: Nexys2 developed by Digilent Inc. with the serial ADC module, PmodAD2. The details of analogue multiplexer IC HCF4051B are given in the data sheet [5]. Presently only one analogue input channel was selected using its select lines at C, B and A inputs. The Fig.6 also depicts that, the temperature sensor LM35 output line is connected to the multiplexer s input channel I0. The digital multi-meter (DMM), displays the voltage produced by temperature sensor of the order of 0.27 Volts (270 mv). As given in [8], the scale factor of LM35 temperature sensor is 10mV/ C. The DMM displays 270mV; which relates with the temperature of the order of 27 C. Figure 6. A Photograph of Testing the Farm-Parameters Monitoring System using FPGA IV.CONCLUSION The research paper focuses on the development of a prototype for the precision-agriculture, with the help of analogue multiplexer and FPGA based system. The attention has been given to perform a well-defined data acquisition process over different farm parameters, as well as to develop a highly advanced monitoring system using the Xilinx ChipScope Logic Analyzer. The ChipScope Analyzer serves to display FPGA internal signals in run-time. At present, a single physical

7 251 Development of Precision-Agricultural Data Acquisition System and Xilinx ChipScope Pro Logic Analyzer Based Monitoring parameter, temperature has been taken into the consideration to develop the prototype. As a future extension of the research work, the researchers would deploy different sensors for signal conditioning over the farm parameters; like electrical conductivity of the soil, (ph) in the soil, the soil-moisture and the percentage level of the humidity in the atmosphere around the farm. At the farmer-end the complete system developed using such a platform assures that, it would definitely increase the crop-productivity; when the soil electrical-conductivity kind of key-parameter is observed keenly; due to which an automatic loop-control system would take care of controlling the salinity of the soil. REFERENCE [1] Ye Fan., FPGA-based data acquisition system. Signal Processing, Communications and Computing (ICSPCC), 2011 IEEE International Conference on. ISSN: [2] YANG Shujie, GUO Zonglian, Development of high-speed data acquisition system based on FPGA, CNKI Journal: Electric Power Automation Equipment. ISSN: June [3] RUAN Shuang-xi,QIU Chun-ling,TIAN Di, Research and Design of Meteorological Data Collection System Based on ARM, CNKI Journal: Electric Power Automation Equipment. ISSN: February [4] Arshak, Khalil; Jafer, E.; Ibala, C., Testing FPGA based digital system using XILINX ChipScope logic analyzer, Electronics Technology, ISSE '06. 29th International Spring Seminar on. E-ISBN: May [5] A datasheet of HCF4051B. Analogue Multiplexers-Demultiplexers, Viewed 29 December 2013, from [6] Support Document, Xilinx ISE demo project for the PmodAD2 and a PmodDA1, Digilent, Inc., Pullman, WA , DSD November [7] Reference manual, Digilent Nexys2 Board Reference Manual, Digilent Inc., Pullman, WA 99163, Doc: [8] A datasheet of LM35. Temperature Sensor. Viewed 29 August 2013, from [9] Pawan Gaikwad. Xilinx ChipScope Pro to Visualize FPGA Internal Signals. Lap Lambert Academic Publishing. ISBN: [10] Datasheet. 4-Channel, 12-/10-/8-Bit ADC with I2C-Compatible Interface in 8-Lead SOT-23. Analogue Devices, Inc., U.S.A.,