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1 Doc Rev 1.04 Datasheet 11-Aug-2010 Document information Info Author Keywords Content J.G. 1010, Datasheet Abstract

2 Revision History Revision Date Description Author Second revision J.G Max output current values updated J.G Annex 2 updated A.M.A. Copyright: 2010 ADD Semiconductor. ADD Semiconductor does not warrant nor represent that any license, either expressed or implied is granted under any ADD Semiconductor patent right, copyright, mask work right or other ADD Semiconductor intellectual property right relating to any combination, machine or process in which ADD Semiconductor product and services are used. Information published by ADD Semiconductor regarding third party products or services does not constitute a license from ADD Semiconductor to use such products or services or a warranty of endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from ADD Semiconductor under the patents or other intellectual property of ADD Semiconductor. Third party trademarks are hereby acknowledged. Liability disclaimer ADD Semiconductor reserves the right to make changes without further notice to the product to improve reliability, functionality or design. ADD Semiconductor does not assume any liability arising out of the application or use of any product or circuits described herein. All application information is advisory and does not form part of the specification. Life support applications These products are not designed for its use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. ADD Semiconductor customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify ADD Semiconductor for any damages resulting from such improper use or sale. Contact details For your nearest distributor, please see Receive available updates automatically by subscribing to enews from our homepage or check our website regularly for any available updates. Headquarters: Torre C2, Pol. Puerta Norte, A-23 Km. 509, Zaragoza (Spain) Phone: ; Fax: Advanced Digital Design Doc Rev 1.04 Datasheet 11-Aug

3 Contents 1. General Description Block Diagram Pin Assignment Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions DC Characteristics Power Consumption Thermal data Oscillator Power-on Mechanical data Recommended mounting conditions Conditions of Standard Reflow Temperature Profile Manual Soldering Annex Annex ADD1010 Application circuit example Analog Front End example Doc Rev 1.04 Datasheet 11 Aug

1. General Description ADD1010 is a Power Line Communications SOC which implements a full PLC node using FSK modulation.

A complete set of Peripherals has been developed achieving a high grade of versatility, providing a low cost and small size solution for AMR & AMM system using narrow band power line communications.

5kHz Baudrate Selectable: 600 to 4800 bps Compliant to EHS and KONNEX Half Duplex Receiver Sensitivity: Up to 44dBμVrms Convolutional coding, Viterbi decoding CRC and FEC error correction Enhanced

4 1. General Description ADD1010 is a Power Line Communications SOC which implements a full PLC node using FSK modulation. It includes an enhanced 8051 microcontroller, a Medium Access Controller (MAC) and a Modem circuit for Power Line medium. A complete set of Peripherals has been developed achieving a high grade of versatility, providing a low cost and small size solution for AMR & AMM system using narrow band power line communications. Features: Power Line Carrier Modem for 50 and 60Hz mains 8 Programmable Carrier Frequencies from 60 to 132.5kHz Baudrate Selectable: 600 to 4800 bps Compliant to EHS and KONNEX Half Duplex Receiver Sensitivity: Up to 44dBμVrms Convolutional coding, Viterbi decoding CRC and FEC error correction Enhanced 8051 core, Average speedup of 5 times 128Kbytes internal SRAM 24x8/28x4 Segments LCD Driver Auto Boot-loading Program from Serial Flash In-circuit Serial Flash Programming Programmable Watchdog 3 x UART SPI to Serial Flash and external RTC Buffered SPI to external metering IC Quadruple Dimmer in/out Power Supply 3.3v Pb-Free and RoHS compliant Ambient Temperature Range: -40 C to +85 C 144 pin plastic LQFP (16 x 16 mm) Typical Applications: Automated Meter Reading (AMR) & Advanced Meter Managing (AMM) Street lighting Home Automation ADD CCCCCCCCCCCCC OOOOO YYWW TTT LL Ordering Code : MARKING DIAGRAM =Customer Logo =Customer Part number =Country of Origin =Year/week code =Control Code =Lead Free Code ADD1010AQF144 Pb-Free Doc Rev 1.04 Datasheet 11 Aug

5 1.1 Block Diagram DEBUG D_INIT RSTA Reset Interface Hz RESET Clock DEBUG Power Management VDD VSS LDO_PD CLKA CLKB Clock Interface VDEO INT1 8051C3A Core IDATA JTAG Bscan TDI TDO TCK TRST TMS 128KB SRAM XDATA SRAM CODE SRAM GENERAL PURPOSE I/O BOOT LOADER /PROG SECURED P1.7/ SSN TRIAC_(3:0) VNR DIMMER PERIPHERAL M U X INTA(3:0) INTB(3:0) INTC(3:0) SPI0 SPI1 P5(3:0) P4(5:2) INTD(3:0) UART0 P3(1:0) SEGM(23:20) SEGM(19:0) BCKP(7:4) BCKP(3:0) LCD DRIVER UART1 P5(5:4) UART2 P4(1:0) MEDIUM ACCESS CONTROL TIMER0 TIMER1 P3.4/T0 P3.5/T1 VSENSE PSENSE EMIT(12:1) EMIT0 ENABLE DC_COMP D_IN D_NIN REC(8:1) VIN VRH VRL PLC MODEM TIMER2 T11, T12, T14 WATCHDOG P4.6/T2 P4.7/T2EX /EWDG AVD AVS Figure 1. ADD1010 Block Diagram Doc Rev 1.04 Datasheet 11 Aug

6 1.2 Pin Assignment The following figure illustrates the pinout of the ADD1010 LQFP144 package: Figure 2. LQFP pin assignment Doc Rev 1.04 Datasheet 11 Aug

7 PinNo Pin Name I/O I(mA) Res HY Pin Description 1 P3_3/INT1 I/O ±5 PU - INT1 external interrupt 1 2 P v Power Supply 3 P Ground 4 P Ground (*) 5 P Ground (*) 6 TDI I ±5 PU - JTAG Test Data In 7 TDO O ±5 - - JTAG Test Data Out 8 TCK I ±5 - - JTAG Test Clock 9 TMS I ±5 PU - JTAG Test Mode Select 10 TRST I ±5 PU - JTAG Test Reset 11 D_INIT I ±5 PD Y Initialization signal 12 RSTA I ±5 PD Y Asynchronous Reset 13 /PROG I ±5 PU Y SPI Flash programming pin 14 SECURED I ±5 PD Y Encryption enabling 15 /EWDG I ±5 PD Y Watchdog enable. Active low 16 DEBUG I ±5 PD Y Debug mode enable 17 P v Power Supply 18 CLKEB I/O External clock reference. The user may connect CLKEB to a compatible oscillator or to one terminal of a crystal oscillator 19 P Ground 20 CLKEA I External clock reference. The user may connect CLKEA to the other terminal of the crystal oscillator or tie CLKEA to ground 21 P v Power Supply 22 P Ground 23 P Ground 24 VDE0 P LDO power input. 25 VDE0 P LDO power input. 26 VSS0 P LDO ground 27 LDO_PD I LDO Power down 28 VDD P LDO power output. A capacitor in the range 0.1μF-10μF must be connected here 29 P Ground 30 P v Power Supply 31 VSENSE I ±5 - Y Voltage Amplitude tracking to avoid malfunction 32 PSENSE I ±5 - Y Power tracking to avoid malfunction 33 VNR I ±5 - Y Zero Crossing Detection signal. Used in Home Automation control pins 34 TRIAC_3 O ±5 - - Home Automation Control 3 35 TRIAC_2 O ±5 - - Home Automation Control 2 36 TRIAC_1 O ±5 - - Home Automation Control 1 37 TRIAC_0 O ±5 - - Home Automation Control 0 38 P5_5/TXD1/INTA1 I/O ±5 PU - TxD Serial Port 1 output. Can be configured as dimmer switch input 39 P5_4/RXD1/INTA0 I/O ±5 PU - RxD Serial Port 1 input. Can be configured as dimmer switch input 40 P4_7/T2EX/INTA3 I/O ±5 PU - T2EX Timer2 External input. Can be configured as dimmer switch input 41 P4_6/T2/INTA2 I/O ±5 PU - T2 Timer2 input/output. Can be configured as dimmer switch input Doc Rev 1.04 Datasheet 11 Aug

8 PinNo Pin Name I/O I(mA) Res HY Pin Description 42 P1_7/SSN I/O ±5 PU - 43 P v Power Supply 44 P Ground 45 EMIT_0 O ±X - - TXRX control output pin 46 EMIT_1 O ±X - - PLC Transmission port 1 47 EMIT_2 O ±X - - PLC Transmission port 2 48 P v Power Supply 49 P Ground 50 EMIT_3 O ±X - - PLC Transmission port 3 51 EMIT_4 O ±X - - PLC Transmission port 4 52 EMIT_5 O ±X - - PLC Transmission port 5 53 EMIT_6 O ±X - - PLC Transmission port 6 54 P v Power Supply 55 P Ground 56 EMIT_7 O ±X - - PLC Transmission port 7 57 EMIT_8 O ±X - - PLC Transmission port 8 58 EMIT_9 O ±X - - PLC Transmission port 9 59 EMIT_10 O ±X - - PLC Transmission port P v Power Supply 61 P Ground 62 EMIT_11 O ±X - - PLC Transmission port EMIT_12 O ±X - - PLC Transmission port P v Power Supply 65 P Ground 66 P3_1/TXD0 I/O ±5 PU - TxD Serial Port 0 output 67 P3_0/RXD0 I/O ±5 PU - RxD Serial Port 0 input Silicon Serial Number input. (P1.7 must not be used as generic control port since it searches for a Silicon Serial number device at start-up and could put out undesirable transient values) 68 P4_5/MISO1/INTB3 I/O ±5 PU - MISO1 SPI1 master in / slave out Data. Can be configured as dimmer switch input 69 P4_4/MOSI1/INTB2 I/O ±5 PU - MOSI1 SPI1 master out / slave in Data. Can be configured as dimmer switch input 70 P4_3/SPICLK1/INT SPICLK1 SPI1 clock input/output. Can be configured as dimmer I/O ±5 PU - B1 switch input 71 P4_2/SS1/INTB0 I/O ±5 PU - SS1 SPI1 Slave Select input. Can be configured as dimmer switch input 72 P4_1/TXD2 I/O ±5 PU - TxD Serial Port 2 output 73 P4_0/RXD2 I/O ±5 PU - Rxd Serial Port 2 input 74 P v Power Supply 75 P Ground 76 SEGM_23/INTC3 I/O ±5 - - LCD Segment 23. Can be configured as dimmer switch input 77 SEGM_22/INTC2 I/O ±5 - - LCD Segment 22. Can be configured as dimmer switch input 78 SEGM_21/INTC1 I/O ±5 - - LCD Segment 21. Can be configured as dimmer switch input 79 SEGM_20/INTC0 I/O ±5 - - LCD Segment 20. Can be configured as dimmer switch input 80 SEGM_19 O ±5 - - LCD Segment SEGM_18 O ±5 - - LCD Segment SEGM_17 O ±5 - - LCD Segment SEGM_16 O ±5 - - LCD Segment 16 Doc Rev 1.04 Datasheet 11 Aug

9 PinNo Pin Name I/O I(mA) Res HY Pin Description 84 SEGM_15 O ±5 - - LCD Segment SEGM_14 O ±5 - - LCD Segment SEGM_13 O ±5 - - LCD Segment SEGM_12 O ±5 - - LCD Segment SEGM_11 O ±5 - - LCD Segment VDD P LDO power output. A capacitor in the range 0.1μF-10μF must be connected here 90 P v Power Supply 91 P Ground 92 SEGM_10 O ±5 - - LCD Segment SEGM_9 O ±5 - - LCD Segment 9 94 SEGM_8 O ±5 - - LCD Segment 8 95 SEGM_7 O ±5 - - LCD Segment 7 96 SEGM_6 O ±5 - - LCD Segment 6 97 SEGM_5 O ±5 - - LCD Segment 5 98 SEGM_4 O ±5 - - LCD Segment 4 99 SEGM_3 O ±5 - - LCD Segment SEGM_2 O ±5 - - LCD Segment SEGM_1 O ±5 - - LCD Segment SEGM_0 O ±5 - - LCD Segment P v Power Supply 104 P Ground BCKP_7/SEGM_27 /INTD3 BCKP_6/SEGM_26 /INTD2 BCKP_5/SEGM_25 /INTD1 BCKP_4/SEGM_24 /INTD0 I/O ±5 - - LCD Backplane 7. Can be configured as dimmer switch input I/O ±5 - - LCD Backplane 6. Can be configured as dimmer switch input I/O ±5 - - LCD Backplane 5. Can be configured as dimmer switch input I/O ±5 - - LCD Backplane 4. Can be configured as dimmer switch input 109 BCKP_3 O ±5 - - LCD Backplane BCKP_2 O ±5 - - LCD Backplane BCKP_1 O ±5 - - LCD Backplane BCKP_0 O ±5 - - LCD Backplane P Ground 114 DC_COMP O ± Direct Current pin, used in external comparator loop 115 P v Power Supply 116 ENABLE O ± External comparator latch enable signal 117 P Ground 118 DNIN I ±5 - - External comparator negative output pin 119 DIN I ±5 - - External comparator output pin 120 REC_1 O ±5 - - Control Bias Output 1. Used in external comparator loop 121 REC_2 O ±5 - - Control Bias Output 2. Used in external comparator loop 122 REC_3 O ±5 - - Control Bias Output 3. Used in external comparator loop 123 REC_4 O ±5 - - Control Bias Output 4. Used in external comparator loop 124 REC_5 O ±5 - - Control Bias Output 5. Used in external comparator loop 125 REC_6 O ±5 - - Control Bias Output 6. Used in external comparator loop 126 REC_7 O ±5 - - Control Bias Output 7. Used in external comparator loop Doc Rev 1.04 Datasheet 11 Aug

10 PinNo Pin Name I/O I(mA) Res HY Pin Description 127 REC_8 O ±5 - - Control Bias Output 8. Used in external comparator loop 128 P v Power Supply 129 P Ground 130 VRL I (**) - - Analog input Low Voltage Reference 131 VIN I (**) - - Direct-Analog Input Voltage 132 VRH I (**) - - Analog input High Voltage Reference 133 AVD1 P v Analog Power Supply AVS1 P Analog Ground AVD2 P v Analog Power Supply AVS2 P Analog Ground P v Power Supply 138 P Ground 139 P5_3/MISO0 I/O ±5 PU - MISO SPI0 master in / slave out Data 140 P5_2/MOSI0 I/O ±5 PU - MOSI SPI0 master out / slave in Data 141 P5_1/SPICLK0 I/O ±5 PU - SPICLK SPI0 clock input/output 142 P5_0/SS0 I/O ±5 PU - SS SPI0 Slave Select input 143 P3_5/T1 I/O ±5 PU - T1 Timer1 external input 144 P3_4/T0 I/O ±5 PU - T0 Timer0 external input (*) Mandatory to be tied down (**)See application circuit I/O: pin direction I:Input O:output P:Power I(mA): nominal current +:source -:sink X:fixed by external resistor, see application circuits RES: pin pullup/pulldown resistor PU:Internal pullup PD:Internal pulldown HY: input hysteresis Table 1. ADD1010 pin description Doc Rev 1.04 Datasheet 11 Aug

Exposure to the Absolute Maximum Conditions for extended periods may affect device reliability. (VSS = 0 V) Parameter Symbol Rating Unit Supply Voltage -0.5 to 4.0 V Input Voltage VI -0.5 to +0.5( 4.

11 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions given in the Recommended Operating Conditions section. Exposure to the Absolute Maximum Conditions for extended periods may affect device reliability. (VSS = 0 V) Parameter Symbol Rating Unit Supply Voltage -0.5 to 4.0 V Input Voltage VI -0.5 to +0.5( 4.0V) V Output Voltage VO -0.5 to +0.5(<4.0V) V Storage Temperature TST -55 to 125 ºC Junction Temperature TJ -40 to 125 ºC Output Current (*)1 IO ±10 (*)2 ma Notes: (*)1. DC current that continuously flows for 10ms or more, or average DC current. (*)2. Applies to all the pins except EMIT pins. EMIT pins should be only used according to circuit configurations recommended by ADD. ATTENTION Observe ESD Precautions Precautions for handling electrostatic sensitive devices should be taken into account to avoid malfunction. Charged devices and circuit boards can discharge without detection. Doc Rev 1.04 Datasheet 11 Aug

12 2.2 Recommended Operating Conditions Parameter Symbol Rating Min. Typ. Max. Unit Supply Voltage VDEO V VDA Junction Temperature TJ ºC Doc Rev 1.04 Datasheet 11 Aug

13 2.3 DC Characteristics (=3.3v ± 0.3v, VSS=0v, TJ=-40 to 125 C) Parameter Condition Symbol Rating Min. Typ. Max. Unit Supply Voltage H-level Input Voltage (3.3v CMOS) VIH L-level Input Voltage (3.3v CMOS) VIL H-level Output Voltage 3.3v I/O IOH=-100μA VOH V L-level Output Voltage 3.3v I/O IOL=100μA VOL H-level Output V-I Characteristics 3.3v I/O =3.3±0.3 IOH Refer to Annex1 ma L-level Output V-I Characteristics 3.3v I/O =3.3±0.3 IOL Refer to Annex1 Internal Pull-up Resistor (*)1 3.3v I/O Rpu kω Internal Pull-down Resistor (*)1 3.3v I/O Rpd kω Junction Temperature TJ ºC Notes: (*)1. Only applicable to pins with internal pulling. See related table. Doc Rev 1.04 Datasheet 11 Aug

14 2.4 Power Consumption External Driver: ADD1010 SoC consumption values when working with an external driver (see Analog Front End Example section). Parameter Condition Symbol Rating Min. Typ. Max. Unit Power Consumption in reception TA=25 C, =3.3v P Rx mw Power Consumption in transmission TA=25 C, =3.3v P Tx mw Power Consumption (worst case) TA=85 C, =3.6v P mw Internal Driver: ADD1010 SoC consumption values when working with ADD1010 internal driver. Parameter Condition Symbol Rating Min. Typ. Max. Unit Power Consumption in reception ADD1010 working in Internal Driver mode TA=25 C, =3.3v ID_P Rx mw Power Consumption in transmission ADD1010 working in Internal Driver mode TA=25 C, =3.3v ID_P Tx mw Power Consumption ADD1010 working in Internal Driver mode (worst case) TA=85 C, =3.6v ID_P * 1, * 2 mw *1.Measured using recommended external configuration. *2.RL=0R (Load Impedance=0Ω). Doc Rev 1.04 Datasheet 11 Aug

15 2.5 Thermal data Parameter Symbol LQFP144 Unit Thermal resistance junction-ambient steady state R Theta-ja 53 *(1) ºC/W 37 *(2) Notes: 1. Mounted on 2-layer PCB. 2. Mounted on 4-layer PCB. Theta-ja is calculated based on a standard JEDEC defined environment and is not reliable indicator of a device s thermal performance in a non-jedec environment. The customer should always perform their own calculations/simulations to ensure that their system s thermal performance is sufficient. Doc Rev 1.04 Datasheet 11 Aug

16 2.6 Oscillator Figure 3. Internal Oscillator Cell Parameter Test Condition Symbol Rating Min. Typ. Max. Unit Crystal Oscillator frequency fundamental Xtal MHz External Oscillator Capacitance See figure Cx pf H-level Input Voltage XVIH L-level Input Voltage XVIL V External Oscillator Parallel Resistance Rp not needed External Oscillator Series Resistance Rs not needed Ω Notes: 1. The crystal should be located as close as possible to CLKEB and CLKEA pins. 2. Recommended value for Cx is 18pF. This value may depend on the specific crystal characteristics. 3. Crystal Stability/Tolerance/Ageing values must be selected according to standard PRIME requirements. Doc Rev 1.04 Datasheet 11 Aug

17 Crystal oscillation cell Internal output pin Oscillation control input pin CLKEA Oscillation circuit input pin CLKEB Oscillation control output pin Figure 4. Internal Oscillator Cell Doc Rev 1.04 Datasheet 11 Aug

18 2.7 Power-on In power-on, D_INIT should be released before asynchronous reset signal RSTA in order to ensure proper system start up. Not minimum time is required between both releases, Δt > 0, so a simple RC circuit is enough to satisfy this requirement. Doc Rev 1.04 Datasheet 11 Aug

19 3. Mechanical data 144-pin plastic LQFP (16x16mm) Pb-free, RoHS compliant. Ambient Temperature Range: -40ºC to +85ºC. Ordering Code: ADD1010AQF144 Doc Rev 1.04 Datasheet 11 Aug

20 3.1 Recommended mounting conditions Conditions of Standard Reflow Items Method Contents IR(Infrared Reflow) / Convection Times 2 Floor life Before unpacking From unpacking to second reflow In case over period of floor life Please use within 2 years after production Within 8 days Baking with 125 C +/- 3 C for 24hrs +2hrs/-0hrs is required. Then please use within 8 days. (please remember baking is up to 2 times) Floor life condition Between 5 C and 30 C and also below 70%RH required. (It is preferred lower humidity in the required temp range.) Temperature Profile H rank: 260 C Max (a) Average ramp-up rate: 1 C/s to 4 C/s (b) Preheat & Soak: 170 C to 190 C, 60s to 180s (c) Average ramp-un rate: 1 C/s to 4 C/s (d) Peak temperature: 260 C Max, Up to 255 C within 10s (d ) Liquidous temperature: Up to 230 C within 40s or Up to 225 C within 60s or Up to 220 C within 80s (e) Cooling: Natural cooling or forced cooling *Temperature on the top of the package is measured Doc Rev 1.04 Datasheet 11 Aug

21 3.1.2 Manual Soldering Items Contents Floor life Before unpacking From unpacking to Manual Soldering Please use within 2 years after production Within 2 years after production (No control required for moisture adsorption because it is partial heating) Floor life condition Solder Condition Between 5 C and 30 C and also below 70%RH required. (It is preferred lower humidity in the required temp range.) Temperature of soldering iron: Max 400 C, Time: Within 5 seconds/pin *Be careful for touching package body with iron Doc Rev 1.04 Datasheet 11 Aug

2 pinout table with Nominal Current I(mA)=±5 Condition: MIN Process=

22 4. Annex 1 V I Characteristics 3.3 Vstandard CMOS IO L, M type Pins marked in section 1.2 pinout table with Nominal Current I(mA)=±5 Condition: MIN Process= Slow Tj= 125 C = 3.0 V TYP Process=Typical Tj= 25 C = 3.3 V MAX Process=Fast Tj= 40 C = 3.6 V Doc Rev 1.04 Datasheet 11 Aug

23 V I Characteristics 3.3 Vstandard CMOS IO H, V type Pins marked in section 1.2 pinout table with Nominal Current I(mA)=±10 Condition: MIN Process= Slow Tj= 125 C = 3.0 V TYP Process=Typical Tj= 25 C = 3.3 V MAX Process=Fast Tj= 40 C = 3.6 V Doc Rev 1.04 Datasheet 11 Aug

24 V I Characteristics 3.3 Vstandard CMOS IO H, V type Pins marked in section 1.2 pinout table with Nominal Current I(mA)=±X Condition: MIN Process= Slow Tj= 125 C = 3.0 V TYP Process=Typical Tj= 25 C = 3.3 V MAX Process=Fast Tj= 40 C = 3.6 V v Doc Rev 1.04 Datasheet 11 Aug

25 Doc Rev 1.04 Datasheet 11 Aug of Annex ADD1010 Application circuit example 2 3 VPD 4 TEST2 5 TDI 6 TDO 7 TCK 8 TMS 9 TRST 10 D_INIT 11 RSTA 12 PROG 13 SECURED 14 EW 15 DEBUG 16 VDD CLKEB CLKEA PLL VDE0 24 VDE0 25 VSS0 26 LDO_PD 27 VDD VSENSE 31 PSENSE 32 VNR 33 TRIAC3 34 TRIAC2 35 TRIAC0 37 P55/TXD1/INTA1 38 P54/RXD1/INTA0 39 P47/T2EX/INTA3 40 P46/T2/INTA2 41 P17/SSN EMIT0 45 EMIT1 46 EMIT EMIT3 50 EMIT4 51 EMIT5 52 EMIT EMIT7 56 EMIT8 57 EMIT9 58 EMIT EMIT11 62 EMIT P31/TXD0 66 P30/RXD0 67 P45/MISO1/INTB3 68 P44/MOSI1/INTB2 69 P43/SPICLK1/INTB1 70 P42/SS1/INTB0 71 P40/RXD SEGM23/INTC3 76 SEGM22/INTC2 77 SEGM21/INTC1 78 SEGM20/INTC0 79 SEGM19 80 SEGM18 81 SEGM17 82 SEGM16 83 SEGM15 84 SEGM14 85 SEGM13 86 SEGM12 87 SEGM SEGM10 92 SEGM9 93 SEGM8 94 SEGM7 95 SEGM6 96 SEGM5 97 SEGM4 98 SEGM3 99 SEGM2 100 SEGM1 101 SEGM BCKP7/SEGM27/INTD3 105 BCKP6/SEGM26/INTD2 106 BCKP5/SEGM25/INTD1 107 BCKP4/SEGM24/INTD0 108 BCKP1 111 BCKP DC_COMP ENABLE DNIN 118 DIN 119 REC1 120 REC2 121 REC3 122 REC4 123 REC5 124 REC6 125 REC7 126 REC VRL 130 VIN 131 VRH 132 AVD1 133 AVS1 134 AVD2 135 AVS P53/MISO0 139 P52/MOSI0 140 P51/SPICLK0 141 P50/SS0 142 P35/T1 143 P34/T0 144 P33/INT1 1 TRIAC1 36 P41/TXD2 72 BCKP3 109 BCKP2 110 U51 ADD1010 BP4 BP5 BP6 BP7 P34/T0 P35/T1 P46/T2 P43/SPICLK1 P40/RXD2 P42/SS1 DEBUG PSENSE VSENSE SEG22 BP0 BP1 BP2 BP3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG23 P47/T2EX P31/TXD0 P30/RXD0 P45/MISO1 P41/TXD2 P44/MOSI1 PROG P55/TXD1 P54/RXD1 P33 C70 C69 C67 C60 C59 C58 C73 C72 C71 C80 C78 C77 C76 C75 C61 10uF R53 10K C62 10uF R54 1K R58 NM R57 0R 1 2 Y MHz C63 18pF C65 18pF C66 10uF C64 10uF C74 10uF C79 10uF R50 180R R51 130R ADC1 R52 0R C53 10uF C54 F C55 R66 33R R67 33R R68 33R R69 33R R70 33R R71 33R WE SECURED RESET SI 5 SCK 6 CS 1 WP 3 RESET 7 SO 2 8 VSS 4 U50 M25PE40 SS0 SPICLK0 MOSI0 MISO0 MISO0 C50 MOSI0 SPICLK0 SS0 1 DQ 2 U52 DS2401 D50 GREEN R62 220R TXRX R60 0R W50 Jumper R55 1K C56 C57 C68 C52 C51 F VRH VRL BP7 BP6 BP5 BP4 RESET P34/T0 P35/T1 P46/T2 P43/SPICLK1 P40/RXD2 P42/SS1 P33 PSENSE VSENSE BP0 P47/T2EX P31/TXD0 P30/RXD0 P45/MISO1 P41/TXD2 P44/MOSI PROG P55/TXD1 P54/RXD1 BP1 N SEG20 SEG18 SEG16 SEG14 SEG12 ADC1 SEG8 SEG6 SEG4 SEG2 SEG0 TXRX P SEG23 SEG22 SEG21 SEG19 SEG17 SEG15 SEG13 SEG11 SEG10 SEG9 SEG7 SEG5 SEG3 SEG1 DEBUG BP2 BP3 N P VNR TRIAC3 TRIAC2 TRIAC1 TRIAC0 VNR TRIAC0 TRIAC1 TRIAC2 TRIAC3 R63 33R R64 33R R65 33R R72 33R R73 33R R74 33R 1 Initial release M.C. R61 4K7 2 Updated clock circuit M.C.

26 5.2 Analog Front End example Optional discharge RX CIRCUIT TX CIRCUIT PHASE NEUTRAL L N R9 270K R17 270K R18 270K C4 150nF L1 10uH TVS1 SM6T15CA TXRX T1 5024X044 TXRX R15 10K Q2 NTR4003NT1G C81 4.7nF R1 1K C6 47nF D1 PMBD V R12 10K R11 10K L3 68uH C8 68nF C1 C2 100pF L2 100uH ADC1 C5 68nF R5 10K R7 10K 16V D3 BAT54S C9 16V 16V C10 100uF R2 3K D2 BAT54 Q1 FDC6420C R10 3K D4 BAT54 R3 10K C3 C7 R14 10K 3V3 R8 10K R13 10K 3V3 R4 10K R6 10K P N P N TX/RX FILTER SELECT Doc Rev 1.04 Datasheet 11 Aug of 26

Document information. 1000B, Datasheet. Abstract

Document information. 1000B, Datasheet. Abstract Doc Rev 1.05 Datasheet 11-Aug-2010 Document information Info Author Keywords Content J.G. 1000B, Datasheet Abstract Revision History Revision Date Description Author 1.03 2010-03-29 Second revision J.G.