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1 %URDGFRP&DOLVWR Π$0XOWL&KDQQHO0XOWL6HUYLFH &RPPXQLFDWLRQV3ODWIRUP John Nickolls L.J. Madar III Scott Johnson Viresh Rustagi Ken Unger Mustafiz Choudhury Broadcom Corporation 1 Calisto Hot Chips 2002

2 &DOLVWR Π2XWOLQH Communications gateways Multi-channel, multi-service, real-time Platform architecture Cluster architecture SpiceEngine vector DSPs Shared memory Multi-channel I/O Implementation Performance Summary 2 Calisto Hot Chips 2002

3 0XOWL&KDQQHO&RPPXQLFDWLRQV Cable, xdsl Access Gateways Universal Port Gateway (RAS) VoDSLAM PSTN IP Class 4 Switch Packet Network ATM/FR/IP VoIP/DSL/DLC CO/PBX Trunking Gateway Enterprise Voice/Video 3G Wireless 3 Calisto Hot Chips 2002

4 &DOLVWR Œ *DWHZD\%ODGH Packet Backplane Interconnect Backplane Interface Packet Switch Circuit Interface *DWHZD\ %ODGH Circuit Backplane Interconnect Carrier-class/enterprise gateways Voice over packet, media, fax, data, wireless, trunking, remote access Require many diverse services Require 1000 s of channels per blade Severely limited power budget Prior gateways were low density Complex designs, many different chips ÎCalisto is a gateway on a chip Integrates DSPs, Us, RAMs, I/O Programmable multi-service platform Supports channels per chip Simple Calisto chip array Enables over 2,016 channels per blade ÎEfficient low-power design 4 Calisto Hot Chips 2002

5 0XOWL6HUYLFH*DWHZD\6WDFN Real-Time OS Packet Network RTP/UDP or AAL2 Jitter Buffer Voice-band Signaling Voice Detect/Noise Gen Voice Coder Fax/Data Relay Fax/Data Modem Conference/Mix Service Tone Service Call Discriminator Echo Cancel PCM or AAL1 Circuit Network Circuit Network MCycles/S OS: Complex service suite Minimize assembler ÎFlexible compiled C software Any service, any port, any time Total program image KB ÎSingle-image shared memory Compute + memory demand DSP/RISC MS/channel 4 20 KB inter-frame data/channel ÎBalanced compute and memory Mix of DSP, packet, OS work No time for DSP task + packet task ÎHybrid DSP/RISC processors ÎDedicated OS processors Total: MS required per channel 5 Calisto Hot Chips 2002

6 0DQ\5HDOWLPH3HULRGLF7DVNV Process frames periodically for all channels Service-specific frame period: 5, 6, 10, 16.7, 20, or 30 msec 800 to 3,000 tasks/sec per DSP, or 4 to 15 tasks per frame period ÎEvery service stack can be executed any time Requires low latency processing delay with low jitter Incremental latency of 1 2 msec, jitter under 250 µsec ÎCombine all processing in single per-frame task, minimize overhead Packet ι Circuit and Packet η Circuit Get ι pkt 1 JB ι pkt 1 Accumulate η frame f1 Get ι pkt 2 Task ο f1 Jitter Buffer ι pkt 2 Put η pkt 1 Accumulate η frame f2 Put η pkt 2 Accumulate η frame f3 Channel task flow 0 msec 5 msec 10 msec 15 msec Task ο f2 Generate ι frame f1 Get ι pkt 3 JB ι pkt 3 Task ο f3 Generate ι frame f2 6 Calisto Hot Chips 2002

7 0DSSLQJ$SSOLFDWLRQ$WWULEXWHV $SSOLFDWLRQ$WWULEXWH Many independent channels Many diverse services High channel density Digital signal processing Network packet processing Mix of DSP and packet work Low latency, low jitter Î Î Î Î Î Î Î Î 3ODWIRUP$UFKLWHFWXUH Many processors, many parallel per-channel tasks Programmable, primarily in C; large instruction memory, fast cache fill Minimize power, share resources Vector data parallelism, operand throughput, memory bandwidth Task parallelism, sequential protocols Hybrid DSP/RISC processors Consistent task run time, minimize task overhead and contention 7 Calisto Hot Chips 2002

8 &DOLVWR%&0$UFKLWHFWXUH Clusters partition functions CM MB 1 MB Total Cluster Memory Task data, I/O buffers, stacks 4 Cluster Processors Run OS and supervise cluster 16 SpiceEngine DSPs Run DSP/packet tasks 5 Memory and I/O Bridges Share resources efficiently SM 768 KB Shared Memory Single OS & application image 4 Multi-channel I/O interfaces Main Processor I/O MP Hub Runs OS and supervises chip Chip synchronization Hub JTAG BOOT 2 Packet I/O 2 TDM I/O Cluster Memory 256 KB Cluster Memory 256 KB MB MB Shared Memory 768 KB Hub MP SDRAM MB MB Cluster Memory 256 KB Cluster Memory 256 KB 8 Calisto Hot Chips 2002

9 &OXVWHU$UFKLWHFWXUH 256 KB Cluster Memory Shared by, s, MB, I/O Task, OS, I/O communication Pipelined CM switch CM Low latency load pipeline Minimal memory contention Cluster synch hub Hub 4 SpiceEngine DSP pool Next available runs task CM No channel affinity Æ min latency RISC Cluster Processor Schedules tasks and output Services interrupts and input Frees s of overhead I/O Bus IOB CM KB Bank 0 32 D$ Chip Hub BIF 32 Shared Memory Switch Port MB 192 Cluster Memory (CM) Pipelined Crossbar Switch CM 32 KB Bank 1 32 Hub CM 32 KB Bank 2 CM 32 KB Bank 3 CM 32 KB Bank 4 CM 32 KB Bank 5 CM 32 KB Bank 6 32 CM KB Bank 7 9 Calisto Hot Chips 2002

10 6SLFH(QJLQH Π9HFWRU'63 MUL 17 x 17 Instruction Cache Fill Interface Vector Registers 1 KB MReg 33 Configuration Registers 8 x 128 Vector Address Units ALU 40/32/16 VAU Regs 16 x 10 Vector Load/Store SHIFT 40/32/16 Accumulators 2 x 40 Instruction Cache 384 x 24 Registers 16 x 32 BITU 32 Cluster Memory Interface Load/ Store ALU 32 MMU Vector registers Fast structured data access Reduce cluster memory demand Fixed-point DSP pipeline Configurable 16/32/40 bits 10 Parallel operations/cycle ITU saturation arithmetic Efficient C compiler target Simple single-mac datapath Narrow 24-bit instruction issue Wide configuration register issue for loops and vector operations Fewer cycles than comparable DSPs, using primarily compiled C J. Nickolls, Broadcom SpiceEngine: A Vector Signal Processor, Microprocessor Forum, Oct. 18, Calisto Hot Chips 2002

11 :K\9HFWRU5HJLVWHUV" VAU vw VAU va vw Write 32/16/8 y[0] y[2] y[4] y[6] x[0] x[2] x[4] x[6] c[0] c[2] c[4] va Read vm Load/Store m[0] m[1] m[2] 32/16/8 y[1] y[3] y[5] y[7] x[1] x[3] x[5] x[7] c[1] c[3] c[5] 32/16/8 32/16/8 vb Read VAU vm VAU vb Fast structured data access Vectors, arrays, tables, lists Multi-port vector register access Compiler-scheduled preload Efficient DSP performance Vector preload covers memory latency, unlike data cache miss Reduce DSP memory accesses and power: O(N T) Æ O(N + T) Vector address unit (VAU) Low overhead strided address Vector registers & configurations Sustain 1 cycle per MAC with minimal memory bandwidth 11 Calisto Hot Chips 2002

12 9HFWRUL]LQJ&&RPSLOHU 7RROV Multi-level loop vectorization Automatic and manual vector register allocation Vector register load scheduling Multi-level vector stride detection Dynamic configuration generation Minimum-cost configuration generation, load scheduling Signal processing, cross-module optimizations Value range optimization, saturation algebra Intrinsic deduction, inlining, constant propagation Redundant store elimination (e.g. ITU overflow flag) High-efficiency signal/packet processing in C Typical ITU reference C within 2x cycles of hand-coded assembler ÎEnables complete C service stacks, including DSP and network code Multi-channel debugging, profiling, performance tuning tools 12 Calisto Hot Chips 2002

13 &DFKH)LOOIURP6KDUHG0HPRU\ SDRAM Controller IOB I/O Bus IOB 32 Shared Memory 192 KB Bank 0 Shared Memory Pipelined Cross Bar Switch 128 MB MP Cluster 0 D$ BIF Hub MB Shared Memory 192 KB Bank Cluster 1 CM 1 Cluster 3 MB Shared Memory 192 KB Bank Cluster Memory (CM) Shared Memory 192 KB Bank Cluster 2 Cluster 4 CM 2 MB MB CM 4 Shared Memory SM Single program image, 768 KB Fills & instruction caches Interleaved 4 banks x 128 bits Pipelined crossbar switch Delivers full 512 bits per cycle Typical utilization 50% 80% Supports I/O bus and SDRAM instruction cache fill Memory Bridge DMA engine Cache reduces memory demand 192 byte line amortizes latency Average miss cost: I SM MB 13 Calisto Hot Chips 2002

14 0XOWL&KDQQHO6FDWWHU*DWKHU,2 Boot Port IOB IOB Cluster 2 D$ Packet I/O Port CM 2 Ingress BIF Hub Packet I/O Port IOB I/O Arbiter Cluster 3 Cluster 4 CM 3 Cluster 1 TDM I/O Port IOB CM 4 Cluster Memory (CM) 1 TDM I/O Port Egress IOB SM MB Packet and cell network I/O IP and ATM networks 100 Mbps full duplex, pin-efficient TDM sample stream I/O Circuit and AAL1 networks Bit-serial ports Multi-channel scatter/gather Ingress/egress ring buffers in Cluster or Shared Memory Classify ingress packet/cell, DMA to ring buffer Assemble egress packets from chained DMA buffers Ring buffer synchronization 14 Calisto Hot Chips 2002

15 (IILFLHQF\IRUORZSRZHU Scalable multi-processor parallelism Many small DSPs exploit channel task parallelism Higher efficiency than fewer large VLIW DSPs Shared program memory Significant reduction in area and power vs. DSP farms Instruction caches reduce memory demand Cluster memory shared by DSPs and Enables scalable DSP array, pool scheduling Vector DSPs reduce memory demand Avoid task preemption, minimize overhead No cycles wasted on DSP task preemption Balanced DSP/RISC MS and memory Channel density typically limited equally 15 Calisto Hot Chips 2002

16 &DOLVWR Œ %&0,PSOHPHQWDWLRQ Implementation 130 M transistors.13µm CMOS -G 166 MHz clock 1.2 V core, 2.5 V I/O 1.2 Watts 239 BGA 19x19 mm Q1/2002 production Low power design Extensive clock gating Low power pipelined busses RAM defect repair Redundant rows and columns Manufacturing test, laser repair 16 SpiceEngine DSPs 2.7 GIPS 2.7 GMACS, 26.6 GOPS 16 KB Vector registers 18 KB Cache 5 RISC Processors 830 MIPS 40 KB Cache 768 KB Shared Memory 10.6 GB/sec bandwidth 1 MB Cluster Memory 18.6 GB/sec bandwidth Multi-channel I/O 16 Calisto Hot Chips 2002

17 17 Calisto Hot Chips 2002 &DOLVWR Π%&0

18 26/RZ/DWHQF\6FKHGXOLQJ Multi-channel real-time OS Develop application service stack for single channel OS maps each channel to a periodic per-frame channel task OS/MMU restricts tasks to access only assigned channel memory Schedule per-frame channel tasks in a periodic window Combine up/down, DSP/packet processing in one per-frame task Run each per-frame task to completion, within known deadline Zero cycles wasted on task preemption OS schedule minimizes longest processing latency Stagger channel tasks relative to input frames, schedule output Highest priority task gets next available SpiceEngine ÎAchieves less than 250 µsec output packet jitter OS distributed across clusters Each manages its cluster resources 18 Calisto Hot Chips 2002

19 %&0*DWHZD\3HUIRUPDQFH Calisto Gateway xchange software ÎComplete carrier-class VoP gateway service suite ITU bit-exact vocoders, G.7xx, GSM, BroadVoice, 64/128 msec adaptive line echo cancellation (ECAN) Voice activity detection, comfort noise generation DTMF tone detect/generate, tone relay, fax/modem detect Fax relay, Fax modems, T.38 FoIP, AAL2 Annex M Packet interface: IP/RTP/UDP, ATM AAL1/2/5, adaptive jitter buffer Conference mixing, in-band signaling, remote test, encryption Breakthrough density for VoP Gateways 240/220 channels G.711 VoP, 32/64 msec ECAN, 5 mw/channel 184 channels G.711 VoP, 128 msec ECAN 120 channels G.729a VoP, 64 msec ECAN 104 channels G.729ab VoP, 128 msec ECAN, T.38 Fax relay ÎEnables 2,016 channel OC-3 gateway blade with 10 chips 19 Calisto Hot Chips 2002

20 &DOLVWR Œ 2&*DWHZD\%ODGH Simple array of 10 Calisto chips Carrier-class multi-service Gateway xchange software ÎEnables 2,016 channel OC-3 packet voice gateway blade 20 Calisto Hot Chips 2002

21 &DOLVWR Œ 6XPPDU\ Multi-channel multi-service communications platform Integrated multi-processor system Balanced performance and memory Consistent real-time performance Flexible C programmable platform Efficient low-power architecture Appropriate use of parallelism Shared resources Vector DSPs reduce memory usage Low power design and implementation Tightly coupled OS and software Enables carrier-class gateways Calisto : 16 SpiceEngine DSPs 5 Control Processors Multi-channel I/O 1.75 MB Memory.13µm CMOS 166 MHz 1.2V, 1.2 Watts 239 BGA 19x19 mm Q1/2002 production 21 Calisto Hot Chips 2002