! Memory Overview. ! ROM Memories. ! RAM Memory " SRAM " DRAM. ! This is done because we can build. " large, slow memories OR

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1 ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 2: April 5, 26 Memory Overview, Memory Core Cells Lecture Outline! Memory Overview! ROM Memories! RAM Memory " SRAM " DRAM 2 Memory Overview A Typical Computer System CPU L-D L-I L2-Cache Video RAM GPU AGP bus USB bus System bus Ch Memory Controller I/O Controller Other buses Ch 2 PCI bus Disk Adapter DRAM DIMM DRAM DIMM Ethernet Adapter 4 CPU Memory Hierarchy Locality and Cacheing CPU Chip L on-cpu cache off-chip cache memory L2 L3 L4 k to 64 k SRAM (register file) 64k to 4M 4M to 32M SRAM or DRAM 8M! Memory hierarchies exploit locality by cacheing (keeping close to the processor) data likely to be used again! This is done because we can build " large, slow memories OR " small, fast memories BUT " we can t build large, fast memories! If hierarchy works, we get the illusion of SRAM access time with disk based memory capacity. " SRAM (static RAM) ns access time, very expensive (on-cpu faster) " DRAM (dynamic RAM) ns, cheaper " Disk -- access time measured in milliseconds, very cheap 5 6

2 Semiconductor Memory Classification Memory Architecture: Core M bits M bits Random Access SRAM DRAM RWM NVRWM ROM Non-Random Access FIFO LIFO Shift Register CAM EPROM E 2 PROM FLASH Mask-Programmed Programmable (PROM) N Words S S S 2 S N-2 S N_ Word Word Word 2 Word N-2 Word N- Storage Cell N words => N select signals Too many select signals A A A K- Decoder S Word Word Word 2 Word N-2 Word N- Storage Cell Decoder reduces # of select signals K = log2n Memory Architecture: Decoders Array-Structured Memory Architecture M bits M bits Problem: ASPECT RATIO or HEIGHT >> WIDTH S Word S Word 2 L-K Bit Line Storage Cell N Words S S 2 S N-2 S N_ Word Word 2 Word N-2 Word N- Storage Cell A A A K- Decoder Word Word 2 Word N-2 Word N- Storage Cell A K A K+ A L- Row Decoder Sense Amplifiers / Drivers Word Line M.2 K Amplify swing to rail-to-rail amplitude N words => N select signals Too many select signals Decoder reduces # of select signals K = log2n A A K- Column Decoder Selects appropriate word MOS NOR ROM ROM Memories [] [] [2] [3] [] [] [2] [3] 2

3 MOS NOR ROM MOS NOR ROM [] [] [] [] [2] [3] [2] [3] [] [] [2] [3] [] [] [2] [3] Non-Volatile Memory ROM Contact-Mask Programmable ROM PseudonMOS NOR gate 5 6 Contact-Mask Programmable ROM MOS NAND ROM [] [] [2] [3] [] [] [2] [3] All word lines high by default with exception of selected row 7 3

4 MOS NAND ROM MOS NAND ROM [] [] [2] [3] [] [] [2] [3] [] [] [] [] [2] [2] [3] [3] All word lines high by default with exception of selected row All word lines high by default with exception of selected row Read-Write Memories (RAM) RAM Memories STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (-3 transistors/cell) Slower Single Ended 6T SRAM Cell 6-transistor CMOS SRAM Cell! Cell size accounts for most of memory array size! 6T SRAM Cell " Used in most commercial chips " Data stored in cross-coupled inverters! Read: " Precharge, bit " Raise word! Write: " Drive data onto, " Raise bit_b M 23 4

5 6-transistor CMOS SRAM Cell 6-transistor CMOS SRAM Cell (=) Assume bitlines precharged to Vdd VDD Read Operation VDD M M 6-transistor CMOS SRAM Cell C bit = M = (=) C bit (=) Write Operation Write to cell VDD =, =VDD M 6T SRAM Cell = =! Read: " Precharge, " Raise! Write: " Drive data onto, " Raise word bit bit_b = M =! Design Strategy? " () data-read operation should not destroy stored data " (2) data-write operation should allow modification of stored data 3 5

6 Assume is stored (=) Assume is stored (=) V must not exceed V T,n so stays OFF SRAM Read! Precharge both bitlines high! Then turn on wordline,! One of the two bitlines will be pulled down by the cell bit word! Ex: A =, A_b = P P2 " discharges, stays high " But A bumps up slightly! Read stability " A must not flip " N >> N word A_b A bit N time (ps) bit_b A N N3 A_b bit_b N4 33 V,max <V T,2 Assume is stored (=) Assume is stored (=) Assume is stored (=) If =5V, V T,n =V =.778 6

7 6T SRAM Cell Assume is stored (=)! Read: " Precharge, " Raise! Write: " Drive data onto, " Raise word bit bit_b If =V, V T,n =.2V =.778! Design Strategy? " () data-read operation should not destroy stored data " (2) data-write operation should allow modification of stored data 38 (=), Write (=), Write V 2 stays below V T,n, by Read design strategy (=), Write (=), Write V must reduce below V T,n so turns OFF V = V T,n 7

8 (=), Write (=), Write If =5V, V T,n =V, µ n /µ p =2 =.389 If =V, V T,n =.2V, µ n /µ p =2 =.389 DRAM 3-Transistor DRAM Cell! Smaller than SRAM! Require data refresh to compensate for leakage 2 W W R R M X X VDD-VT C S 2 VDD-VT ΔV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a = V W-V Tn 45 -Transistor DRAM Cell DRAM Cell Observations C M C S X VDD/2 C ΔV V V ( PRE V BIT V ) S = = PRE C S + C Write "" Read "" V T sensing VDD/2 Write: CS is charged or discharged by asserting and. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 25 mv. T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than. 8

9 Ideas Admin! Memory for compact state storage! Share circuitry across many bits! HW 8 due 4/7! EC (from HW 7) due 4/ " Minimize area per bit # maximize density! To keep area down aggressively use: " Pass transistors, Ratioing " Precharge, Amplifiers! Final Project " Teams of up to 3 people " Don t work alone! " Report your teams to me by 4/ " Design memory (SRAM or DRAM) " OR propose your own project by 4/ " Posted before Thursday class " Due 4/26 (last day of class) " Everyone gets an extension until 5/6 (day of final exam)