EDA Software Support. Introduction

Transcription

1 January 1998, er. 7 Introduction Seamless design flow and high-quality integration of third party EDA tools are essential to the continued success of programmable logic deices (PLDs). Thus, Altera has established the Altera Commitment to Cooperatie Engineering Solutions (ACCESS SM ) program. Through the ACCESS program, Altera and key EDA endors jointly deelop and market next-generation high-leel design tools and methodologies. Altera proides EDA partners with critical technical information and assistance, and ACCESS partners dedicate resources to ensure the best quality design results for Altera architectures. The ACCESS program proides a total solution that allows designers to generate and erify multiple design reisions in a single day, greatly reducing the product deelopment cycle. Altera has been a leader in support of industry standards, such as EDIF, VHDL, Verilog HDL, VITAL, and the library of parameterized modules (LPM). Altera has also made a commitment to support current ACCESS partner design flows. f For more information on software support proided by Altera, see the MAX+PLUS II Programmable Logic Deelopment System & Software Data Sheet in this data book. This document identifies the type of product(s) aailable from each ACCESS partner, i.e., design entry, compilation/synthesis, and simulation/erification. These products either support Altera deices directly or proide an interface to the MAX+PLUS II deelopment software. In addition, the MAX+PLUS II software contains the necessary interfaces and libraries to support many EDA tools. Altera recommends contacting EDA software manufacturers directly for details on product features, specific deice support, and product aailability. Table 1 lists third-party tool support for Altera deices. f Go to the Altera world-wide web site ( for up-to-date information on: ACCESS partner support for Altera deices. MAX+PLUS II ACCESS Key Interface Guidelines for Cadence, Mentor Graphics, Synopsys, Viewlogic, and other EDA endors. Altera Corporation 719 A-GN-EDA-07

2 Table 1. Third-Party Tool Support for Altera Deices (Part 1 of 3) Company Design Entry Compilation/ Synthesis ACCEL Technologies, Inc. TEL: (619) FAX: (619) Accolade Design Automation, Inc. TEL: (425) FAX: (425) ACEO Technology TEL: (510) FAX: (510) ACUGEN Software, Inc. TEL: (603) FAX: (603) ALDEC, Inc. TEL: (805) FAX: (805) Cadence Design Systems, Inc. TEL: (408) FAX: (408) Exemplar Logic, Inc. TEL: (510) FAX: (510) Flynn Systems Corporation TEL: (603) FAX: (603) IK Technology Corporation, Ltd. (Japan) TEL: (81) FAX: (81) IKOS Systems, Inc. TEL: (408) FAX: (408) i-logix, Inc. TEL: (508) FAX: (508) Simulation/ Verification 720 Altera Corporation

3 Table 1. Third-Party Tool Support for Altera Deices (Part 2 of 3) Company Design Entry Compilation/ Synthesis ISDATA GmbH (Germany) TEL: (49) 721/ FAX: (49) 721/ Mentor Graphics Corporation TEL: (503) FAX: (503) MINC, Incorporated TEL: (719) FAX: (719) Model Technology, Inc. TEL: (503) FAX: (503) OrCAD, Inc. TEL: (503) FAX: (503) Sophia Systems and Technology TEL: (408) FAX: (408) Summit Design, Inc. TEL: (503) FAX: (503) Synario Design Automation TEL: (425) SYNARIO FAX: (425) Synopsys, Inc. TEL: (650) FAX: (650) Synplicity, Inc. TEL: (408) FAX: (408) Veda, Inc. TEL: (800) 600-VEDA FAX: (408) Simulation/ Verification Altera Corporation 721

4 Table 1. Third-Party Tool Support for Altera Deices (Part 3 of 3) Company Design Entry Compilation/ Synthesis VeriBest Incorporated TEL: (650) FAX: (650) Viewlogic Systems, Inc. TEL: (508) FAX: (508) Simulation/ Verification Interfaces The MAX+PLUS II deelopment software fully supports the following design enironments and proides interfaces to these tools: Cadence Logic Workbench and Design Framework II Mentor Graphics Falcon Framework Synopsys Viewlogic Poweriew and Workiew Office The features supported in the Cadence, Mentor Graphics, Viewlogic, and Synopsys interfaces with the MAX+PLUS II software are summarized in the sections below. Altera/Cadence Interface By combining Cadence design entry, synthesis, and erification tools (i.e., Logic Workbench and Design Framework II) with the MAX+PLUS II software, designs can be implemented in any Altera PLD. The Altera/Cadence interface supports a top-down or mixed-leel design methodology. Designs can be entered as a mixture of schematics, VHDL, and Verilog HDL. The Altera/Cadence interface supports the following features: Fully integrated design enironment Easy-to-use, top-down design enironment Schematic, Verilog HDL, or VHDL design entry EDIF netlist files that contain timing information for simulation LPM, ersion VITAL-compliant library RAM/ROM support Design description with architecture-independent design entry libraries Altera-proided gencklk utility, which generates simulation models deice selection, fitting, and multi-deice partitioning 722 Altera Corporation

5 Altera/Mentor Graphics Interface By combining Mentor Graphics design entry, synthesis, and erification tools (i.e., Falcon Framework) with the MAX+PLUS II software, designs can be implemented in any Altera PLD. The Altera/Mentor Graphics design flow supports a top-down or mixedleel design methodology. Designs can be entered as a mixture of schematics and VHDL. The Altera/Mentor Graphics interface supports the following features: Fully integrated design enironment Easy-to-use, top-down design enironment Schematic design entry Industry-standard behaioral design entry with VHDL (supporting both IEEE Std and ) and the Altera Hardware Description Language (AHDL), including syntax coloring and HDL templates in the MAX+PLUS II Text Editor VITAL-compliant library LPM, ersion RAM/ROM support Altera-proided gencklk utility, which generates simulation models for ClockLock and ClockBoost features Design description with architecture-independent design entry libraries deice selection, fitting, and multi-deice partitioning Altera/Synopsys Interface The Altera/Synopsys interface brings high-leel design methodology to high-density programmable logic. This interface contains Altera synthesis and simulation libraries, which describe logic functions that can be used to implement designs in Altera PLDs using FPGA or Design Compiler. The Altera/Synopsys interface supports the following features: Fully integrated design enironment VITAL-compliant library Industry-standard behaioral design entry with VHDL, Verilog HDL, and AHDL Synopsys timing constraints supported in the MAX+PLUS II Assignment & Configuration File (.acf) format RAM/ROM for the FLEX 10K family with the Altera-proided genmem utility, which generates timing and simulation models Altera Corporation 723

6 Altera-proided gencklk utility, which generates simulation models for ClockLock and ClockBoost features Different deice speed grades for FLEX 10K, FLEX 8000, and FLEX 6000 deices deice selection, fitting, and multi-deice partitioning Synopsys-proided Altera interfaces for FPGA Express Altera/Viewlogic Interface By combining Viewlogic design entry, synthesis, and erification tools (i.e., Poweriew and Workiew Office) with the MAX+PLUS II software, designs can be implemented in any Altera PLD. The Altera/Viewlogic design flow supports a top-down or mixed-leel design methodology. Designs can be entered as a mixture of schematics, VHDL, and AHDL. The Altera/Viewlogic interface supports the following features: Fully integrated design enironment Industry-standard behaioral design entry with VHDL and AHDL Easy-to-use, top-down design enironment Schematic design entry LPM, ersion RAM/ROM support Altera-proided gencklk utility, which generates simulation models Design description with architecture-independent design entry libraries deice selection, fitting, and multi-deice partitioning 724 Altera Corporation

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