UTOPIA Level 3 Slave. MegaCore Function UTOPIA3SL. User Guide September 2001

Transcription

1 UTOPIA Level 3 Slave MegaCore Function UTOPIA3SL User Guide September Innovation Drive San Jose, CA (48) A-UG-IPUTOPIA3SL-1.1

2 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide Copyright 21 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. All rights reserved. ii Altera Corporation

3 About this User Guide User Guide This user guide provides comprehensive information about the Altera UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL). Table 1 shows the user guide revision history. f Go to the following sources for more information: See Features on page 9 for a complete list of the core features, including new features in this release. Refer to the UTOPIA3SL readme file for late-breaking information that is not available in this user guide. Table 1. User Guide Revision History Date September 21 June 21 Description First revision. Added uflw_err and oflw_err signals. Initial release. How to Find Information The Adobe Acrobat Find feature allows you to search the contents of a PDF file. Click on the binoculars icon in the top toolbar to open the Find dialog box, or click the right mouse button for a pull-down menu. Bookmarks serve as an additional table of contents. Thumbnail icons, which provide miniature previews of each page, provide a link to the pages. Numerous links, shown in green text, allow you to jump to related information. Altera Corporation iii

4 About this User Guide How to Contact Altera UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide For the most up-to-date information about Altera products, go to the Altera world-wide web site at For additional information about Altera products, consult the sources shown in Table 2. Table 2. How to Contact Altera Information Type Access USA & Canada All Other Locations Altera Literature Services Non-technical customer service Electronic mail lit_req@altera.com (1) lit_req@altera.com (1) Telephone hotline (8) SOS-EPLD (48) (7:3 a.m. to 5:3 p.m. Pacific Time) Fax (48) (48) Technical support Telephone hotline (8) 8-EPLD (7: a.m. to 5: p.m. Pacific Time) General product information Note: (1) You can also contact your local Altera sales office or sales representative. (48) (1) (7:3 a.m. to 5:3 p.m. Pacific Time) Fax (48) (48) (1) Electronic mail telecom@altera.com telecom@altera.com FTP site ftp.altera.com ftp.altera.com Telephone (48) (48) (1) World-wide web site iv Altera Corporation

5 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide About this User Guide Typographic Conventions The UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide uses the typographic conventions shown in Table 3. Table 3. Conventions Visual Cue Meaning Bold Type with Initial Capital Letters bold type Bold italic type Italic Type with Initial Capital Letters Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: f MAX, \maxplus2 directory, d: drive, chiptrip.gdf file. Book titles are shown in bold italic type with initial capital letters. Example: 1999 Device Data Book. Document titles are shown in italic type with initial capital letters. Example: AN 75 (High-Speed Board Design). Italic type Internal timing parameters and variables are shown in italic type. Examples: t PIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file. Initial Capital Letters Subheading Title Courier type Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. References to sections within a document and titles of Quartus II and MAX+PLUS II Help topics are shown in quotation marks. Example: Configuring a FLEX 1K or FLEX 8 Device with the BitBlaster Download Cable. Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix _n, e.g., reset_n. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\max2work\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. 1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. Altera Corporation v

6 About this User Guide Abbreviations and Acronyms UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide AHDL Altera hardware description language ATM asynchronous transfer mode CPU central processing unit EDA electronic design automation EOP end of packet ERR error ESB embedded system block FIFO first-in first-out Gbps gigabits per second HDL hardware description language I/O input/output IP intellectual property LE logic element LSB least significant bit LSByte least significant byte Mbps megabits per second MPHY multi-phy MSB most significant bit MSByte most significant byte OC-12 optical carrier level 12 OC-48 optical carrier level 48 OSI open system interconnection PC personal computer PHY OSI physical layer PLD programmable logic device RX receive SOC start of cell SOP start of packet SPHY single-phy TX transmit UTOPIA universal test & operations physical interface for ATM VHDL VHSIC hardware description language VHSIC very high speed integrated circuit vi Altera Corporation

7 Contents User Guide About this User Guide How to Find Information... iii How to Contact Altera... iv Typographic Conventions...v Abbreviations and Acronyms... vi About this Core General Description...9 Features...9 Getting Started Design Walkthrough...11 Obtaining & Installing the UTOPIA3SL...12 Downloading the MegaCore Function...12 Installing the MegaCore Files...12 Generating a Custom UTOPIA3SL...13 Implementing the System...14 Simulating Your Design...14 Using the Verilog HDL Demo Testbench...15 Using the Visual IP Software...15 Synthesis, Compilation & Place & Route...15 Using Third-Party EDA Tools for Synthesis...15 Using the Quartus II Development Tool for Compilation & Place-and-Route...16 Licensing for Configuration...16 Performing Post-Routing Simulation...17 Specifications s & Protocols...2 UTOPIA Level Functional Description...21 Data Flow (DIR)...21 TXUTOPIA3SL...21 RXUTOPIA3SL...22 UTOPIA Level 3 Block...24 FIFO Buffer...24 Bus Parity (PRTY)...24 Bus Width...25 UTOPIA Data Width (UDAT)...25 Data Width (ADAT)...25 FIFO Buffer (FIFO)...25 Altera Corporation vii

8 Contents UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide Cell Length (CLEN)...26 PHY Configuration...29 Multi-PHY (MPHY)...29 Number of Ports (NPORTS)...29 Multi-PHY Address Translation (ATRANS)...29 Direct Status Indication Mode (DSTAT)...29 I/O Signals...3 Typical Configurations...32 Performance...36 AC Timing...37 viii Altera Corporation

9 General Description About this Core User Guide The UTOPIA Level 3 Slave MegaCore function (UTOPIA3SL) is designed for use in physical layer (PHY) devices that transfer data to and from asynchronous transfer mode (ATM) devices using the UTOPIA Level 3 interface, as defined by the ATM Forum. The UTOPIA level 3 interface specifies an operating frequency of up to 14 MHz, and a data path width of 8, 16, or 32 bits resulting in data transfer rates of up to 832 Mbps, 1.6 Gbps, or 3.2 Gbps, respectively. Typical applications for the UTOPIA3SL include: OC-48, quad OC-12, or 16 x OC- 3 line rates. The UTOPIA3SL is compliant with all applicable standards, including: ATM Forum, UTOPIA 3 Physical Layer Specification, af-phy- 136., November Altera Corporation, TM Specification. 1 About this Core Features Configurable for receive or transmit directions Supports single-phy (SPHY) and multi-phy(mphy) operation Configurable for up to 31 devices in MPHY mode Optional configuration of port/address map Configurable UTOPIA data width of 8, 16, or 32 bits Configurable slave interface data width of 8, 16, 32, or 64 bits Configurable cell transfer length Optional parity error detection Optional direct status indication Altera Corporation 9

10 Notes:

11 Getting Started User Guide Design Walkthrough This section describes how to obtain a variant from the UTOPIA Level 3 Slave MegaCore function (UTOPIA3SL). It explains how to install the UTOPIA3SL on your PC, and walks you through the process of implementing the variant in a design. You can test-drive a UTOPIA3SL using the Altera OpenCore feature within the Quartus II software to instantiate it, to perform place-androute, to perform static timing analysis, and to simulate it using a thirdparty simulator, within your custom logic. You only need licenses when you are ready to generate programming files. This design walkthrough involves the following steps: 1. Obtaining and installing the UTOPIA3SL MegaCore function. 2 Getting Started 2. Generating a custom UTOPIA3SL for your system using the Altera MegaWizard Plug-In. 3. Implementing the rest of your system using AHDL, VHDL, or Verilog HDL. 4. Simulating the UTOPIA3SL within your design. 5. Synthesis, compilation, and place-and-route. 6. Licensing the UTOPIA3SL to configure the device. 7. Performing post-routing simulation. The instructions assume that: You are using a PC You are familiar with the Quartus II software. The Quartus II software (the newest version) is installed in the default location. You are using the OpenCore feature to test-drive a UTOPIA3SL, or you have licensed it. Altera Corporation 11

12 Getting Started Obtaining & Installing the UTOPIA3SL UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide To start using the UTOPIA3SL, you need to obtain the MegaCore package, which includes the following: Data sheet User guide interface functional specification MegaWizard Plug-In Encrypted gate level netlist Place-and-route constraints (where necessary) Secure RTL simulation model Demo testbench Access to problem reporting system Downloading the MegaCore Function If you have Internet access, you can download the UTOPIA Level 3 MegaCore function from the Altera web site. Follow the instructions below to obtain the core via the Internet. If you do not have Internet access, you can obtain the core from your local Altera representative. 1. Point your web browser at 2. In the IP MegaSearch keyword field type UTOPIA. 3. Click the link for the UTOPIA Level 3 Slave MegaCore function. 4. On the product page, click the Free Test-Drive icon. 5. Follow the on-line instructions to download the function and save it to your hard disk. Installing the MegaCore Files Use the MegaWizard Plug-In to generate the files and install them on your PC. The following instructions describe this process. For UNIX systems, you must have Java runtime environment version 1.3 before you can use the MegaWizard Plug-In. You can download this file from the Java web site at For Windows, follow the instructions below: 1. Click Run (Start menu). 12 Altera Corporation

13 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingGetting Started Generating a Custom UTOPIA3SL 2. Type <path name>\<filename>.exe, where <path name> is the location of the downloaded UTOPIA3SL and <filename> is the filename of the UTOPIA3SL. Click OK. 3. The MegaCore Installer dialog box appears. Follow the MegaWizard Plug-In instructions to finish the installation. 4. If you do not have the Quartus II software version 1.1 or higher, you must specify the directory in which you installed the files as a user library. Search for User Libraries in Quartus II Help for instructions on how to add these libraries. This section describes the design flow using the UTOPIA Level 3 Slave MegaCore function and the Quartus II development system. A MegaWizard Plug-In is provided with the UTOPIA3SL. The MegaWizard Plug-In Manager used within the Quartus II software allows you to create or modify design files to meet the needs of your application. You can then instantiate the UTOPIA3SL in your design file. To create a custom UTOPIA3SL using the MegaWizard Plug-In, follow these steps: 1. Start the MegaWizard Plug-In by choosing the MegaWizard Plug-In Manager command (Tools menu) in the Quartus II software. The MegaWizard Plug-In Manager dialog box is displayed. 1 Refer to Quartus II Help for detailed instructions on how to use the MegaWizard Plug-In Manager. 2. Specify that you want to create a new custom variant and click Next. 3. On the second page of the MegaWizard Plug-In, open the Communications folder, and select the UTOPIA3SL from the UTOPIA folder. 4. Choose the type of output files (language), specify the folder and name for the files the MegaWizard Plug-In creates, and click Next. 5. Select the optional parameters and choices that you require. 1 If your chosen variant (configuration) is not included as part of the downloaded package, the MegaWizard Plug-In generates the necessary text to request this variant. Forward this text to telecom@altera.com for processing. 2 Getting Started Altera Corporation 13

14 Getting Started UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide 6. The final screen lists the design files created by the MegaWizard Plug-In, and indicates the location of the simulation models for the selected variant. Click Finish. Implementing the System Once you have created/obtained your custom UTOPIA3SL, you are ready to implement it. You can use the files generated by the MegaWizard Plug- In, and use the Quartus II software or other EDA tools to create your design. Table 1 lists the generated files. Table 1. MegaWizard Plug-In Files Description Verilog HDL VHDL Design File Wrapper.v.vhd Sample Instantiation _inst.v _inst.vhd Black Box Module _bb.v Symbol files for the Quartus II software used to instantiate the.bsf.bsf UTOPIA3SL into a schematic design An encrypted HDL netlist file.e.vqm.v.e.vqm.v Note: (1) AHDL output file creation is not supported in the UTOPIA3SL v1.1.p1 MegaWizard Plug-In. If AHDL output files are required, please contact telecom@altera.comto request them. Simulating Your Design Altera provides three models to be used for functional verification of the UTOPIA3SL within your design. A Verilog HDL demo testbench, including scripts to run it, is also provided. This demo testbench used with the ModelSim-Altera simulation tool demonstrates how to instantiate a model in a design. To find the simulation models for your selected variant, refer to the last page of the MegaWizard Plug-In Manager. These models and the demo testbench are located on your hard drive, the paths are: sim_lib/<variant>/modelsim_verilog/ sim_lib/<variant>/modelsim_vhdl/ sim_lib/<variant>/visual_ip/ sim_lib/<variant>/test/ 1 <variant> is a unique code (aotxxxx_#_utopia3sl) assigned to the specific configuration requested through the MegaWizard Plug-In. 14 Altera Corporation

15 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingGetting Started Using the Verilog HDL Demo Testbench The demo testbench includes some simple stimulus to control the user interfaces of the UTOPIA3SL. Each UTOPIA3SL variant includes scripts to compile and run the demo testbench using a variety of simulators and models. Synthesis, Compilation & Place & Route Using the Visual IP Software The Visual IP software facilitates the use of Visual IP simulation models with third-party simulation tools. To view a simulation model, you must have the Visual IP software installed on your system. To download the software, or for instructions on how to use the software, refer to the Altera web site at and search for Visual IP. For examples of how to use the provided Visual IP model, refer to the sample scripts included with the demo testbench. After you have verified that your design is functionally correct, you are ready to perform synthesis and place-and-route. Synthesis can be performed by the Quartus II development tool, or by a third-party synthesis tool. The Quartus II software works seamlessly with tools from many EDA vendors, including Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, and Viewlogic. 2 Getting Started Using Third-Party EDA Tools for Synthesis To synthesize your design in a third-party EDA tool, follow these steps: 1. Create your custom design instantiating a UTOPIA3SL. 2. Synthesize the design using your third-party EDA tool. Your EDA tool should treat the UTOPIA3SL instantiation as a black box by either setting attributes or ignoring the instantiation. 3. After compilation, generate a netlist file in your third-party EDA tool. Altera Corporation 15

16 Getting Started UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide Using the Quartus II Development Tool for Compilation & Placeand-Route To use the Quartus II software to compile and place-and-route your design, follow these steps: 1. Select Compile mode (Processing menu). 2. Specify the compiler settings in the Compiler Settings dialog box (Processing menu) or use the Compiler Settings wizard. 3. If you are not using the Quartus II software version 1.1 or higher, you must specify the user libraries for the project and the order in which the compiler searches the libraries. 4. Specify the input settings for the project. Choose EDA Tool Settings (Project menu). Select Custom EDIF in the Design entry/synthesis tool list. Click Settings. In the EDA Tool Input Settings dialog box, make sure that the relevant tool name or option is selected in the Design Entry/Synthesis Tool list. 5. Add your third-party EDA tool-generated netlist file to your project. 6. Add any.tdf,.vhd, or.v files not synthesized in the third-party tool. 7. Add the pre-synthesized and encrypted.e.vqm.v file from your working directory, created by the MegaWizard Plug-In Manager. 8. Constrain your design as required. 9. Compile your design. The Quartus II compiler synthesizes and performs place-and-route on your design. f Licensing for Configuration Refer to Quartus II Help for further instructions on performing compilation. After you have compiled and analyzed your design, you are ready to configure your targeted Altera PLD. If you are evaluating the UTOPIA3SL with the OpenCore feature, you must license the function before you can generate programming files. To obtain licenses contact your local Altera sales representative. 1 All current UTOPIA3SL variants use a single license, with ordering code: PLSM-UTOPIA3SL. 16 Altera Corporation

17 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingGetting Started Performing Post-Routing Simulation After you have licensed the UTOPIA3SL, you can generate EDIF, VHDL, Verilog HDL, and Standard Delay Output Files from the Quartus II software and use them with your existing EDA tools to perform functional modeling and post-routing simulation of your design. 1. Open your existing Quartus II project. 2. Depending on the type of output file you want, specify Verilog HDL output settings or VHDL output settings in the General Settings dialog box (Project menu). 3. Compile your design with the Quartus II software, refer to the Using the Quartus II Development Tool for Compilation & Placeand-Route section. The Quartus II software generates output and programing files. 4. You can now import your Quartus II software-generated output files (.edo,.vho,.vo, or.sdo) into your third-party EDA tool for postroute, device-level, and system-level simulation. 2 Getting Started Altera Corporation 17

18 Notes:

19 Specifications User Guide Customized variants of the UTOPIA Level 3 Slave MegaCore function (UTOPIA3SL) can be generated/requested using the MegaWizard Plug- In within the Quartus II software. Table 1 shows the optional features available to generate all variants. Table 1. Optional Features Options Parameters Choices Data flow DIR RX / TX Bus parity PRTY Yes / No Include FIFO buffer FIFO Yes / No UTOPIA data width UDAT 8 / 16 / 32 data width (1) ADAT 8 / 16 / 32 / 64 Cell length CLEN (n/a for UTOPIA data width of 16 or 32) 54 (n/a for UTOPIA data width of 8 or 32) 56 (n/a for UTOPIA data width of 8 or 16) Multi-PHY MPHY Yes / No Number of ports (2) NPORTS 2-31 (only valid when MPHY = Yes) Multi-PHY address ATRANS Direct (No translation) translation (2) Custom (Port to address mapping) Direct status mode (3) DSTAT Yes / No 3 Specifications Notes: (1) FIFO buffer required, otherwise data width must be equal to UTOPIA data width. (2) Only applicable for multi-phy configuration. (3) Only available for multi-phy configuration with up to 4 ports. f For detailed instructions on generating a custom UTOPIA3SL, refer to the Generating a Custom UTOPIA3SL section in the Getting Started chapter. Altera Corporation 19

20 Specifications s & Protocols UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide Two interfaces, described below, support the UTOPIA3SL. UTOPIA Level 3 The UTOPIA level 3 interface is an external protocol defined by the ATM Forum. Depending on the variant chosen (see Table 1), the UTOPIA3SL uses this interface to support: a data width of 8, 16, or 32 bits, SPHY or MPHY operation, bus parity, 52, 53, 54, or 56 octet cells, and direct status or polling mode. If MPHY = No, the utxaddr[4:]/urxaddr[4:] address lines are not present. If DSTAT = No, the utxclav[3:1]/urxclav[3:1] ports are not present. If PRTY = No, the utxprty/urxprty ports are not present. f For further information on this interface, refer to the ATM Forum, UTOPIA 3 Physical Layer Specification, af-phy-136., November 1999, available at The TM interface is a full-duplex synchronous bus protocol. The UTOPIA3SL supports data widths of 8, 16, 32, and 64 bits on the interface. If PRTY = No, the arxpar/atxpar ports are not present. If the chosen variant of the UTOPIA3SL is configured to include a multicell first in first out (FIFO) buffer for crossing the clock domain, the interface operates as a slave, otherwise it operates as a master. f For further information on this interface, refer to the Functional Specification, available at 2 Altera Corporation

21 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingSpecifications Functional Description This section describes the various optional features available to generate a UTOPIA3SL, and their respective functions. Some of these options are inter-dependent, and are therefore grouped and described accordingly. Data Flow (DIR) The UTOPIA3SL functions either as a transmitter (TXUTOPIA3SL) where data flows from the ATM device to the PHY device, or as a receiver (RXUTOPIA3SL) where data flows from the PHY device to the ATM device. Both the TXUTOPIA3SL and RXUTOPIA3SL have control signals for handshaking. 1 In order for the UTOPIA3SL to act as a full-duplex, bidirectional transceiver, you need to instantiate two variants: a TXUTOPIA3SL and a RXUTOPIA3SL. TXUTOPIA3SL The TXUTOPIA3SL is polled by the ATM layer to determine whether it is ready to receive data transfers. Polling is achieved when the PHY device outputs the port address on the utxaddr bus. Two cycles later, if the port can accept one or more complete ATM cells, the TXUTOPIA3SL accepts the data transfer by driving its utxclav signal high, in accordance with the UTOPIA level 3 interface specification. The cells from the ATM layer are thus transferred via the UTOPIA level 3 interface, and are in turn sent to the PHY device via the interface. Figure 1 shows the TXUTOPIA3SL block diagram. 3 Specifications Altera Corporation 21

22 Specifications UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide Figure 1. TXUTOPIA3SL Block Diagram FIFO Port Clock Domain UTOPIA Clock Domain atxclk_ atxreset_n_ atxena_ atxdav_ atxdat_[63/31/15/7:] atxval_ atxpar_ atxsop_ atxeop_ atxerr_ Global Signals soc_ soc_err_ oflw_err_ uflw_err_ FIFO Port N* Clock Domain FIFO Port UTOPIA Level 3 Block utxclk utxreset_n utxenb_n utxaddr[4/3/2/1/:] utxclav[3/:] utxdata[31/15/7:] utxprty utxsoc UTOPIA Level 3 atxclk_n* atxreset_n_n* atxena_n* atxdav_n* atxdat_n*[63/31/15/7:] atxval_n* atxpar_n* atxsop_n* atxeop_n* atxerr_n* FIFO Port N* (1) prty_err Global Signal Global Signals soc_n* soc_err_n* oflw_err_n* uflw_err_n* Note: (1) N * is equivalent to a number from 1 to 31, depending on the number of ports chosen as an option, see Table 1. RXUTOPIA3SL The RXUTOPIA3SL is polled by the ATM layer to determine whether it is ready to transfer data. Polling is achieved when the PHY device outputs the port address on the urxaddr bus. Two cycles later, if the port is ready to send one or more complete ATM cells, the RXUTOPIA3SL completes the data transfer by driving its urxclav signal high, in accordance with the UTOPIA level 3 interface specification. Thus the RXUTOPIA3SL accepts cells from the PHY layer via the interface, and sends them to the ATM layer device via the UTOPIA level 3 interface. The RXUTOPIA3SL also checks for parity errors on the UTOPIA level 3 interface. Figure 2 shows the RXUTOPIA3SL block diagram. 22 Altera Corporation

23 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingSpecifications Figure 2. RXUTOPIA3SL Block Diagram FIFO Port Clock Domain UTOPIA Clock Domain arxclk_ arxreset_n_ arxena_ arxdav_ arxdat_[63/31/15/7:] FIFO Port arxpar_ arxsop_ arxerr_ Global Signals soc_ soc_err_ oflw_err_ uflw_err_ FIFO Port N* Clock Domain arxclk_n* arxreset_n_n* arxena_n* arxdav_n* arxdat_n*[63/31/15/7:] arxpar_n* arxsop_n* arxerr_n* FIFO Port N* (1) UTOPIA Level 3 Block urxclk urxreset_n urxenb_n urxaddr[4/3/2/1/:] urxclav[3/:] urxdata[31/15/7:] urxprty urxsoc prty_err Global Signal UTOPIA Level 3 3 Specifications Global Signals soc_n* soc_err_n* oflw_err_n* uflw_err_n* Note: (1) N * is equivalent to a number from 1 to 31, depending on the number of ports chosen as an option, see Table 1. f For further details on the transmitter or receiver functions, including timing information, refer to the ATM Forum, UTOPIA 3 Physical Layer Specification, af-phy-136., November Both variants, TXUTOPIA3SL and RXUTOPIA3SL, are further divided into sub-blocks: the UTOPIA block and the FIFO buffer, as illustrated in Figures 1 and 2. Altera Corporation 23

24 Specifications UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide UTOPIA Level 3 Block The UTOPIA block is the Input/Output (I/O) port for the UTOPIA level 3 interface. This block s primary function is address decoding and port selection. The following is a summary list of functions. Cell-based handshaking Cell available status indication PHY address decoding UTOPIA data bus parity checking Parity error indication FIFO Buffer The FIFO buffer is used for clock decoupling between the internal clock and the UTOPIA clock. The following is a summary list of functions. Data width conversion Cell-based handshaking Start of packet (SOP) error detection SOP indication SOP error indication Recovery from invalid cell lengths End of packet (EOP) generation Error (ERR) signal generation Overflow indication Underflow indication For both UTOPIA and FIFO buffer sub-blocks, functionality is largely dependent on the chosen variant, see Table 1. Bus Parity (PRTY) The UTOPIA level 3 interface specifies that odd parity be passed. In the receive direction, where data flows from the interface to the UTOPIA level 3 interface, the user must insert the parity (arxpar) lines for the correct parity to be placed on the urxprty line. The data bus (urxdata) and parity (urxprty) are monitored for errors. When an error is detected, the prty_err signal is asserted for the duration of the current cell transfer. 24 Altera Corporation

25 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingSpecifications In the transmit direction, where data flows from the UTOPIA level 3 interface to the interface, the data bus (utxdata) and parity (utxprty) lines are monitored for errors. When a parity error is detected, the prty_err signal is asserted for one clock cycle. The error signal (atxerr) on the bus is asserted upon detecting the parity error, till the end of the current cell. Bus Width UTOPIA Data Width (UDAT) This feature sets the UTOPIA data bus width. In accordance with UTOPIA level 3 interface handshaking, the UTOPIA3SL supports the three following options: 8-bit UTOPIA data bus 16-bit UTOPIA data bus 32-bit UTOPIA data bus 1 The UTOPIA data bus width can differ from the data bus width. Data Width (ADAT) This feature sets the data bus width. Four choices are available: 8, 16, 32, or 64 bits. 3 Specifications 1 If the data width chosen is not equal to the UTOPIA data bus width, the user MUST also choose the Include FIFO buffer option. FIFO Buffer (FIFO) The user has the option to include, or not include a FIFO buffer. If the user chooses the Include FIFO buffer option, one FIFO buffer is included for each port. If the FIFO is not included, the interface signals are on the same clock domain as the UTOPIA clock. Altera Corporation 25

26 Specifications UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide Four global signals: soc_n *, soc_err_n *, oflw_err_n*, and uflw_err_n* are also included, and intended as additional optional logic to be used as required by the user. The soc_n * signal indicates a cell has been written to the FIFO buffer from either the UTOPIA level 3 interface via the TXUTOPIA3SL, or the interface via the RXUTOPIA3SL. The soc_err_n * signal is asserted to indicate a start of cell (soc) error condition. A soc error indicates a start of packet (SOP) is incorrectly positioned. The oflw_err_n* indicates that a cell transfer has been initiated with the arxdav (RXUTOPIA3SL) or utxclav (TXUTOPIA3SL) deasserted thus indicating that the FIFO buffer cannot accept a full cell. This overflow-type condition causes the cell to be discarded. The uflw_err_n* indicates an underflow condition exists in the FIFO buffer. The uflw_err_n* signal is asserted when the utxenb_n signal (TXUTOPIA) or atxena signal (RXUTOPIA) is sampled asserted, and the core does not hold valid data to be placed on the bus. In the TXUTOPIA, the soc_n *, soc_err_n *, and oflw_err_n* signals are asynchronous to the utxclk. The uflw_err_n* is synchronous to the atxclk. The soc_n * signal is asserted two clock cycles after the utxsoc signal is asserted. The soc_err_n * signal is asserted one clock cycle after an error is detected on the utxsoc signal. In the RXUTOPIA, the soc_n *, soc_err_n *, and oflw_err_n* signals are synchronous to the arxclk_n *. The uflw_err_n* is synchronous to the urxclk. The soc_n * signal is asserted when the arxsop_n * signal is detected on the interface. The soc_err_n * signal is asserted when an error is detected on the arxsop_n * signal on the interface. Cell Length (CLEN) The UTOPIA level 3 interface specifies a standard cell structure of 52 octets for all UTOPIA data widths. The following cell structures are also supported: 53 octets for the 8-bit UTOPIA data bus 54 octets for the 16-bit UTOPIA data bus 56 octets for the 32-bit UTOPIA data bus The UTOPIA3SL converts cells formatted for the into a cell structure used by the UTOPIA level 3 interface. Figures 3 to 7 show the cell structures used to transport data across the interface. 26 Altera Corporation

27 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingSpecifications Figure 3. 8-Bit, 52-and 53-Octet Cell Structures 7 DAT SOP EOP 7 DAT SOP EOP H1 1 H1 1 H2 H2 H3 H3 H4 H4 P1 HEC P2 P1 P2 P48 1 P octets 53 octets Figure Bit, 52 and 54 Octet Cell Structures 15 DAT SOP EOP 15 DAT SOP EOP 3 H1 H3 P1 H2 H4 P2 1 H1 H3 HEC H2 H4 UDF 1 Specifications P1 P2 P47 P48 1 P47 P octets 54 octets Altera Corporation 27

28 Specifications UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide Figure Bit, 52 and 56 Octet Cell Structures 31 DAT SOP EOP 31 DAT SOP EOP H1 H2 H3 H4 1 H1 H2 H3 H4 1 P1 P2 P3 P4 HEC UDF UDF UDF P1 P2 P3 P4 P45 P46 P47 P48 1 P45 P46 P47 P octets 56 octets Figure Bit, 56 Octet Cell Structure 63 DAT SOP EOP H1 H2 H3 H4 HEC UDF UDF UDF 1 P1 P2 P3 P4 P5 P6 P7 P8 P41 P42 P43 P44 P45 P46 P47 P octets with HEC Figure Bit, 52 Octet Cell Structure 63 DAT SOP EOP H1 H2 H3 H4 X (1) (1) (1) (1) X X X 1 P1 P2 P3 P4 P5 P6 P7 P8 P41 P42 P43 P44 P45 P46 P47 P octet without HEC Note: (1) In the case of a 52-octet cell, DAT [31:] is discarded 28 Altera Corporation

29 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingSpecifications PHY Configuration The UTOPIA3SL can be configured for one of two modes of operation: SPHY or MPHY. The SPHY configuration is a single data path, point-to-point connection between the ATM device and PHY device. Only one interface port is included. Multi-PHY (MPHY) The MPHY configuration allows for a single PHY device to have multiple ports. One interface is included for each port. Polling is done by internal direct status. The dav signal is not blocked. It is immediately updated and valid after the first cell transfer. Number of Ports (NPORTS) If the chosen UTOPIA3SL variant includes the MPHY option, the user can select the number of ports, up to Multi-PHY Address Translation (ATRANS) This feature offers two options for translation: Direct or Custom. Direct implies no translation. Ports are assigned in a sequential order, starting at zero. Custom implies port to address mapping. The user specifies an address for each port via the MegaWizard Plug-In. Specifications Direct Status Indication Mode (DSTAT) The UTOPIA3SL can be configured to operate in direct, or polling status mode. In polling status mode, a single UTOPIA Clav (utxclav[]) signal is used to indicate that the cell buffer may accept at least one entire cell; a single UTOPIA Clav (urxclav[]) signal is used to indicate that at least one entire cell is available in the FIFO buffer. This applies for any number of ports, from 2 to 31. Altera Corporation 29

30 Specifications UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide In direct status indication mode, four UTOPIA Clav (utxclav[3:]) signals, one for each port, are used to indicate that the cell buffer may accept at least one entire cell; four UTOPIA Clav (urxclav[3:]) signals, one for each port, are used to indicate that at least one entire cell is available in the FIFO buffer. The DSTAT mode is only possible when the chosen variant is an MPHY device with up to four ports. I/O Signals Tables 2 to 6 list the I/O signals used in the UTOPIA3SL The active low signals are indicated by _n. Table 2. UTOPIA Level 3 Transmit Signal Direction Description Configuration Requirement utxclk Input Transfer/ clock None utxreset_n Input Active low synchronous reset None utxenb_n ATM to PHY Active low signal. Enables port selection in None MPHY mode utxaddr[n:] ATM to PHY Address for MPHY device being selected MPHY = Yes utxclav[] PHY to ATM Cell buffer may accept at least one entire cell None utxclav[3:1] PHY to ATM Cell buffer may accept at least one entire cell NPORTS <=4, DSTAT utxdata ATM to PHY Data bus UDAT = 32, 16, 8 [31/15/7:] utxprty ATM to PHY Odd parity calculated across data bus PRTY = Yes utxsoc ATM to PHY Start of cell None Table 3. UTOPIA Level 3 Receive Signal Direction Description Configuration Requirement urxclk Input Transfer/ clock None urxreset_n Input Active low synchronous reset None urxenb_n ATM to PHY Enables port selection in MPHY mode None urxaddr[4:] ATM to PHY Address for MPHY device being selected MPHY = Yes urxclav[] PHY to ATM At least one entire cell is available in the None FIFO buffer urxclav[3:1] PHY to ATM At least one entire cell is available in the NPORTS <=4, DSTAT FIFO buffer urxdata PHY to ATM Data bus UDAT = 32, 16, 8 [31/15/7:] urxprty PHY to ATM Odd parity calculated across data bus PRTY = Yes urxsoc PHY to ATM Start of cell None 3 Altera Corporation

31 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingSpecifications Table 4. Receive Signal Direction Description Configuration Requirement arxclk Input Clock FIFO = Yes arxreset_n Input Active low synchronous reset FIFO = Yes arxena Master to Slave Enables port selection in MPHY mode None arxdat [63/31/15/7:] Input Data bus ADAT = 64, 32, 16, 8 arxval Slave to Master Data valid FIFO = No arxdav Slave to Master Cell buffer may accept at least one entire cell None arxpar Input Odd parity calculated across data bus PRTY = Yes arxsop Input Start of packet None arxerr Input Data error None Table 5. Transmit Signal Direction Description Configuration Requirement atxclk Input Clock FIFO = Yes atxreset_n Input Active low synchronous reset FIFO = Yes atxena Master to Slave Enables port selection in MPHY mode None atxdav Slave to Master Cell buffer may accept at least one entire cell None atxdat [63/31/15/7:] Output Data bus ADAT = 64, 32, 16, 8 atxval Slave to Master Data valid FIFO = Yes atxpar Output Odd parity calculated across data bus PRTY = Yes atxsop Output Start of packet None atxeop Output End of packet None atxerr Output Data error. Current cell contains a soc or prty error and should be discarded. None 3 Specifications Table 6. Global Signals Signal Direction Description Configuration Requirement prty_err Output Parity error in current cell PRTY = Yes soc[n-1:] Output Start of cell has been written to the FIFO. FIFO = Yes soc_err[n-1:] Output Start of cell error. FIFO = Yes oflw_err[n-1:] Output FIFO overflow. Current cell is discarded. FIFO=Yes uflw_err[n-1:] Output FIFO underflow FIFO=Yes Altera Corporation 31

32 Specifications Typical Configurations UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide This section shows some common example configurations, illustrated in Figures 8 to 12. Figure 8 shows an RXUTOPIA3SL and a TXUTOPIA3SL configured for one port, and for full-duplex operation. Figure 8. One Port Configuration. RXUTOPIA3SL FIFO Port Clock Domain UTOPIA Clock Domain arxclk_ arxreset_n_ arxena_ arxdav_ arxdat_[63/31/15/7:] arxsop_ FIFO Port UTOPIA Level 3 Block urxclk urxreset_n urxenb_n urxaddr[4/3/2/1/:] urxclav[3/:] urxdata[31/15/7:] urxsoc UTOPIA Level 3 arxerr_ Global Signals soc_ soc_err_ oflw_err_ uflw_err_ TXUTOPIA3SL FIFO Port Clock Domain UTOPIA Clock Domain atxclk_ atxreset_n_ atxena_ atxdav_ atxdat_[63/31/15/7:] atxval_ atxsop_ atxerr_ atxeop_ FIFO Port UTOPIA Level 3 Block utxclk utxreset_n utxenb_n utxaddr[4/3/2/1/:] utxclav[3/:] utxdata[31/15/7:] utxsoc UTOPIA Level 3 Global Signals soc_ soc_err_ oflw_err_ uflw_err_ 32 Altera Corporation

33 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingSpecifications Figure 8 shows an RXUTOPIA3SL configured for four ports. Figure 9. RXTUOPIA3SL Four Port Configuration FIFO Port Clock Domain UTOPIA Clock Domain arxclk_ arxreset_n_ arxena_ arxdav_ arxdat_[63/31/15/7:] arxsop_ arxerr_ FIFO Port Global Signals soc_ soc_err_ oflw_err_ uflw_err_ FIFO Port 1 Clock Domain arxclk_1 arxreset_n_1 arxena_1 arxdav_1 arxdat_1[63/31/15/7:] arxsop_1 FIFO Port 1 3 Global Signals arxerr_1 soc_1 soc_err_1 oflw_err_1 uflw_err_1 FIFO Port 2 Clock Domain arxclk_2 UTOPIA Level 3 Block urxclk urxreset_n urxenb_n urxaddr[4/3/2/1/:] urxclav[3/:] urxdata[31/15/7:] urxsoc UTOPIA Level 3 Specifications arxreset_n_2 arxena_2 arxdav_2 arxdat_2[63/31/15/7:] FIFO Port 2 arxsop_2 arxerr_2 Global Signals soc_2 soc_err_2 oflw_err_2 uflw_err_2 FIFO Port 3 Clock Domain arxclk_3 arxreset_n_3 arxena_3 arxdav_3 arxdat_3[63/31/15/7:] arxsop_3 arxerr_3 FIFO Port 3 Global Signals soc_3 soc_err_3 oflw_err_3 uflw_err_3 Altera Corporation 33

34 Specifications UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide Figure 1 shows a TXUTOPIA3SL configured for four ports. Figure 1. TXUTOPIA3SL Four Port Configuration FIFO Port Clock Domain UTOPIA Clock Domain atxclk_ atxreset_n_ atxena_ atxdav_ atxdat_[63/31/15/7:] atxval_ atxsop_ atxeop_ atxerr_ FIFO Port Global Signals soc_ soc_err_ oflw_err_ uflw_err_ FIFO Port 1 Clock Domain atxclk_1 atxreset_n_1 Global Signals atxena_1 atxdav_1 atxdat_1[63/31/15/7:] atxval_1 atxsop_1 atxeop_1 atxerr_1 soc_1 soc_err_1 oflw_err_1 uflw_err_1 FIFO Port 2 Clock Domain atxclk_2 atxreset_n_2 atxena_2 atxdav_2 atxdat_2[63/31/15/7:] atxval_2 atxsop_2 atxeop_2 atxerr_2 FIFO Port 1 FIFO Port 2 UTOPIA Level 3 Block utxclk utxreset_n utxenb_n utxaddr[4/3/2/1/:] utxclav[3/:] utxdata[31/15/7:] utxsoc UTOPIA Level 3 Global Signals soc_2 soc_err_2 oflw_err_2 uflw_err_2 FIFO Port 3 Clock Domain atxclk_3 atxreset_n_3 atxena_3 atxdav_3 atxdat_3[63/31/15/7:] atxval_3 atxsop_3 atxeop_3 atxerr_3 FIFO Port 3 Global Signals soc_3 soc_err_3 oflw_err_3 uflw_err_3 34 Altera Corporation

35 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingSpecifications Figure 11 shows an RXUTOPIA3SL configured for four ports, without FIFO buffers. Figure 11. RXUTOPIA3SL No FIFO Buffer Configuration. arxena_ arxdav_ arxdat_[63/31/15/7:] arxval_ arxsop_ arxerr_ arxena_1 arxdav_1 arxdat_1[63/31/15/7:] arxval_1 arxpar_1 arxsop_1 arxerr_1 arxena_2 arxdav_2 arxdat_2[63/31/15/7:] arxval_2 arxpar_2 arxsop_2 arxerr_2 arxena_3 arxdav_3 UTOPIA Level 3 Block uclk ureset_n urxenb_n urxaddr[4/3/2/1/:] urxclav[3/:] urxdata[31/15/7:] urxsoc UTOPIA Level 3 3 Specifications arxdat_3[63/31/15/7:] arxval_3 arxpar_3 arxsop_3 arxerr_3 Note: (1) The interface signals are intended to be on the same clock domain as the UTOPIA clock. Altera Corporation 35

36 Specifications UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide Figure 12 shows a TXUTOPIA3SL configured for four ports, without FIFO buffers. Figure 12. TXUTOPIA3SL No FIFO Buffer Configuration. atxena_ atxdav_ atxdat_[63/31/15/7:] atxsop_ atxeop_ atxerr_ atxena_1 atxdav_1 atxdat_1[63/31/15/7:] atxsop_1 atxeop_1 atxerr_1 atxena_2 atxdav_2 UTOPIA Level 3 Block uclk ureset_n utxenb_n utxaddr[4/3/2/1/:] utxclav[3/:] utxdata[31/15/7:] utxsoc UTOPIA Level 3 atxdat_2[63/31/15/7:] atxsop_2 atxeop_2 atxerr_2 atxena_3 atxdav_3 atxdat_3[63/31/15/7:] atxsop_3 atxeop_3 atxerr_3 Note: (1) The interface signals are intended to be on the same clock domain as the UTOPIA clock. Performance Tables 7 to 9 show the estimated resource utilization and performance for these sample configurations. The utilization and performance information was generated with the Quartus II version 1.1 software, for an APEX 2K4E-1 device 36 Altera Corporation

37 UTOPIA Level 3 Slave MegaCore Function (UTOPIA3SL) User Guide GettingSpecifications Table 7 lists the estimated resources and speed of a one port RXUTOPIA3SL and TXUTOPIA3SL. Table 7. One Port Configuration Utilization Performance Direction Parameters LE ESB f MAX (MHz) RXUTOPIA3SL TXUTOPIA3SL PRTY=No, FIFO=Yes, UDAT=32, ADAT=32, CLEN=52, MPHY=No PRTY=No, FIFO=Yes, UDAT=32, ADAT=32, CLEN=52, MPHY=No Table 8 lists the estimated resources and speed of a four port RXUTOPIA3SL and TXUTOPIA3SL. Table 8. Four Port Configuration Utilization Performance Direction Parameters LE ESB f MAX (MHz) RXUTOPIA3SL TXUTOPIA3SL PRTY=No, FIFO=Yes, UDAT=32, ADAT=32, CLEN=52, MPHY=Yes, NPORTS=4, ATRANS=No, DSTAT=No PRTY=No, FIFO=Yes, UDAT=32, ADAT=32, CLEN=52, MPHY=Yes, NPORTS=4, ATRANS=No, DSTAT=No 1, , Table 9 lists the estimated resources and speed of an RXUTOPIA3SL and a TXUTOPIA3SL without FIFO buffers. 3 Specifications Table 9. No FIFO Buffer Configuration Utilization Performance Direction Parameters LE ESB f MAX (MHz) RXUTOPIA3SL TXUTOPIA3SL PRTY=No, FIFO=No, UDAT=32, ADAT=32, CLEN=52, MPHY=Yes, NPORTS=4, ATRANS=No, DSTAT=No PRTY=No, FIFO=No, UDAT=32, ADAT=32, CLEN=52, MPHY=Yes, NPORTS=4, ATRANS=No, DSTAT=No AC Timing For timing information on the UTOPIA level 3 interface, refer to the ATM Forum, UTOPIA 3 Physical Layer Specification, af-phy-136., November 1999, available at Altera Corporation 37

38 Notes: