Not Recommended for New Designs TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS SLES152B OCTOBER 2005 REVISED NOVEMBER 2007

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1 TAS318, TAS318IA 1 Introduction 1.1 Features 8 channel Programmable Audio Digital Signal 16-, 2-, 24-, and 32-Bit Word Sizes Processor (DSP) 64-f S, 128-f S, 192-f S, and 256-f S SCLK to 135-MHz Maximum Speed, >28 Processing Support Discrete 4 channel TDM, 6 channel Cycles Per Sample at 48 khz TDM, and 8 channel TDM Data-Transfer Sample Rates of 32 khz to 192 khz Formats 48-Bit Data Path and 28-Bit Coefficients Two I 2 C Ports for Slave or Master Download Single-Cycle, 76-Bit Multiply Accumulate Soft Volume Controller Five Simultaneous Operations Per Clock Cycle Dither Generator 122 Words of 48-Bit Data Memory Efficient log 2 /2 x Estimator 122 Words of 28-Bit Coefficient Memory Single 3.3-V Power Supply 3K Words of 54-Bit Program RAM 38-Pin Thin Shrink Small-Outline Package (TSSOP) (DCP) 5.88K Words of 24-Bit Delay Memory (122.5 ms at 48 khz) AEC-Q1 (Grade 2: 4 C to 15 C) 15 Stereo/TDM Data Formats Compliant for Automotive Applications (TAS318IA) Independent Input/Output Data Formats 1.2 Applications Automotive Sound Systems Digital Televisions Home Theater Systems Mini-Component Audio TAS318/TAS318IA SDIN1 SDIN2 SDIN3 SDIN4 Serial Audio Input Port 8 Audio DSP Core 48-Bit Data Path 28-Bit Coefficients 76-Bit MAC 8 Serial Audio Output Port SDOUT1 SDOUT2 SDOUT3 SDOUT4 MCLK LRCLK SCLKIN SCLKOUT1 SCLKOUT2 PLL and Clock Control 3K Code RAM 1K Data RAM 1K Coeff. RAM 5.8K Delay RAM Boot ROM Volume Update 851 MCU I 2 C Port #1 I 2 C Port #2 I 2 C Interface 8-Bit Microprocessor 256 IRAM 2K ERAM 12K Code RAM B74-1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 25 27, Texas Instruments Incorporated

2 TAS318, TAS318IA Contents 1 Introduction I 2 C Register Map Features Clock Control Register (x) Applications Status Register (x2) Functional Description I 2 C Memory Load Control and Data Registers (x4 2.1 Device Description... 3 and x5) Power Supply Clock Control Serial Audio Ports (SAPs) Memory Access Registers (x6 and x7) Electrical Specifications Absolute Maximum Ratings Over Operating Temperature Range (unless otherwise noted) M851Warp Microprocessor Package Dissipation Ratings 2.6 I 2 C Control Interface... 4 (TAS318/TAS318IA) Audio DSP Core Recommended Operating Conditions 3 Physical Characteristics... 6 (TAS318/TAS318IA) Terminal Assignments Electrical Characteristics (TAS318/TAS318IA) Terminal Descriptions Timing Characteristics Reset (RESET) Master Clock Signals (TAS318/TAS318IA) Power-On Reset (RESET) Power Down (PDN) Serial Audio Port Slave Mode Signals (TAS318/TAS318IA) Serial Audio Port Master Mode Signals 3.6 I 2 C Bus Control (CS)... 8 (TAS318/TAS318IA) Programmable General Purpose I/O (GPIO) Pin-Related Characteristics of the SDA and SCL 3.8 Input and Output Serial Audio Ports... 9 I/O Stages for F/S-Mode I 2 C-Bus Devices Algorithm and Software Development Tools for Reset Timing (TAS318/TAS318IA) TAS318/TAS318IA Application Information Clock Controls Schematics Microprocessor Controller Recommended Oscillator Circuit General I 2 C Operations Recommended PCB Design for TAS318IA 6.2 Detailed I 2 C Operation Applications I 2 C Master-Mode Device Initialization Contents Submit Documentation Feedback

3 2 Functional Description 2.1 Device Description TAS318, TAS318IA The TAS318 and TAS318IA are fully programmable high-performance audio processors. The devices use an efficient, custom, multi-instruction programming environment optimized for digital audio processing algorithms. The TAS318/TAS318IA architecture provides high-quality audio processing by using a 48-bit data path, 28-bit filter coefficients, and a single-cycle bit multiplier with a 76-bit accumulator. An embedded 851 microprocessor provides algorithm and data control for the TAS318/TAS318IA. The TAS318 is the commercial version intended for home audio and other commercial applications. The TAS318IA is the automotive version that is qualified for use in automotive applications. Audio DSP Core SDIN1 SDIN2 SDIN3 SDIN4 SDOUT1 SDOUT2 Serial Audio Port 8 Channels Data Path SDOUT3 SDOUT4 8 Channels Coef. RAM (122 28) Data RAM (122 48) MCLK LRCLK SCLKIN SCLKOUT1 Clock Control Controller 54 Memory Interface Code RAM (3K 54) SCLKOUT2 Internal Data RAM (256 8) 8 Microprocessor Core Delay Memory (5.8K 24) External Data RAM (248 8) Code RAM (12K 8) 8-Bit MCU (851) Code ROM Control Registers 8 8 Volume Update I 2 C Control Interface Power Supply 2 SDA 2 SCL CSO GPIO AVDD DVDD B75-1 Figure 2-1. Expanded TAS318/TAS318IA Functional Block Diagram Submit Documentation Feedback Functional Description 3

4 TAS318, TAS318IA 2.2 Power Supply The power supply contains supply regulators that provide analog and digital regulated power for various sections of the TAS318/TAS318IA. Only one external 3.3-V supply is required. All other voltages are generated on-chip from the external 3.3-V supply. 2.3 Clock Control The TAS318/TAS318IA can be an audio data clock-master or clock-slave device. In clock-master mode, it generates MCLK, SCLK, and LRCLK. In clock-slave mode, it accepts MCLK, SCLK, and LRCLK. It can generate or accept master clocks from 6 MHz to MHz. Master or slave operation is set via I 2 C register x. The TAS318/TAS318IA can use a 6-MHz to 2-MHz crystal or a 6-MHz to MHz, 3.3-V MCLKI digital input as the master clock in either clock-master or clock-slave mode. In clock-slave mode, the master clock frequency does not need to be an integer multiple of the sample rate. The TAS318/TAS318IA does not support clock error detection. If a clock error occurs, the TAS318/TAS318IA does not prevent invalid data or clocks from being output. This means that the application system must be designed to handle clock errors. 2.4 Serial Audio Ports (SAPs) Serial audio data is input via pins SDIN1, SDIN2, SDIN3, and SDIN4. Serial audio data is output on pins SDOUT1, SDOUT2, SDOUT3, and SDOUT4. The TAS318/TAS318IA accepts 32-, 44.1-, 48-, 88.2-, 96-, , or 192-kHz serial data as 16-, 2-, 24-, or 32-bit data in left justified, right justified, or I 2 S serial data formats. All four ports accommodate these three 2 channel data formats. In addition to supporting the 2 channel formats, SDIN1 and SDOUT1 also provide support for time-division multiplex (TDM) data formats of 4, 6, or 8 channels. The data formats are selectable via I 2 C register x. All input channels must use the same data format. All output channels must use the same data format. However, the input and output formats can be different. 2.5 M851Warp Microprocessor The M851Warp (851) microprocessor controls I 2 C reads and writes and participates in some audio processing tasks requiring multiframe (f S period) processing cycles. The 851 processor performs some control calculations and exchanges data between the audio DSP core and the I 2 C interface. It also provides mode control for the SAP interface and clock control. The microcode can program the GPIO pin for post-boot-up operation to be an input or an output. For more information, see the TAS318/TAS318IA Firmware Programmer's Guide (SLEU67). 2.6 I 2 C Control Interface The TAS318/TAS318IA has an I 2 C slave-only interface (SDA1 and SCL1) for receiving commands and providing status to the system controller, and a separate master I 2 C interface (SDA2 and SCL2) to download programs and data from external memory such as an EEPROM. See Section 6 for more information. 4 Functional Description Submit Documentation Feedback

5 TAS318, TAS318IA 2.7 Audio DSP Core The audio DSP core arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit and data and coefficient memory blocks. The primary features of the audio DSP core are: 48-bit data path with 76-bit accumulator Hardware multiplier (28 bit 48bit) Read/write single-cycle memory access Input is 48-bit 2s-complement data multiplexed in from the SAP immediately following an LRCLK pulse. Output is 32-bit 2s-complement data on four buses. Separate control for writing to delay memory Separate coefficient memory (28 bit) and data memory (48 bit) Linear feedback shift register (LFSR) is a random-number generator that can be used to dither the audio. Coefficient RAM, data RAM, LFSR seed, program counter, and memory pointers are all mapped into the same 5.88K memory space for convenient addressing by the microprocessor. Memory interface block contains four pointers two for data memory and two for coefficient memory. The audio DSP core is used to implement all audio processing functions. Submit Documentation Feedback Functional Description 5

6 TAS318, TAS318IA 3 Physical Characteristics 3.1 Terminal Assignments DCP PACKAGE (TOP VIEW) AVSS VR_PLL XTALI XTALO MCLKI MICROCLK_DIV CS GPIO DVDD DVSS SDIN1 SDIN2 SDIN3 SDIN4 SDA1 SCL1 SDA2 SCL2 LRCLK AVDD RESERVED PLL2 PLL1 PLL RESERVED RESET PDN DVDD DVSS VR_DIG SDOUT1 SDOUT2 SDOUT3 SDOUT4 SCLKOUT2 SCLKOUT1 MCLKO SCLKIN P Physical Characteristics Submit Documentation Feedback

7 TAS318, TAS318IA 3.2 Terminal Descriptions TERMINAL NAME NO. 3.3 Reset (RESET) INPUT/ OUTPUT (1) PULLUP/ PULLDOWN (2) AVDD 38 I Analog power supply (3.3 V) AVSS 1 Analog ground CS 7 I Pulldown Chip select DVDD 9, 3 I Digital power supply input (3.3 V) DVSS 1, 29 Digital ground GPIO 8 I/O Pullup GPIO control (user programmable) LRCLK 19 I/O Pulldown Sample rate clock (f S ) DESCRIPTION MCLKIN 5 I Master clock input (connect to ground when not in use) MCLKO 21 O Master clock output MICROCLK_DIV 6 I Pulldown Internal microprocessor clock divide control PDN 31 I Pullup PLL 34 I Pullup PLL control PLL1 35 I Pulldown PLL control 1 PLL2 36 I Pullup PLL control 2 RESERVED 33, 37 Reserved. Connect to ground RESET 32 I Pullup Reset, active low SCL1 16 I/O I 2 C port 1 clock (always a slave) Power down. Powers down all logic and stops all clocks, active low. Coefficient memory remains stable through the power-down cycle. SCL2 18 I/O I 2 C port 2 clock (always a master) SCLKIN 2 I Pulldown Bit clock input SCLKOUT1 22 O Bit clock 1 out. Used to receive input serial data. SCLKOUT2 23 O Bit clock 2 out. Used to clock output serial data. SDA1 15 I/O I 2 C port 1 data (always a slave) SDA2 17 I/O I 2 C port 2 data (always a master) SDIN1 11 I Pulldown Serial data input 1 SDIN2 12 I Pulldown Serial data input 2 SDIN3 13 I Pulldown Serial data input 3 SDIN4 14 I Pulldown Serial data input 4 SDOUT1 27 O Serial data output 1 SDOUT2 26 O Serial data output 2 SDOUT3 25 O Serial data output 3 SDOUT4 24 O Serial data output 4 VR_PLL 2 Internal regulator. This pin must not be used to power external devices. XTALI 3 O Oscillator input (connect to ground when not in use) XTALO 4 O Oscillator output VR_DIG 28 Internal regulator. This pin must not be used to power external devices. (1) I = input, O = output (2) All pullups are 2-µA weak pullups, and all pulldowns are 2-µA weak pulldowns. The pullups and pulldowns are included to ensure proper input logic levels if the terminals are left unconnected (pullups logic 1 input; pulldowns logic input). Devices that drive inputs with pullups must be able to sink 2 µa while maintaining a logic- drive level. Devices that drive inputs with pulldowns must be able to source 2 µa while maintaining a logic-1 drive level. The RESET pin is an asynchronous control signal that restores all TAS318/TAS318IA components to the default configuration. When a reset occurs, the audio DSP core is put into an idle state and the 851 starts initialization. A valid MCLKI or XTLI must be present when clearing the RESET pin to initiate a device reset. A reset can be initiated by applying a logic on RESET. A reset can also be issued at power turnon by the three internal power supplies. Submit Documentation Feedback Physical Characteristics 7

8 TAS318, TAS318IA As long as RESET is held LOW, the device is in the reset state. During reset, all I 2 C and serial data bus operations are ignored. The I 2 C interface SCL and SDA lines go into a high-impedance state and remain in that state until device initialization has completed. The rising edge of the reset pulse begins the initialization housekeeping functions of clearing memory and setting the default register values. Once these are complete, the TAS318/TAS318IA enables its master I 2 C interface and disables its slave I 2 C interface. Then the TAS318/TAS318IA looks for an EEPROM as described in Section 2.6, I 2 C Control Interface. 3.4 Power-On Reset (RESET) On power up, it is recommended that the TAS318/TAS318IA RESET be held LOW until DVDD has reached 3.3 V. This can be done by programming the system controller or by using an external RC delay circuit. The 1-kΩ and 1-µF values provide a delay of approximately 2 µs. The values of R and C can be adjusted to provide other delay values as necessary. 3.5 Power Down (PDN) PDN is a user-firmware-definable pin that is programmed in the default TAS318 and TAS318IA configuration to stop all clocks in the TAS318/TAS318IA, while preserving the state of the device. For more information, see TAS318/TAS318IA Firmware Programmer's Guide (SLEU67). 3.6 I 2 C Bus Control (CS) The TAS318/TAS318IA has a control to specify the slave and master I 2 C address. This control permits up to two TAS318/TAS318IA devices to be placed in a system without external logic. See Section 6.2 for a complete description of this pin. 3.7 Programmable General Purpose I/O (GPIO) The TAS318/TAS318IA has one GPIO pin that is 851 firmware programmable. On power up or following a reset, the GPIO pin becomes an input. Afterwards, the microprocessor can program the GPIO as an input or an output. For more information, see TAS318/TAS318IA Firmware Programmer's Guide (SLEU67) No EEPROM is Present or a Memory Error Occurs Following reset or power-up initialization with the EEPROM not present or if a memory error occurs, the TAS318/TAS318IA is in one of two modes, depending on the setting of the GPIO pin. GPIO pin is logic HIGH (through a 2-kΩ resistor) With the GPIO pin held HIGH during initialization, the TAS318/TAS318IA comes up in the default configuration with the serial data outputs not active. Once the TAS318/TAS318IA has completed the default initialization procedure and after the status register is updated and the I 2 C slave interface is enabled, the GPIO pin is an output and is driven LOW. Following the HIGH-to-LOW transition of the GPIO pin, the system controller can access the TAS318/TAS318IA through the I 2 C interface and read the status register to determine the load status. If a memory-read error occurs, the TAS318/TAS318IA reports the error in the status register (I 2 C subaddress x2). GPIO pin is logic LOW (through a 2-kΩ resistor) With GPIO pin held LOW during initialization, the TAS318/TAS318IA comes up in an I/O test configuration. In this case, once the TAS318/TAS318IA completes its default test initialization procedure, the status register is updated, the I 2 C slave interface is enabled, and the TAS318/TAS318IA streams audio unaltered from input to output as SDIN1 to SDOUT1, SDIN2 to SDOUT2, etc. In this configuration, the GPIO pin is an output signal that is driven LOW. If the external logic is no 8 Physical Characteristics Submit Documentation Feedback

9 TAS318, TAS318IA longer driving the GPIO pin low after the load has completed (~1 ms following a reset if no EEPROM is present), the state of the GPIO pin can be observed. Then the system controller can access the TAS318/TAS318IA through the I 2 C interface and read the status register to determine the load status. If the GPIO pin state is not observed, the only indication that the device has completed its initialization procedure is that the TAS318/TAS318IA streams audio and the I 2 C slave interface has been enabled GPIO Pin Function After Device Is Programmed Once the TAS318/TAS318IA has been programmed, either through a successful boot load or via slave I 2 C download, the operation of GPIO can be programmed to be an input and/or output. 3.8 Input and Output Serial Audio Ports The TAS318/TAS318IA supports system architectures that require data format conversions between TDM and non-tdm of the same format type without the need for additional glue logic. In addition, the TAS318/TAS318IA supports data format conversions between right justified and I 2 S and between left justified and I 2 S. All the supported conversions are listed in Table 3-1. If the input port is configured for a TDM format, only SDIN1 is active. If a TDM format is selected for the output port, only SDOUT1 is active. INPUT SAP (SDIN1, SDIN2, SDIN3, SDIN4) Table 3-1. Supported Conversions OUTPUT SAP (SDOUT1, SDOUT2, SDOUT3, SDOUT4) 2 channel left justified TDM left justified 2 channel left justified 2 channel I 2 S TDM left justified 2 channel left justified 2 channel I 2 S TDM I 2 S TDM I 2 S 2 channel I 2 S 2 channel I 2 S 2 channel leftjustified 2 channel I 2 S 2 channel right justified 2 channel right justified 2 channel I 2 S Submit Documentation Feedback Physical Characteristics 9

10 TAS318, TAS318IA Table 3-2. Serial Data Input and Output Formats INPUT OUTPUT MODE CONTROL CONTROL SERIAL FORMAT IM[3:] OM[3:] Left justified 16, 2, 24, 32 WORD DATA RATES MAX LENGTHS (khz) SCLK 2 channel 1 1 Right justified 16, 2, 24, I 2 S 16, 2, channel left justified 16, 2, 24, MCLK MCLK channel I 2 S 16, 2, crystal crystal Time-division multiplexed (4, channel left justified 16, 2, 24, , or channel I 2 S 16, 2, 24 channel) channel left justified 16, 2, 24, MCLK MCLK channel I 2 S 16, 2, crystal crystal Input Port Word Size Output Port Word Size x 15 Î XX IW[2:] OW[2:] DWFMT (Data Word Format) S Slave Addr Ack Subaddr Ack xxxxxxxx Ack xxxxxxxx Ack DWFMT Ack IOM Ack IM[3:] OM[3:] Input Port Format Output Port Format R3-1 Figure 3-1. Serial Data Controls Table 3-3. Serial Data Input and Output Data Word Sizes IW1, OW1 IW, OW FORMAT 32-bit data 1 16-bit data 1 2-bit data bit data 1 Physical Characteristics Submit Documentation Feedback

11 TAS318, TAS318IA Following a reset, ensure that the clock register (x) is written before performing volume, treble, or bass updates. Commands to reconfigure the SAP can be accompanied by mute and unmute commands for quiet operation. However, care must be taken to ensure that the mute command has completed before the SAP is commanded to reconfigure. Similarly, the TAS318/TAS318IA should not be commanded to unmute until after the SAP has completed a reconfiguration. The reason for this is that an SAP configuration change while a volume or bass or treble update is taking place can cause the update not to be completed properly. When the TAS318/TAS318IA is transmitting serial data, it uses the negative edge of SCLK to output a new data bit. The TAS318/TAS318IA samples incoming serial data on the rising edge of SCLK. The TAS318/TAS318IA only supports TDM, left justified, right justified, and I 2 S formats channel I 2 S Timing In 2 channel I 2 S timing, LRCLK is LOW when left channel data is transmitted and HIGH when right channel data is transmitted. SCLK is a bit clock running at 64 f S, which clocks in each bit of the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS318/TAS318IA masks unused trailing data-bit positions. 2-Channel I 2 S (Philips Format) Stereo Input/Output 32 Clks 32 Clks LRCLK (Note Reversed Phase) Left Channel Right Channel SCLK SCLK MSB LSB MSB LSB 24-Bit Mode Bit Mode Bit Mode T34-4 Figure 3-2. I 2 S 64-f S Format Submit Documentation Feedback Physical Characteristics 11

12 TAS318, TAS318IA Channel Left Justified Timing In 2 channel left justified timing, LRCLK is HIGH when left channel data is transmitted and LOW when right channel data is transmitted. SCLK is a bit clock running at 64 f S which clocks in each bit of the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS318/TAS318IA masks unused trailing data-bit positions. 2-Channel Left-Justified Stereo Input LRCLK 32 Clks Left Channel 32 Clks Right Channel SCLK SCLK MSB LSB MSB LSB 24-Bit Mode Bit Mode Bit Mode T34-2 Figure 3-3. Left justified 64-f S Format 12 Physical Characteristics Submit Documentation Feedback

13 TAS318, TAS318IA Channel Right Justified Timing In 2-channel right-justified timing, LRCLK is HIGH when left channel data is transmitted and LOW when right channel data is transmitted. SCLK is a bit clock running at 64 f S, which clocks in each bit of the data. The first bit of data appears on the data lines 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In the right-justified mode, the last bit clock before LRCLK transitions always clocks the LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS318/TAS318IA masks unused leading data-bit positions. 2-Channel Right-Justified (Sony Format) Stereo Input LRCLK 32 Clks Left Channel 32 Clks Right Channel SCLK SCLK MSB LSB MSB LSB 24-Bit Mode Bit Mode Bit Mode T34-3 Figure 3-4. Right justified 64-f S Format TDM Modes The TDM modes on the TAS318/TAS318IA provide left justified and I 2 S formats. Each word in the TDM data stream adheres to the bit placement shown in Figure 3-5 and Figure 3-6. Two cases are illustrated an I 2 S data format and a left-justified data format. Submit Documentation Feedback Physical Characteristics 13

14 TAS318, TAS318IA 128 Clks 128 Clks LRCLK Left Channels Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC5) 32-Bit Word (DAC7) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 32-Bit Word (DAC6) 32-Bit Word (DAC8) 96 Clks 96 Clks LRCLK Left Channels Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC5) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 32-Bit Word (DAC6) 64 Clks 64 Clks LRCLK LRCLK Left Channels Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 1-Chip, 8-, 6-, 4-Channel and Multiplexed 6-Channel Operation SCLK Left-Justified Format MSB LSB LRCLK 32-Bit Mode SCLK 24-Bit Mode Bit Bit Mode Bit (Example) Bit Mode T85-1 Figure 3-5. Left-Justified TDM Formats 14 Physical Characteristics Submit Documentation Feedback

15 TAS318, TAS318IA 128 Clks 128 Clks LRCLK Left Channels Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC5) 32-Bit Word (DAC7) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 32-Bit Word (DAC6) 32-Bit Word (DAC8) 96 Clks 96 Clks LRCLK Left Channels Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC5) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 32-Bit Word (DAC6) 64 Clks 64 Clks LRCLK LRCLK Left Channels Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 1-Chip, 8-, 6-, 4-Channel and Multiplexed 6-Channel Operation SCLK I2S Format MSB LSB LRCLK 24-Bit Mode SCLK 2-Bit Mode Bit (Example) Bit Mode T85-2 Figure 3-6. I 2 S TDM Formats Submit Documentation Feedback Physical Characteristics 15

16 TAS318, TAS318IA SAP Input to SAP Output Processing Flow All SAP data format options other than I 2 S result in a two-sample delay from input to output, as shown in Figure 3-7. If I 2 S formatting is used for both the input SAP and the output SAP, the polarity of LRCLK in Figure 3-7 must be inverted. However, if I 2 S format conversions are performed between input and output, the delay becomes either 1.5 samples or 2.5 samples, depending on the processing clock frequency selected for the audio DSP core relative to the sample rate of the incoming data. The I 2 S format uses the falling edge of LRCLK to begin a sample period, whereas all other formats use the rising edge of LRCLK to begin a sample period. This means that the input SAP and audio DSP core operate on sample windows that are 18 out of phase, with respect to the sample window used by the output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint of the sample period used by the audio DSP core to process the data. If the processing cycle completes all processing tasks before the midpoint of the processing sample period, the output SAP outputs this processed data. However, if the processing time extends past the midpoint of the processing sample period, the output SAP outputs the data processed during the previous processing sample period. In the former case, the delay from input to output is 1.5 samples. In the latter case, the delay from input to output is 2.5 samples. Therefore, delay from input to output can be either 1.5 or 2.5 sample times when data format conversions are performed that involve the I 2 S format. However, which delay time is obtained for a particular application is determinable and fixed for that application, providing care is taken in the selection of MCLKI/XTALI with respect to the incoming sample clock, LRCLK. 16 Physical Characteristics Submit Documentation Feedback

17 TAS318, TAS318IA 1 st Half Sample Time N Sample Time N Sample Time N + 1 Sample Time N + 2 Serial Rx Regs Input Holding Regs Input Holding Regs SDOUT1 SDIN1 SDIN1 A U Channel 1 B V SDOUT2 SDIN2 C D Input Mux Channel 2 Output Mux W X SDOUT3 SDIN2 SDIN3 SDIN3 E Y Channel 3 F Z SDIN4 G SDIN4 H Sample Time N + 1 Sample Time N Sample Time N + 1 Sample Time N + 2 Serial Rx Regs Input Holding Regs Input Holding Regs SDOUT1 SDIN1 A U SDIN1 Channel 1 B V SDOUT2 SDIN2 C D Input Mux Channel 2 Output Mux W X SDOUT3 SDIN2 SDIN3 E Y SDIN3 Channel 3 F Z SDIN4 SDIN4 G H Serial Rx Regs Serial Rx Regs 2 nd Half Sample Time N Sample Time N Sample Time N + 1 Sample Time N + 2 Input Holding Regs Input Holding Regs A U Channel 1 B V C D Input Mux Channel 2 Output Mux W X E Y Channel 3 F Z G H Sample Time N + 2 Sample Time N Sample Time N + 1 Sample Time N + 2 Input Holding Regs Input Holding Regs A U Channel 1 B V C D Input Mux Channel 2 Output Mux W X E Y Channel 3 F Z G H SDOUT1 SDOUT2 SDOUT3 SDOUT1 SDOUT2 SDOUT3 B76-1 Figure 3-7. SAP Input-to-Output Latency Submit Documentation Feedback Physical Characteristics 17

18 TAS318, TAS318IA 4 Algorithm and Software Development Tools for TAS318/TAS318IA The TAS318/TAS318IA algorithm and software development tool set is a combination of classical development tools and graphical development tools. The tool set is used to build, debug, and execute programs in both the audio DSP and 851 sections of the TAS318/TAS318IA. Classical development tooling includes text editors, compilers, assemblers, simulators, and source-level debuggers. The 851 can be programmed exclusively in ANSI C. The 851 tool set is an off-the-shelf tool set, with modifications as specified in this document. The 851 tool set is a complete environment with an IDE, editor, compiler, debugger, and simulator. The audio DSP core is programmed exclusively in assembly. The audio DSP tool set is a complete environment with an IDE, context-sensitive editor, assembler, and simulator/debugger. Graphical development tooling provides a means of programming the audio DSP core and 851 through a graphical drag-and-drop interface using modular audio software components from a component library. The graphical tooling produces audio DSP assembly and 851 ANSI C code, as well as coefficients and data. The classical tools can also be used to produce the executable code. In addition to building applications, the tool set supports the debug and execution of audio DSP and 851 code on both simulators and EVM hardware. 18 Algorithm and Software Development Tools for TAS318/TAS318IA Submit Documentation Feedback

19 TAS318, TAS318IA 5 Clock Controls Clock management for the TAS318/TAS318IA consists of two control structures: Master clock management Oversees the selection of the clock frequencies for the 851 microprocessor, the I 2 C controller, and the audio DSP core The master clock (MCLKI or XTALI) is the source for these clocks. In most applications, the master clock drives an on-chip digital phase-locked loop (DPLL), and the DPLL output drives the microprocessor and audio DSP clocks. Also available is the DPLL bypass mode, in which the high-speed master clock directly drives the microprocessor and audio DSP clocks. Serial audio port (SAP) clock management Oversees SAP master/slave mode Controls output of SCLKOUT1, SCLKOUT2, and LRCLK in the SAP master mode Figure 5-2 shows the clock circuitry in the TAS318/TAS318IA. Input pin MCLKI or XTALI provides the master clock for the TAS318/TAS318IA. Within the TAS318/TAS318IA, these two inputs are combined by an OR gate and, thus, only one of these two sources can be active at any one time. The source that is not active must be logic. In normal operation, 1, 2, or 4 (as determined by the logic levels set at input pins PLL and PLL1) divides the master clock. The DPLL then multiplies this signal by 11 in frequency (PLL2 = LOW). The multiplier ratio is always 11 (pin PLL2 = LOW). The DPLL output is the processing clock used by the audio DSP core. Submit Documentation Feedback Clock Controls 19

20 TAS318, TAS318IA Table 5-1. PLL2, PLL1, and PLL Pin Configuration Controls PLL2 PLL1 PLL AUDIO DSP CLOCK 11 MCLK/ MCLK/ MCLK/4 1 1 Reserved 1 X X Reserved Audio DSP clock or audio DSP clock/4 is used to clock the on-chip microprocessor. The input pin MICROCLK_DIV makes this clock choice. A logic-1 input level on this pin selects the audio DSP clock for the microprocessor clock; a logic- input level on this pin selects the audio DSP clock/4 for the microprocessor clock. The microprocessor clock must be 34 MHz. Table 5-2. MICROCLK_DIV Pin Configuration Control MICROCLK_DIV MICROPROCESSOR CLOCK Audio DSP clock/4 1 Audio DSP clock NOTE The state of PLL, PLL1, PLL2, and MICROCLK_DIV can only be changed while the TAS318 or TAS318IA RESET pin is held low. The TAS318/TAS318IA only supports dynamic sample-rate changes between any of the supported sample frequencies when a fixed-frequency master clock is provided. During dynamic sample-rate changes, the TAS318/TAS318IA remains in normal operation and the register contents are preserved. To avoid producing audio artifacts during the sample-rate changes, a volume or mute control can be included in the application firmware that mutes the output signal during the sample-rate change. The fixed-frequency clock can be provided by a crystal, attached to XTLI and XTLO, or an external 3.3-V fixed-frequency TTL source attached to MCLKI. When the TAS318/TAS318IA is used in a system in which the master clock frequency (f MCLK ) can change, the TAS318/TAS318IA must be reset during the frequency change. In these cases, the procedure shown in Figure 5-1 should be used. 2 Clock Controls Submit Documentation Feedback

21 TAS318, TAS318IA Enable Mute and Wait for Completion RESET Pin = Low Change f MCLK No Are Clocks Stable? Yes RESET Pin = High After TAS318/TAS318IA Initializes, Re-initialize I 2 C Registers F7-1 Figure 5-1. Master Clock Frequency (f MCLK ) Change Procedure Submit Documentation Feedback Clock Controls 21

22 TAS318, TAS318IA SCLKIN MCLKI XTALI XTALO MCLKO PLL2 PLL1 PLL SCLKOUT1 LRCLK MICROCLK_DIV SCLKOUT2 2 2 M U X OSC MCLK 2 2 M U X PLL 11 M U X Z = 2 DEFAULT X = 1 DEFAULT M U X M U X 4 M U X Y = 64 DEFAULT M U X PLL and Clock Management Input SAP Audio DSP Core Output SAP I 2 C Master/Slave Controller Master SCL 1 Microprocessor and I 2 C Bus Controller Oversample Clock 1/(M+1) M = 8 (Default) N = (Default) 1/2 N 8-Bit WARP 851 Microprocessor 2xSDA 2xSCL B78-1 Figure 5-2. DPLL and Clock Management Block Diagram 22 Clock Controls Submit Documentation Feedback

23 TAS318, TAS318IA SCL SDA DIGITAL AUDIO PROCESSOR CLOCK PLL2 PLL1 PLL MCLKO MUX x 11 PLL PLL [1:] XTALI CRYSTAL XTALO OSC MCLKI AB assigns TDM time slots for those TDM outputs involving two TAS318s. For these output formats, one of the TAS318 chips must be defined as AB =. The other TAS318 chip must be defined as AB = 1. IW2/OW2 X X X X Word Size Code IW1/OW1 1 1 Word Size IW/OW bit 16-bit 2-bit 24-bit x1 2 I C MODULE MICROPROCESSOR CLOCK 2 I C SAMPLING CLOCK N = 1 2 I C MASTER SCL M = 8 1/(M+1) 2N MUX N[2:] M[3:] MUX 4 S Slave Addr MUX x Data Word Format (DWMFT) Ack Sub-Addr Ack w[1:] y[2:] Ack ICS IMS x[2:] z[2:] Ack DWMFT Ack IOM Ack AB IW[2:] OW[2:] NOTE: Input and output word sizes are independent. S Slave Addr Ack Sub-Addr Ack Ack Ack Ack xxxxxxx Ack MUX MUX IM[3:] OM[3:] Serial Audio Port (AP) Mode Code IM3/OM3 IM2/OM2 IM1/OM1 IM/OM 1 Discrete, right justified Mode Discrete, left justified Discrete, I2S TDM_LJ_8 TDM_LJ_6 TDM_LJ_4 TDM_I2S_8 TDM_I2S_6 TDM_I2S_4 Discrete, I2S Discrete, I2S MUX MUX MUX MUX Discrete, I2S Discrete, I2S Discrete, I2S Discrete, I2S SCLKOUT2 SCLKOUT1 SCLKIN Discrete, I2S Figure 5-3. Serial Data Format, Clock Management, and I 2 C M&N Assignments Submit Documentation Feedback Clock Controls 23

24 TAS318, TAS318IA When the serial audio port (SAP) is in the master mode, the SAP uses the MCLKI or XTALI master clock to drive the serial port clocks SCLKOUT1, SLCKOUT2, and LRCLK. When the SAP is in the slave mode, LRCLK is an input and SCLKOUT2 and SCLKOUT1 are derived from SCLKIN. As shown in Figure 5-2, SCLKOUT1 clocks data into the input SAP and SCLKOUT2 clocks data from the output SAP. Two distinct clocks are required to support TDM-to-discrete and discrete-to-tdm data-format conversions. Such format conversions also require that SCLKIN be the higher-valued bit-clock frequency. For TDM-in/discrete-out format conversions, SCLKIN must be equal to the input bit clock. For discrete-in/tdm-out format conversions, SCLKIN must be equal to the output bit clock. The frequency settings for SCLKOUT1, SCLKOUT2, and LRCLK in the SAP master mode, as well as the SAP master/slave mode selection, are all controlled by I 2 C commands. Table 5-3 lists the default settings at power turnon or after a received reset. Table 5-3. TAS318/TAS318IA Clock Default Settings CLOCK SCLKOUT1 SCLKOUT2 MCLKO LRCLK Audio DSP clock Microprocessor clock DEFAULT SETTING SCLKIN SCLKIN MCLKI or XTALI Input Set by pins PLL and PLL1 Set by pin MICROCLK_DIV PLL multiply ratio 11 I 2 C sampling clock N = I 2 C master SCL M = 8 The selections provided by the dedicated TAS318/TAS318IA input pins and the programmable settings provided by I 2 C subaddress commands give the TAS318/TAS318IA a variety of clocking options. However, the following clocking restrictions must be adhered to: MCLKI or XTALI 128 f S NOTE For some TDM modes, MCLKI or XTALI must be 256 f S Audio DSP clock <136 MHz Microprocessor clock/2 I 2 C SCL clock Microprocessor clock 34 MHz I 2 C oversample clock/2 I 2 C SCL clock XTALI 2 MHz MCLKI 25 MHz As long as these restrictions are met, all other clocking options are allowed. See Section 7.1 for information on programming the clock register. 24 Clock Controls Submit Documentation Feedback

25 TAS318, TAS318IA Table 5-4. TAS318/TAS318IA MCLK and LRCLK Common Values (MCLK = MHz or MCLK = MHz) Input LRCLK f S PLL f S MCLK/ MCLK/ SCLK SCLK Divider Ch SCLKIN SCLKIN X Mux 1, 2, Rate 32, Multi- f Sample LRCLK MCLK Freq SCLK 1, OUT1 Ch per OUT2 1, 2, 4 DSPCLK per Rate Freq 3, 4, 6, 8, 64, 128, plier (MHz) Max f DSPCLK /f Rate Ratio (MHz) 2, 3, 4, 6, Rate SDOUT Rate (pins S SDIN ( f S ) (MHz) 16, , 256, 11 (pin MHz (khz) ( f S ) 8, 16, 32 ( f S ) ( f S ) PLL, 384, 512 PLL2) PLL1) Slave Mode, 2 Channels In, 2 Channels Out N/A N/A N/A N/A N/A N/A N/A Slave Mode, 2 Channels In, TDM Out N/A N/A N/A N/A Slave Mode, TDM In, 2 Channels Out N/A N/A N/A N/A Slave Mode, TDM In, TDM Out N/A N/A N/A N/A Master Mode, 2 Channels In, 2 Channels Out N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Submit Documentation Feedback Clock Controls 25

26 TAS318, TAS318IA Table 5-4. TAS318/TAS318IA MCLK and LRCLK Common Values (MCLK = MHz or MCLK = MHz) (continued) Input LRCLK f S PLL f S MCLK/ MCLK/ SCLK SCLK Divider Ch SCLKIN SCLKIN X Mux 1, 2, Rate 32, Multi- f Sample LRCLK MCLK Freq SCLK 1, OUT1 Ch per OUT2 1, 2, 4 DSPCLK per Rate Freq 3, 4, 6, 8, 64, 128, plier (MHz) Max f DSPCLK /f Rate Ratio (MHz) 2, 3, 4, 6, Rate SDOUT Rate (pins S SDIN ( f S ) (MHz) 16, , 256, 11 (pin MHz (khz) ( f S ) 8, 16, 32 ( f S ) ( f S ) PLL, 384, 512 PLL2) PLL1) N/A N/A Master Mode, 2 Channels In, TDM Out N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Master Mode, TDM In, 2 Channels Out N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Master Mode, TDM In, TDM Out N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Clock Controls Submit Documentation Feedback

27 TAS318, TAS318IA 6 Microprocessor Controller The 851 microprocessor receives and distributes I 2 C write data, retrieves and outputs to the I 2 C bus controllers the required I 2 C read data, and participates in most processing tasks requiring multiframe processing cycles. The microprocessor has its own data RAM for storing intermediate values and queuing I 2 C commands, a fixed boot-program ROM, and a program RAM. The microprocessor boot program cannot be altered. The microprocessor controller has specialized hardware for master and slave interface operation, volume updates, and a programmable interval timer interrupt. For more information, see the TAS318/TAS318IA Firmware Programmer's Guide (SLEU67). The TAS318/TAS318IA has a slave-only I 2 C interface that is compatible with the inter-ic (I 2 C) bus protocol and supports both 1-kbps and 4-kbps data-transfer rates for multiple 4-byte write and read operations (maximum is 2 bytes). The slave I 2 C control interface is used to program the registers of the device and to read device status. The TAS318/TAS318IA also has a master-only I 2 C interface that is compatible with the I 2 C bus protocol and supports 375-kbps data transfer rates for multiple 4-byte write and read operations (maximum is 2 bytes). The master I 2 C interface is used to load program and data from an external I 2 C EEPROM. On power up of the TAS318/TAS318IA, the slave interface is disabled and the master interface is enabled. Following a reset, the TAS318/TAS318IA disables the slave interface and enables the master interface. Using the master interface, the TAS318/TAS318IA automatically tests to see if an I 2 C EEPROM is at address 11xxx. The value xxx can be chip select, other information, or don t cares, depending on the EEPROM selected. If a memory is present and it contains the correct header information and one or more blocks of program/memory data, the TAS318/TAS318IA loads the program, coefficient, and/or data memories from the EEPROM. If a memory is present, the download is complete when a header is read that has a zero-length data segment. At this point, the TAS318/TAS318IA disables the master I 2 C interface, enables the slave I 2 C interface, and starts normal operation. If no memory is present or if an error occurred during the EEPROM read, TAS318/TAS318IA disables the master I 2 C interface, enables the slave I 2 C interface, and loads the unprogrammed default configuration. In this default configuration, the TAS318/TAS318IA streams eight channels of audio from input to output if the GPIO pin is LOW. The master and slave interfaces do not operate simultaneously. In the slave mode, the I 2 C bus is used to: Load the program and coefficient data Microprocessor program memory Microprocessor extended memory Audio DSP core program memory Audio DSP core coefficient memory Audio DSP core data memory Update coefficient and other control values Read status flags Once the microprocessor program memory has been loaded, it cannot be updated until the TAS318/TAS318IA has been reset. The master and slave modes do not operate simultaneously. When acting as an I 2 C master, the data transfer rate is fixed at 375 khz, assuming MCLKI or XTALI = MHz, PLL = PLL1 =, and MICROCLK_DIV =. When acting as an I 2 C slave, the data transfer rate is determined by the master device on the bus. The I 2 C communication protocol for the I 2 C slave mode is shown in Figure 6-1. Submit Documentation Feedback Microprocessor Controller 27

28 TAS318, TAS318IA Start (By Master) Read or Write (By Master) Stop (By Master) Slave Address (By Master) Data Byte (By Transmitter) Data Byte (By Transmitter) S C S 1 C S R / W A C K M S B L S B A C K M S B L S B A C K S (1) Acknowledge (By TAS318/TAS318IA) Acknowledge (By Receiver) Acknowledge (By Receiver) SDA MSB MSB 1 MSB 2 LSB SCL Start Condition SDA While SCL = 1 Stop Condition SDA While SCL = 1 T87 1 Figure 6-1. I 2 C Slave-Mode Communication Protocol 6.1 General I 2 C Operations As shown in Figure 6-2, an I 2 C read transaction requires that the master device first issue a write transaction to give the TAS318/TAS318IA the subaddress to be used in the read transaction that follows. This subaddress assignment write transaction is then followed by the read transaction. For write transactions, the subaddress is supplied in the first byte of data written, and this byte is followed by the data to be written. For I 2 C write transactions, the subaddress must always be included in the data written. There cannot be a separate write transaction to supply the subaddress, as was required for read transactions. If a subaddress assignment-only write transaction is followed by a second write transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted by the TAS318/TAS318IA as another subaddress replacing the one previously written. 28 Microprocessor Controller Submit Documentation Feedback

29 TAS318, TAS318IA I 2 C Read Transaction Start (By Master) Write (By Master) TAS318/ TAS318IA Subaddress (By Master) Stop (By Master) Start (By Master) Read (By Master) Data (By TAS318/ TAS318IA) Data (By TAS318/ TAS318IA) Stop (By Master) S TAS318/ TAS318IA Address W ACK Subaddress ACK S S TAS318/ TAS318IA Address R ACK Data ACK Data ACK NAK S 7-Bit Slave Address (By Master) Acknowledge (By TAS318/ TAS318IA) Acknowledge (By TAS318/ TAS318IA) 7-Bit Slave Address (By Master) Acknowledge (By TAS318/ TAS318IA) Acknowledge (By Master) Acknowledge (By Master) No Acknowledge (By Master) I 2 C Write Transaction Start (By Master) Write (By Master) TAS318/ TAS318IA Subaddress (By Master) Data (By Master) Data (By Master) Stop (By Master) S TAS318/ TAS318IA Address W ACK Subaddress ACK Data ACK Data ACK ACK S 7-Bit Slave Address (By Master) Acknowledge (By TAS318/ TAS318IA) Acknowledge (By TAS318/ TAS318IA) Acknowledge (By TAS318/ TAS318IA) Acknowledge (By TAS318/ TAS318IA) Acknowledge (By TAS318/ TAS318IA) R6 1 Figure 6-2. I 2 C Subaddress Access Protocol 6.2 Detailed I 2 C Operation The I 2 C slave mode is the mode that is used to change configuration parameters during operation and to perform program and coefficient downloads from a master device. The latter can be used to replace the I 2 C master-mode EEPROM download. The TAS318/TAS318IA supports both random and sequential I 2 C transactions. The TAS318/TAS318IA I 2 C slave address is 111xy, where the first six bits are the TAS318/TAS318IA device address and bit x is CS, which is set by the TAS318/TAS318IA internal microprocessor at power up. Bit y is the R/W bit. The pulldown resistance of CS creates a default address when no connection is made to the pin. Table 6-1 and Table 6-2 show all the legal addresses for I 2 C slave and master modes. The TAS318/TAS318IA I 2 C block does respond to the broadcast address (h). Table 6-1. Slave Addresses BASE ADDRESS CS R/W SLAVE ADDRESS 11 1 x x x6a x6b Submit Documentation Feedback Microprocessor Controller 29

30 TAS318, TAS318IA Table 6-2. Master Addresses BASE ADDRESS CS R/W MASTER ADDRESS 11 xa 11 1 xa xa xa3 The following is an example use of the I 2 C master address to access an external EEPROM. The TAS318/TAS318IA can address up to two EEPROMs depending on the state of CS. Initially, the TAS318/TAS318IA comes up in I 2 C master mode. If it finds a memory such as the 24C512 EEPROM, it reads the headers and data as previously described. In this I 2 C master mode, the TAS318/TAS318IA addresses the EEPROMs as shown in Table 6-3 and Table 6-4. Table 6-3. EEPROM Address I 2 C TAS318/TAS318IA Master Mode = xa1/a A MSB CS R/W (EEPROM) 1 1 1/ Table 6-4. EEPROM Address I 2 C TAS318/TAS318IA Master Mode = xa3/a2 A MSB CS R/W (EEPROM) / Random I 2 C Transactions Supplying a subaddress for each subaddress transaction is referred to as random I 2 C addressing. For random I 2 C read commands, the TAS318/TAS318IA responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a given subaddress does not use all 32 bits, the unused bits are read as logic. I 2 C write commands, however, are treated in accordance with the data assignment for that address space. If a write command is received for a biquad subaddress, for example, the TAS318/TAS318IA expects to see five 32-bit words. If fewer than five data words have been received when a stop command (or another start command) is received, the data received is discarded. Sequential I 2 C Transactions The TAS318/TAS318IA also supports sequential I 2 C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I 2 C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS318/TAS318IA. For I 2 C sequential write transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted before a stop or start is transmitted determines how many subaddresses are written to. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; just the incomplete data is discarded. Sequential read transactions do not have restrictions on outputting only complete subaddress data sets. If the master does not issue enough data-received acknowledges to receive all the data for a given subaddress, the master device does not receive all the data. If the master device issues more data-received acknowledges than required to receive the data for a given subaddress, the master device simply receives complete or partial sets of data, depending on how many data-received acknowledges are issued from the subaddress(es) that follow. I 2 C read transactions, both sequential and random, can impose wait states. 3 Microprocessor Controller Submit Documentation Feedback