A hardware evaluation of π-cipher
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1 FPGA Results (by Mohamed El Haddedy) A hardware evaluation of π-cipher Table 1: FPGA results for all variants of π-cipher (Spartan-6 (xc6slx16csg324-3)) /Area Encryption Encryption Encryption Oversize of the platform 1753 NA From slices (we can get the following number of used LUT, FF, and unused (FF, LUT) unused fully used Encryption out of out of out of out of out of out of out of out of out of 4527 Encryption out of out of out of out of out of out of 7643 Encryption ,416 out of out of out of 7642 NA
2 Table 2: FPGA results of π-function on (Spartan-6 (xc6slx16csg324-3)) Area(slices) Max.Freq /Area IOB are limited compare to the design 192 IOB are limited compare to the design From Slices (we can get the following number of used LUT, FF, and unused (FF, LUT) LUT Flip-Flop unused unused LUT fully used out of out of out of out of out of out of 4787 IOB are limited compare to the design Table 3: FPGA results of ARX operation on (Spartan-6 (xc6slx16csg324-3)) Area(slices) Max.Freq /Area IOB are limited compare IOB are limited 5 to the design compare to the design From Slices (we can get the following number of used LUT, FF, and unused (FF, LUT) LUT Flip-Flop unused unused LUT fully used out of out of out of 771 IOB are limited compare to the design
3 Table 4: FPGA results for all variants of π-cipher (VC707 (XC7VX485t-2FFG1761) and ISE14.7) /Area Encryption Encryption Encryption From slices (we can get the following number of used LUT, FF, and unused (FF, LUT) unused fully used Encryption out of out of out of out of out of out of out of out of out of 4295 Encryption out of out of out of out of out of out of out of out of out of 7994 Encryption out of out of out of out of out of out of out of out of out of 15015
4 Table 5: FPGA results of π-function (VC707 (XC7VX485t-2FFG1761) and ISE14.7) /Area From slices (we can get the following number of used LUT, FF, and unused (FF, LUT) unused fully used out of out of out of out of out of out of out of out of out of 9049 Table 6: FPGA results of ARX operation (VC707 (XC7VX485t-2FFG1761) and ISE14.7) /Area From slices ( we can get the following number of used LUT, FF, and unused (FF, LUT) unused fully used Out of out of out of Out of out of out of Out of out of out of 3759 = no.bits * Max.Freq /no.cycles Picipher version: key length is 96 bits, message block length is 128 bits Picipher version: key length is 128 bits, message block length is 256 bits Picipher version: key length is 256 bits, message block length is 512 bit
5 Notes: these processors are small, they occupied around 1% of the total capacity of the FPGA. If we are targeting high speed we can repeat these processor as many as we want and the throughput will be increased by the factor of number of processors (n) = n * one processor throughput Area = n * one processor area The ratio between them is fixed. ASIC Results (by Mohamed El Haddedy and Xinfei Guo) Table 7: ASIC results for all variants of π-cipher (28/32nm technology) Encryption Encryption/ Encryption Encryption/ Encryption Encryption/ Area (um 2 ) Estimated Gate Count (K) Max. Freq. (GHz) # of cycles Power (mw) /Area (Kbps/um 2 ) Table 8: ASIC results of π-function (28/32nm technology) Area (um 2 ) Estimated Gate Count (K) Max. Frequency (GHz) # of cycles Power (mw) /Area (Kbps/um 2 )
6 Table 9: ASIC results of ARX operation (28/32nm technology) Area (um 2 ) Estimated Gate Count Max. Frequency (GHz) # of cycles Power (mw) /Area (Kbps/um 2 )
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