High Capacity and High Performance 20nm FPGAs. Steve Young, Dinesh Gaitonde August Copyright 2014 Xilinx
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1 High Capacity and High Performance 20nm FPGAs Steve Young, Dinesh Gaitonde August 2014
2 Not a Complete Product Overview Page 2
3 Outline Page 3
4 Petabytes per month Increasing Bandwidth Global IP Traffic Growth Growth of Xilinx FPGA Serial Bandwidth 6 Tb/s 5 Tb/s 4 Tb/s 3 Tb/s 2 Tb/s 1 Tb/s 1: Cisco Visual Networking Index, Forecast and Methodology, nm 90nm 65nm 40nm 28nm 20nm N Page 4
5 Higher Bandwidth IO Page 5
6 High Throughput Demands Wider, Faster Data Paths 1,000 Gb/s Page 6
7 Addressing Interconnect Bottlenecks Page 7
8 Clocking Challenge Page 8
9 Benefits of UltraScale Clock Architecture Clock Domain 1 Clock Domain 1 32 Clock Domain 2 Clock Domain 2 Clock Domain 3 Global Clock Network Leaf Cell Clocks Clocking 32 centrally located global clock buffers Root always in center of device I/O Logic GT Clock Root Distribution Clocks Routing Clocks distributed global buffers Root can be in any clock region Skew accumulates from center to edge Balanced skew per clock network Page 9
10 Routing Challenge Page 10
11 CLB Innovations Enable Tighter Packing Removed slice boundary & added MUX Wider functions per block 2x distributed RAM density Wider carry chain Wider functions per block CLB = Slice Slice 0 UltraScale 7 Series CLB carry out Flip-flops sharing same CE are same color Dedicated inputs for each flip-flop Higher performance Reduces LUT utilization UltraScale 7 Series LUT U independent direct route Slice 1 U carry in carry out Bypass CE ignore and RST ignore, RST inversion Higher performance Eliminates synchronous reset bottlenecks 2x the number of CE s Improves CLB packing RST ignore, inversion CE ignore D IN RST CE Flip-flops sharing same CE are same color carry in Page 11
12 Total Wire Length Design Use Fewer CLBs, Shorter Wire Length Re-architected for flexible connectivity and efficient logic packing Better local routability, more control set flexibility, improved P&R algorithms Tighter packing results in shorter net delays, less wire switching Translates into higher utilization, greater performance, less power Total Wirelength UltraScale & Vivado vs Previous Architecture (Normalized to 7 series) 10 Average 7 series UltraScale Fully Used CLB Partially Used CLB Individual Designs Page 12
13 Additional Metal Layers Page 13
14 Routing complexity Routability Benchmark Suite Metrics: Design Routing Complexity and Design Size Congestion Metrics displayed in Vivado No routing congestion High routing congestion Cannot route No congestion Design Size Page 14
15 Routing complexity Routing complexity UltraScale Results Vivado routes more complex designs on UltraScale UltraScale shows lower congestion on complex designs As a result, timing closure is accelerated Delivers 1 speedgrade higher Fmax No routing congestion High routing congestion Cannot route Page 15
16 2nd Generation Stacked Silicon Feature ~20,000 registered routing lines between die Clocking Architecture Spans SLR boundaries Foot-print compatibility between SSI and non-ssi devices Benefit Enables >500 MHz datapath performance between SLRs Deterministic, predictable timing Device size up to 44 million logic cells Abundant clock resources to meet demanding application Ability to seamlessly migrate from monolithic to 3D-IC devices SLR0 SLR1 SLR2 passive interposer Substrate Page 16
17 Power Optimizations Transceiver I/O up to 60% up to 50% Architectural optimizations Low power mode I/O multi-mode control (cont d from 28nm) DDR4 voltage reduction Dynamic up to 30% CLB packing & reduced wire length HW based clock gating on leaf cells Static Spartan-6/Virtex-6 (45nm/40nm) up to 50% up to 65% Transceiver I/O Dynamic Static 7 Series (28nm) up to 30% up to 40% up to 50% up to 40% 25-45% Transceiver I/O Dynamic Static UltraScale (20nm/16nm) BRAM hardened data cascading BRAM dynamic power gating DSP hardened features MMCM & PLL lower supply voltage Process node Power binning & lower voltage scaling 3D IC static power binned slices Page 17
18 Kintex UltraScale FPGAs Logic Resources Memory Resources Clock Resources I/O Resources Integrated IP Resources Speed Grades Footprint Compatible with Virtex UltraScale Page 18 Part Number XCKU035 XCKU040 XCKU060 XCKU075 XCKU100 XCKU115 Logic Cells 355, , , , ,440 1,160,880 CLB Flip-Flops 406, , , ,000 1,095,360 1,326,720 CLB LUTs 203, , , , , ,360 Maximum Distributed RAM (Kb) 5,908 7,050 9,180 7,290 12,825 18,360 Block RAM/FIFO w/ecc (36 Kb each) ,080 1,188 1,680 2,160 Block RAM/FIFO (18 Kb each) 1,080 1,200 2,160 2,376 3,360 4,320 Total Block RAM (Mb) CMT (1 MMCM, 2 PLLs) I/O DLL Maximum Single-Ended HP I/Os Maximum Differential HP I/O Pairs Maximum Single-Ended HR I/Os Maximum Differential HR I/O Pairs DSP Slices 1,700 1,920 2,760 2,592 4,200 5,520 System Monitor PCIe Gen1/2/ Interlaken G Ethernet GTH 16 Gb/s Transceivers Commercial Extended Industrial -1-1L L L L L L -2 Package Package Footprint Dimensions (mm) HR I/O, HP I/O, GTH 16 Gb/s A676 27x27 104, 208, , 208, 16 A900 31x31 104, 364, , 364, 16 A x35 104, 416, , 416, , 416, , 416, 28 A x40 104, 520, , 520, , 520, , 520, 48 B x40 104, 260, , 260, 64 A , 624, x425 A , 624, , 624, 52 D x45 156, 676, , 676, 52 F x45 104, 624, , 624, 64
19 Virtex UltraScale FPGAs Memory Resources Clock Resources I/O Resources Integrated IP Resources Speed Grades Footprint Compatible with Kintex UltraScale Devices Page 19 Part Number XCVU065 XCVU080 XCVU095 XCVU125 XCVU160 XCVU190 XCVU440 Logic Cells 626, , ,800 1,253,280 1,621,200 1,879,920 4,407,480 CLB Flip-Flops 716, ,424 1,075,200 1,432,320 1,852,800 2,148,480 5,037,120 CLB LUTs 358, , , , ,400 1,074,240 2,518,560 Maximum Distributed RAM (Kb) 4,230 3,980 4,800 8,460 10,710 12,690 28,710 Block RAM/FIFO w/ecc (36 Kb each) 1,260 1,421 1,728 2,520 3,276 3,780 2,520 Block RAM/FIFO (18 Kb each) 2,520 2,842 3,456 5,040 6,552 7,560 5,040 Total Block RAM (Mb) CMT (1 MMCM, 2 PLLs) I/O DLL Fractional PLL Maximum Single-Ended HP I/Os ,404 Maximum Differential HP I/O Pairs Maximum Single-Ended HR I/Os Maximum Differential HR I/O Pairs DSP Slices ,200 1,560 1,800 2,880 System Monitor PCIe Gen1/2/ Interlaken G Ethernet GTH 16 Gb/s Transceivers GTY 33 Gb/s Transceivers Commercial Extended Industrial -1-1L L L L L L L -2 Package Package Footprint (1) Dimensions (mm) HR I/O, HP I/O, GTH 16 Gb/s, GTY 33 Gb/s C x40 52, 468, 20, 20 52, 468, 24, 24 52, 468, 24, 24 B x40 52, 312, 32, 32 52, 312, 32, 32 52, 312, 40, 32 A x425 52, 676, 32, 16 52, 676, 32, 16 52, 676, 36, 16 D x45 52, 780, 28, 24 52, 780, 28, 24 52, 780, 28, 24 E x45 52, 624, 32, 32 52, 624, 32, 32 52, 624, 36, x475 (2) 52, 624, 36, 36 52, 624, 36, 36 J x45 52, 312, 32, 32 52, 312, 40, x475 (2) 52, 312, 52, 52 52, 312, 52, 52 A x50 104, 936, 28, 24 52, 988, 28, 24 52, 988, 28, 24 B x50 52, 1248, 36, 0 C x50 0, 520, 60, 60 A x55 52, 1404, 48, 0
20 Key Takeaways Increased IO bandwidth Up to 120 transceivers Up to 33 Gb/s per channel Routing architecture and Vivado designed to reduce congestion and improve performance Clocking architecture for flexibility and performance 2 nd generation SSI delivers "more than Moore" Up to 44 million logic cells in largest device Breakthrough architecture to address the most complex designs
21 Thank You! Page 21
Copyright 2017 Xilinx.
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