ECE 485/585 Microprocessor System Design

Transcription

1 Microprocessor System Design Lecture 6: DDR, DDR2 and DDR-3 SDRAM Memory Modules Zeshan Chishti Electrical and Computer Engineering Dept. Maseeh College of Engineering and Computer Science Source: Lecture based on materials provided by Mark F.

2 DDR (Double Data Rate) SDRAM Innovation Transfer data on rising and falling edges of clock Same internal SDRAM core but 2n-prefetch Benefit 2x the bandwidth, same control & signals as SDRAM Significant Differences: Source synchronous (DQS) Burst length of 2,4,8 only CL = 2, 2.5, 3

3 DDR (Double Data Rate) SDRAM (cont d) 2n prefetch Use same DRAM core (cell array) Fetch twice as many bits Same latency for first data transfer Source synchronous Data transfer is twice clock rate Data strobe sent alongside data Read: supplied by DRAM Data aligned with strobe edge Write: supplied by controller Data centered on strobe edge [from Elpida]

4 DDR SDRAM Access Examples Reads from same open page/bank Micron DDR Datasheet [From: Samsung]

5 Banks Incorporated Into SDRAM Memory address Row Bank Column Why row/bank/column, not bank/row/column? Consider spatial locality Imagine accessing a series of sequential memory addresses After exhausting a column, references to another bank Consider if row/bank reversed Bank would rarely be used, lose benefit of interleaving

6 DDR SDRAM Access Examples Reads from different banks, open row Row Memory address Bank Column [From: Samsung]

7 DDR SDRAM Access Examples Reads from different row Memory address Bank Row Column From: Samsung

8 DDR-2 SDRAM During the dominant high volume (PC) memory technology Innovation 4n-prefetch, faster clocks Benefit Increased bandwidth, same control/signals as DDR SDRAM Significant Differences SSTL-18 (1.8V) vs. SSTL-2 (2.5V) Low power (from lower supply voltage and new low power modes) ODT (On Die Termination) CL = 3,4,5 2Gb devices 4/8 banks vs. 4 banks tfaw = four-bank activation window Burst lengths of 4, 8 no 2 because of 4n-prefetch additive latency

9 Additive Latency 0 4 No additive latency, t RCD = CL = 4 Can t place ACT command in cycle 4 slot occupied by RD AP: B0,Cx So ACT is delayed by full cycle so RD AP: B2, Cx is delayed and resulting data out is delayed (from Micron ACT B<n>,R<x> = activate row <x> in bank <n> RD AP B<n>,C<x> = read column <x> from activated bank <n> (auto pre-charge)

10 Additive Latency Can issue the RD B0,Cx command early (in available slot) No additive latency, t RCD = CL = 4 but processing will still require adherence to t RCD, CL timing constraints [from Micron]

11 Additive Latency (cont d) No additive latency, t RCD = CL = 4 Can issue the RD B0,Cx command early (in available slot) but processing will still require adherence to t RCD, CL timing constraints Permits continuous data read from DRAM (from Micron)

12 DDR-3 Key Differences (from DDR-2) 8n prefetch SSTL-15 (1.5V) vs. SSTL-18 (1.8V) Reduced power consumption (~30%) MHz clocks 2x bandwidth of DDR-2 8 banks vs. 4 banks More open banks less latency Adoption rate Introduction in 2007 (insignificant quantities) Samsung 8 Gb DDR3 described at ISSCC February 2009 Remained dominant PC memory until DDR-4 was introduced recently

13 Micron DDR3 Datasheet

14 DDR3 Commands

15 DDR3 Read Cycle Single read Back-to-back reads to open page

16 Device speed (MHz) Device size (Mb) DRAM Speed and Size Trends MHz 2133MHz 1600MHz 1066MHz 800MHz 400MHz 400MHz 200MHz DDR DDR2 DDR3 DDR Gb 8Gb 4Gb 2Gb 1Gb 512Mb 256Mb 64Mb DDR DDR2 DDR3 DDR4 Higher memory bandwidth and capacity demand With help of process technology and VLSI advances Resulted in to faster and bigger DRAM devices Latest DDR4 specifications Up to 3.2Gbps and 32Gb devices 18

17 DRAM Refresh Leaky storage Periodic Refresh across DRAM rows Un-accessible when refreshing Read and write the same data back Example: 4K rows in a DRAM 100ns read cycle Decay in 64ms

18 Refresh Then: Asynchronous Interface

19 DRAM Refresh Frequency DRAM standard requires memory controllers to send periodic refresh commands to DRAM treflatency (trfc): Varies based on DRAM chip density (e.g., 350ns) trefperiod (trefi): Remains constant (7.8 usec for Current generation DRAM) Timeline 21

20 Refresh Now: N Simultaneous Rows CLK CMD PRE REF ACT Device densit y Num. Bank s Refresh N rows in each 7.8 usec (64ms 8K), perbank Perbank Rows Total Rows Rows in AR trfc (ɳs) 8Gb K 2M ADDR Bank/All ROW 16Gb K 4M DATA trp trfc 32Gb K 8M Command is called Auto-Refresh (AR) Retention Time = 64ms N increases with density (N: 16 8Gb, 32 16Gb) 22

21 Impact of Refresh on Performance DRAM is unavailable to serve requests for of time treflatency trefperiod 4.5% for today s 4Gb DRAM Unavailability increases with higher density due to higher treflatency 23