INSTITUTO SUPERIOR TÉCNICO. Architectures for Embedded Computing

Transcription

1 UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO Departamento de Engenharia Informática for Embedded Computing MEIC-A, MEIC-T, MERC Lecture Slides Version English Lecture 03 Title: Processor Summary: ; ; Assembly Instructions; ;. 2010/2011 Nuno.Roma@ist.utl.pt

2 for Embedded Computing Processor Prof. Nuno Roma ACE 2010/11 - DEI-IST 1 / 29 Previous Class In the previous class... Analysis Levels Definitions Comparative Metrics Benchmarks Quantitative Design Principles Prof. Nuno Roma ACE 2010/11 - DEI-IST 2 / 29

3 Road Map Prof. Nuno Roma ACE 2010/11 - DEI-IST 3 / 29 Summary Today: Processor : Assembly Instructions Bibliography: Computer Architecture: a Quantitative Approach, Appendix B Prof. Nuno Roma ACE 2010/11 - DEI-IST 4 / 29

4 Prof. Nuno Roma ACE 2010/11 - DEI-IST 5 / 29 Instruction Set Architecture (ISA): Concept introduced by IBM in the late 1960 s (IBM 370 architecture); Architecture that is seen from the code generators point of view; Interface between the processor architecture and its hardware implementation. Prof. Nuno Roma ACE 2010/11 - DEI-IST 6 / 29

5 Programming High-Level Languages Low-Level Languages Compiler Assembler Executable Code (Machine Language ) Hardware Implementation Prof. Nuno Roma ACE 2010/11 - DEI-IST 7 / 29 Entities Instructions: Operations Addressing modes Registers Memory Prof. Nuno Roma ACE 2010/11 - DEI-IST 8 / 29

6 Entities Instructions: Operations Addressing modes Registers Memory Since the mid-1980 s, other processing structures that were previously considered just implementation details started to assume a greater relevance (e.g.: execution pipeline). Prof. Nuno Roma ACE 2010/11 - DEI-IST 8 / 29 CISC vs RISC CISC: Complex Instruction-Set Computer versus RISC: Reduced Instruction-Set Computer Differentiating Factors: Number of instructions; Complexity of the operations that are implemented by a single instruction; Number of operands Addressing modes; Memory access. Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 29

7 RISC Success Most current processors are RISC! Only the DSPs keep some CISC characteristics: Worst case is more important than the average performance; Computation kernels well identified and optimized (but rarely used by the compilers i.e., many manual encoding by the programmers...) Prof. Nuno Roma ACE 2010/11 - DEI-IST 10 / 29 Project of an Instruction Set The project of an Instruction Set is a complex task which has to consider a wide set of important factors: Complexity of the control unit implementation; Suitability to the available code generators; Memory usage; Performance. Prof. Nuno Roma ACE 2010/11 - DEI-IST 11 / 29

8 Prof. Nuno Roma ACE 2010/11 - DEI-IST 12 / 29 Stack: and result in the top of the stack; Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 29

9 Stack: and result in the top of the stack; Accumulator: One special register is always used as one of the operands and as the result destination; Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 29 Stack: and result in the top of the stack; Accumulator: One special register is always used as one of the operands and as the result destination; Register-Memory: and result may either be an arbitrary register of the register bank or a memory position; Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 29

10 Stack: and result in the top of the stack; Accumulator: One special register is always used as one of the operands and as the result destination; Register-Memory: and result may either be an arbitrary register of the register bank or a memory position; Register-Register (Load-Store): and result must be registers of the register bank (any one). Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 29 Prof. Nuno Roma ACE 2010/11 - DEI-IST 14 / 29

11 Example: C=A+B Reg Reg Load R1,A Load R2,B Add R3,R1,R2 Store R3,C Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 29 Example: C=A+B Reg Reg Load R1,A Load R2,B Add R3,R1,R2 Store R3,C Reg Mem Load R1,A Add R3,R1,B Store R3,C Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 29

12 Example: C=A+B Reg Reg Reg Mem Accumulator Load R1,A Load R1,A Load R2,B Add R3,R1,B Add R3,R1,R2 Store R3,C Store R3,C Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 29 Example: C=A+B Reg Reg Reg Mem Accumulator Load R1,A Load R1,A Load A Load R2,B Add R3,R1,B Add B Add R3,R1,R2 Store R3,C Store C Store R3,C Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 29

13 Example: C=A+B Reg Reg Reg Mem Accumulator Stack Load R1,A Load R1,A Load A Load R2,B Add R3,R1,B Add B Add R3,R1,R2 Store R3,C Store C Store R3,C Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 29 Example: C=A+B Reg Reg Reg Mem Accumulator Stack Load R1,A Load R1,A Load A Push A Load R2,B Add R3,R1,B Add B Push B Add R3,R1,R2 Store R3,C Store C Add Store R3,C Pop C Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 29

14 Existing Processors in memory Maximum operands Type of architecture Examples 0 3 Reg-Reg Alpha, ARM, MIPS, PowerPC, SPARC, SuperH, Trimedia TM Reg-Mem IBM 360/370, Intel 80x86, Motorola 68000, TI TMS320C54x 2 2 Mem-Mem VAX 3 3 Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 29 Prof. Nuno Roma ACE 2010/11 - DEI-IST 17 / 29

15 Mode Example Interpretation Register Add R4,R3 Regs[R4] Regs[R4]+Regs[R3] Immediate Add R4,#3 Regs[R4] Regs[R4]+3 Displacement Add R4,100(R1) Regs[R4] Regs[R4]+Mem[100+Regs[R1]] Reg Indirect Add R4,(R1) Regs[R4] Regs[R4]+Mem[Regs[R1]] Indexed Add R4,(R1+R2) Regs[R4] Regs[R4]+Mem[Regs[R1]+Regs[R2]] Direct Add R4,(1001) Regs[R4] Regs[R4]+Mem[1001] Mem Indirect Add Regs[R4] Regs[R4]+Mem[Mem[Regs[R3]]] Autoincrement Add R1,(R2)+ Regs[R1] Regs[R1]+Mem[Regs[R2]] Regs[R2] Regs[R2]+d Autodecrement Add R1,-(R2) Regs[R2] Regs[R2]-d Regs[R1] Regs[R1]+Mem[Regs[R2]] Scaled Add R1,10(R2)[R3] Regs[R1] Regs[R1]+ Mem[10+Regs[R2]+Regs[R3]*d] Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 29 Frequency of the Prof. Nuno Roma ACE 2010/11 - DEI-IST 19 / 29

16 Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 29 Memory vs Registers Advantages of register operands: Faster access; Fewer bits required to specify the operands; Fewer memory accesses. Register operands: How many registers? Generic or dedicated/specialized? Number of bits to: Constant value in the immediate addressing mode? Absolute address? Offset? Prof. Nuno Roma ACE 2010/11 - DEI-IST 21 / 29

17 Memory vs Registers Advantages of register operands: Faster access; Fewer bits required to specify the operands; Fewer memory accesses. Register operands: How many registers? Generic or dedicated/specialized? Number of bits to: Constant value in the immediate addressing mode? Absolute address? Offset? Prof. Nuno Roma ACE 2010/11 - DEI-IST 21 / 29 Memory vs Registers Advantages of register operands: Faster access; Fewer bits required to specify the operands; Fewer memory accesses. Register operands: How many registers? Generic or dedicated/specialized? Number of bits to: Constant value in the immediate addressing mode? Absolute address? Offset? Prof. Nuno Roma ACE 2010/11 - DEI-IST 21 / 29

18 Number of Bits Needed for Immediate Prof. Nuno Roma ACE 2010/11 - DEI-IST 22 / 29 Number of Bits of Displacement Prof. Nuno Roma ACE 2010/11 - DEI-IST 23 / 29

19 Types of Most common types of operands: Integer: 8, 16, 32 or 64 bits With or without signal Floating point: Simple precision (32 bits) Double precision (64 bits) Characters: ASCII (8 bits) Unicode (16 bits) Prof. Nuno Roma ACE 2010/11 - DEI-IST 24 / 29 Memory Positions How many bits are stored in a given memory position? Prof. Nuno Roma ACE 2010/11 - DEI-IST 25 / 29

20 Memory Positions How many bits are stored in a given memory position? Common case: 32-bit processor with 8-bit memory positions: How many memory accesses are required to read a single word? Do all accesses read 32-bits? Prof. Nuno Roma ACE 2010/11 - DEI-IST 25 / 29 Aligned Memory Accesses Width xx0 xx1 xx2 xx3 xx4 xx5 xx6 xx7 1 byte (byte) Alin Alin Alin Alin Alin Alin Alin Alin 2 bytes (half word) Aligned Aligned Aligned Aligned 2 bytes (half word) Unaligned Unaligned Unaligned 4 bytes (word) Aligned Aligned 4 bytes (word) Unaligned Unaligned 4 bytes (word) Unaligned Unaligned 4 bytes (word) Unaligned Unaligned 8 bytes (dword) Aligned 8 bytes (dword) Unaligned 8 bytes (dword) Unaligned 8 bytes (dword) Unaligned 8 bytes (dword) Unaligned 8 bytes (dword) Unaligned 8 bytes (dword) Unaligned 8 bytes (dword) Unaligned Prof. Nuno Roma ACE 2010/11 - DEI-IST 26 / 29

21 Endianness Endianness usually refers to the individual byte order within a longer data word stored in external memory; Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 29 Endianness Endianness usually refers to the individual byte order within a longer data word stored in external memory; Once defined, such order is irrelevant within a computer system; Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 29

22 Endianness Endianness usually refers to the individual byte order within a longer data word stored in external memory; Once defined, such order is irrelevant within a computer system; However, it is frequently the source of many data transfer problems between different architectures! Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 29 Endianness Endianness usually refers to the individual byte order within a longer data word stored in external memory; Once defined, such order is irrelevant within a computer system; However, it is frequently the source of many data transfer problems between different architectures! Little Endian: least significant byte stored in the lowest memory address; Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 29

23 Endianness Endianness usually refers to the individual byte order within a longer data word stored in external memory; Once defined, such order is irrelevant within a computer system; However, it is frequently the source of many data transfer problems between different architectures! Big Endian: most significant byte stored in the lowest memory address. Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 29 Prof. Nuno Roma ACE 2010/11 - DEI-IST 28 / 29

24 Code Generation: Types of Assembly Instructions Control Instructions Compilers Role MIPS Prof. Nuno Roma ACE 2010/11 - DEI-IST 29 / 29