ARM Ltd. ! Founded in November 1990! Spun out of Acorn Computers

Transcription

1 ARM Architecture

2 ARM Ltd! Founded in November 1990! Spun out of Acorn Computers! Designs the ARM range of RISC processor cores! Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers.! ARM does not fabricate silicon itself! Also develop technologies to assist with the designin of the ARM architecture! Software tools, boards, debug hardware, application software, graphics, bus architectures, peripherals, cell libraries 3

3 ARM small or big? ARM and Intel running different businesses Intel: Number one semiconductor manufacturer ARM: Leading IP & eco-system provider Revenue Mkt cap $1B $30 B $50B $165 B

4 ARM s Activities Connected Community Development Tools Software IP Processors System Level IP: Data Engines Fabric 3D Graphics SoC memory Physical IP 5

5 ARM Business Today! Processor Shipped Last Year : ~4 Billion! Processor Shipped In Total : >24 Billion ARM Processor Applications! Processor Licenses : 500+! Semiconductor Partners : 200+! Process Technology : nm! Tele-parking Connected Community Members :

6 What is eco-system? Qualcomm announced its Snapdragon S4 class of SoC, which include an integrated modem on die. The 28nm SoC's micro-architecture is based on up to four independent ARM Cortex-A15 CPU cores, plus a 32 core GPU, a 128- bit SIMD engine, three DSPs, and hardwired codecs all running initially at

7 What is eco-system?

8 From 1mm 3 to 1km 3 1mm 3 1km 3 0.7mm 1.2mm 2mm 10 $1000 Mobile Home Embedded Consumer Mobile Computing Enterprise PC Server HPC The Architecture for the Digital World 15

9 ARM Architecture The ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. ARM also known as Advance RISC Machine

10 ARM Cortex Advanced Processors Architectural innovation, compatibility across diverse application spectrum! ARM Cortex-A family:! Applications processors for featurerich OS and 3 rd party applications! ARM Cortex-R family:! Embedded processors for real-time signal processing, control applications! ARM Cortex-M family:! Microcontroller-oriented processors for MCU, ASSP, and SoC applications Cortex-A8 Cortex-R4(F) Cortex -M3 x1-4 Cortex-M1 Cortex-A9...2GHz x1-4 Cortex-A5 Cortex-M4 SC300 Cortex-M0 12k gates... Unparalleled Applicability 20

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13 Why ARM? Simplicity is the key philosophy behind the ARM design RISC machine with small instruction set and consequently a small gate count. High Performance Low power consumption Small amount of silicon die area Open Source Development Tools

14 Data Sizes and Instruction Sets! The ARM is a 32-bit architecture.! When used in relation to the ARM:! Byte means 8 bits! Halfword means 16 bits (two bytes)! Word means 32 bits (four bytes)! Most ARM s implement two instruction sets! 32-bit ARM Instruction Set! 16-bit/32bit Thumb Instruction Set! Jazelle cores can also execute Java bytecode 21

15 Architecture Computer Organization (or Microarchitecture) Control and data paths I/D pipeline design Cache design System Design (or Platform Architecture) Memory and I/O buses Memory controllers Direct memory access Instruction Set Architecture (ISA)

16 ARM Cortex-M0

17 ARM Cortex-M0

18 Integer Core Pipeline! 3-stage pipeline core with von Neumann architecture! Pipeline operates in lockstep all the time Fetch Decode Execute! An instruction is advanced in the pipeline only when another instruction is executed 55

19 ARM Cortex-M0

20 ARM Cortex-M0 Instruction Set Register Set Address Space Branching Data processing Load/Store Exceptions Miscellaneous 32-bits Endianess 32-bits Endianess

21 Cortex-M0 Register Set! All registers are 32 bits wide! 13 general purpose registers! Registers r0 r7 (Low registers)! Registers r8 r12 (High registers)! 3 registers with special meaning/usage! Stack Pointer (SP) r13! Link Register (LR) r14! Program Counter (PC) r15! Special-purpose registers! xpsr shows a composite of the content of! APSR, IPSR, EPSR Main (Thread Mode) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr r15 (pc) xpsr Process (Handler Mode) sp 21

22 Register Usage Arguments into function Result(s) from function otherwise corruptible (Additional parameters passed on stack) Register variables Must be preserved Register r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 The compiler has a set of rules known as a Procedure Call Standard that determine how to pass parameters to a function (see AAPCS) CPSR flags may be corrupted by function call Assembler code which links with compiled code must follow the AAPCS at external interfaces The AAPCS is part of the ABI for the ARM Architecture Scratch register (corruptible) Stack Pointer Link Register Program Counter r12 r13/sp r14/lr r15/pc -r14 can be used as a temporary once value stacked 22

23 ARM Registers

24 The Thumb-2 instruction set! Variable-length instructions! ARM instructions are a fixed length of 32 bits! Thumb instructions are a fixed length of 16 bits! Thumb-2 instructions can be either 16-bit or 32-bit! Thumb-2 gives approximately 26% improvement in code density over ARM! Thumb-2 gives approximately 25% improvement in performance over Thumb 42

25 Instruction Set Introduction! ARMv6-M supports a subset of Thumb-2 technology! A subset of the full Thumb-2 instruction set is supported! The ARM instruction set is not supported! Thumb-2 technology supports mixed 16-bit/32-bit instructions! Small number of additional 32-bit instructions supported! Conditional execution is supported! Only one conditional instruction! Optimized for compilation from C! Thumb-2 instructions are not designed to be written by hand! But easy to learn due to small number of mnemonics 43

26 Binary Upwards Compatibility 44

27 Instruction Classes! Branch instructions! Data-processing instructions! Load and store instructions! Status register access instructions! Miscellaneous instructions 45

28 Instruction Format Label Mnemonic Operand1, Operand2,...; Comments Example Movs R0, #0x12; Set R0 = 0x12

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30 Use of a Suffix With suffix s MOVS R0, R1; Move R1 into R0 and update APSR (only low registers) Without suffix s MOV R0, R1; Move R1 into R0 (both high or low registers)

31 Use of a Suffix With suffix s ADDS R0, R1;R0 = R0 + R1 and update APSR (only low registers) Without suffix s ADD R0, R1; R0 = R0 + R1 (both high or low registers)

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34 Branch MOVS R0, #3 ;Loop counter starting value is 3 loop ; loop is an address label SUBS R0, #1 ;Decrement by 1 and update flag BGT loop ;branch to loop if R0 is Greater Than (GT) 1

35 if (counter > 10) then counter = 0 else counter = counter + 1 CMP R0, #10 ; compare to 10 BLE incr_counter ; if less or equal, then branch MOVS R0, #0 ; counter = 0 B counter_done ; branch to counter_done incr_counter ADDS R0, R0, #1 ; counter = counter +1 counter_done

36 Total = 0; for (i=0;i<5;i=i+1) Total = Total + i; Assume Total is R0 and i is R1; MOVS R0, #0 ; Total = 0 MOVS R1, #0 ; i = 0 loop ADDS R0, R0, R1 ; Total = Total + i ADDS R1, R1, #1 ; i = i + 1 CMP R1, #5 ; compare i to 5 BLTloop ; if less than then branch to loop