The ARM Architecture

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1 1 The ARM Architecture

2 Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines AMBA Development Tools 2

ARM Ltd Founded in November 1990 Spun out of Acorn Computers Designs the ARM range of RISC processor cores Licenses ARM core designs to semiconductor partners who fabricate and sell to their

3 ARM Ltd Founded in November 1990 Spun out of Acorn Computers Designs the ARM range of RISC processor cores Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers. ARM does not fabricate silicon itself Also develop technologies to assist with the designin of the ARM architecture Software tools, boards, debug hardware, application software, bus architectures, peripherals etc 3

4 ARM s Activities Connected Community Development Tools Software IP Processors memory System Level IP: Data Engines Fabric 3D Graphics Physical IP 4 SoC

5 ARM Connected Community

6 Nokia N95 Multimedia Computer OMAP 2420 Applications Processor ARM1136 processor-based SoC, developed using Magma Blast family and winner of 2005 INSIGHT Award for Most Innovative SoC Symbian OS v9.2 Operating System supporting ARM processor-based mobile devices, developed using ARM RealView Compilation Tools S60 3rd Edition S60 Platform supporting ARM processor-based mobile devices Mobiclip Video Codec Software video codec for ARM processor-based mobile devices ST WLAN Solution Ultra-low power b/g WLAN chip with ARM9 processor-based MAC Connect. Collaborate. Create. 6

7 Huge Range of Applications Intelligent toys Utility Meters IR Fire Detector Exercise Machines Energy Efficient Appliances Tele-parking Equipment Adopting 32-bit ARM Microcontrollers 7 Intelligent Vending

RAM 65nm UWB Radio antenna 10 kb Storage memory ~3fW/bit 12µAh Li-ion

8 World s Smallest ARM Computer? Wireless Sensor Network Battery Solar Cells Sensors, timers Cortex-M0 +16KB RAM 65nm UWB Radio antenna 10 kb Storage memory ~3fW/bit 12µAh Li-ion Battery A B C Processor, SRAM and PMU Wirelessly networked into large scale sensor arrays Cortex-M0; 65 8 University of Michigan

1.5km down 1km3 of active telescope Work

9 World s Largest ARM Computer? 4200 ARM powered Neutrino Detectors 70 bore holes 2.5km deep 60 detectors per string starting 1.5km down 1km3 of active telescope Work supported by the National Science Foundation and University of Wisconsin-Madison 9

10 From 1mm3 to 1km3 1mm3 1km3 10 $1000 Home Mobile Mobile Computing Embedded Consumer Enterprise PC Server The Architecture for the Digital World 10 HPC

11 11

12 Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines AMBA Development Tools 12

13 Architecture Versions ARMv7-Cortex x1-4 Cortex-A9 Cortex-A8 ARMv6 x1-4 ARM11 MPCore ARM1176JZ(F)-S ARM1156T2(F)-S ARM1136J(F)-S ARMv5 Cortex-R4F ARM1026EJ-S Cortex-R4 ARM968E-S ARM926EJ-S ARM966E-S ARM946E-S ARM7EJ-S SC200 ARM920T ARMv4 Cortex -M3 ARM922T ARM7TDMI(S) 13 SC100 SC300 Cortex-M1/M0 (v6-m) 13

14 Relative Performance* Freq (MHz) *Represents attainable speeds in 130, 90 or 65nm processes 14 Cortex A8 ARM1176JZ-S ARM1136J-S ARM1026EJ-S ARM926EJ-S ARM920T ARM7TDMI mw/mhz

15 Cortex family Cortex-A8 Cortex-R4 Cortex-M3 15 Architecture v7a MMU AXI VFP & NEON support Architecture v7r MPU (optional) AXI Dual Issue Architecture v7m MPU (optional) AHB Lite & APB

16 Data Sizes and Instruction Sets The ARM is a 32-bit architecture. When used in relation to the ARM: Byte means 8 bits Halfword means 16 bits (two bytes) Word means 32 bits (four bytes) Most ARM s implement two instruction sets 32-bit ARM Instruction Set 16-bit Thumb Instruction Set Jazelle cores can also execute Java bytecode 16

17 ARM and Thumb Performance Dhrystone 20MHz ARM Thumb bit 16-bit 16-bit with 32-bit stack Memory width (zero wait state) 17

18 Thumb-2 Instruction Set EEMBC Analysis - Performance EEMBC Analysis Code Size 18 Second generation of the Thumb architecture Blended 16-bit and 32-bit instruction set 25% faster than Thumb 30% smaller than ARM Increases performance but maintains code density Maximizes cache and tightly coupled memory usage

19 Processor Modes The ARM has seven basic operating modes: 19 User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised IRQ : entered when a low priority (normal) interrupt is raised Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode

20 The ARM Register Set Current Visible Registers Abort Mode Undef SVC Mode IRQ FIQ User Mode Mode Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr 20 Banked out Registers User FIQ IRQ SVC Undef Abort r8 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r9 r10 r11 r12 r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) spsr spsr spsr spsr spsr

21 Exception Handling When an exception occurs, the ARM: Copies CPSR into SPSR_<mode> Sets appropriate CPSR bits 0x1C Change to ARM state 0x18 Change to exception mode 0x14 Disable interrupts (if appropriate) 0x10 Stores the return address in LR_<mode> 0x0C 0x08 Sets PC to vector address 0x04 To return, exception handler needs to: 0x00 Restore CPSR from SPSR_<mode> Restore PC from LR_<mode> This can only be done in ARM state. 21 FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset Vector Table Vector table can be at 0xFFFF0000 on ARM720T and on ARM9/10 family devices

22 Program Status Registers N Z C V Q 24 J U f n d e f s Condition code flags N = Negative result from ALU Z = Zero result from ALU 22 n e I F T d x mode c Interrupt Disable bits. I = 1: Disables the IRQ. F = 1: Disables the FIQ. C = ALU operation Carried out V = ALU operation overflowed Sticky Overflow flag - Q flag i 8 Architecture 5TE/J only Indicates if saturation has occurred J bit Architecture 5TEJ only J = 1: Processor in Jazelle state T Bit Architecture xt only T = 0: Processor in ARM state T = 1: Processor in Thumb state Mode bits Specify the processor mode

23 Cortex-M3 Programmer s Model Main Only two processor modes Fully programmable in C Stack-based exception model Thread Mode for User tasks Handler Mode for OS tasks and exceptions Vector table contains addresses r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr r15 (pc) xpsr 23 Process sp

24 Conditional Execution and Flags ARM instructions can be made to execute conditionally by postfixing them with the appropriate condition code field. This improves code density and performance by reducing the number of forward branch instructions. CMP r3,#0 CMP r3,#0 BEQ skip ADDNE r0,r1,r2 ADD r0,r1,r2 skip By default, data processing instructions do not affect the condition code flags but the flags can be optionally set by using S. CMP does not need S. loop decrement r1 and set flags SUBS r1,r1,#1 BNE loop if Z flag clear then branch 24

25 Classes of Instructions (v4t) Load/Store Miscellaneous Data Operations Change of Flow MOV Bcc BL BLX 25 PC, Rm

26 Branch instructions Branch : Branch with Link : Cond B{<cond>} label BL{<cond>} subroutine_label L Offset Link bit 0 = Branch 1 = Branch with link Condition field The processor core shifts the offset field left by 2 positions, sign-extends it and adds it to the PC ± 32 Mbyte range How to perform longer branches? 26

27 Data processing Instructions Consist of : Arithmetic: Logical: Comparisons: Data movement: ADD AND CMP MOV ADC ORR CMN MVN SUB EOR TST SBC BIC TEQ RSB These instructions only work on registers, NOT memory. Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 Comparisons set flags only - they do not specify Rd Data movement does not specify Rn Second operand is sent to the ALU via barrel shifter. 27 RSC

28 Using a Barrel Shifter:The 2nd Operand Operand 1 Operand 2 Barrel Shifter Register, optionally with shift operation Shift value can be either be: 5 bit unsigned integer Specified in bottom byte of another register. Used for multiplication by constant Immediate value ALU Result 28 8 bit number, with a range of Rotated right through even number of positions Allows increased range of 32-bit constants to be loaded directly into registers

29 Single register data transfer Word LDR STR LDRB LDRH STRB Byte STRH Halfword LDRSB LDRSH Signed byte load Signed halfword load Memory system must support all access sizes Syntax: LDR{<cond>}{<size>} Rd, <address> STR{<cond>}{<size>} Rd, <address> e.g. LDREQB 29

30 Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines AMBA Development Tools 30

31 The ARM7TDM Core ABE A[31:0] Address Incrementer Address Register Incrementer P C PC Update Register Bank A L Decode Stage A U B B B u u u s s Instruction Decompression Multiplier B Barrel Shifter 32 Bit ALU s and Read Data Register Control Logic Write Data Register DBE 31 Instruction Decoder BIGEND MCLK nwait nrw MAS[1:0] ISYNC nirq nfiq nreset ABORT ntrans nmreq SEQ LOCK nm[4:0] nopc ncpi CPA CPB D[31:0]

32 Pipeline changes for ARM9TDMI ARM7TDMI Instruction Fetch Thumb ARM decompress FETCH ARM decode Reg Read Shift Reg Write ALU Reg Select DECODE EXECUTE ARM9TDMI 32 Instruction Fetch ARM or Thumb Inst Decode Reg Reg Decode Read FETCH DECODE Shift + ALU EXECUTE Memory Access Reg Write MEMORY WRITE

33 ARM10 vs. ARM11 Pipelines ARM10 Branch Prediction Instruction Fetch FETCH ARM or Thumb Instruction Decode ISSUE Reg Read DECODE Shift + ALU Memory Access Multiply Multiply Add EXECUTE MEMORY ARM11 Fetch 1 33 Fetch 2 Decode Issue Shift ALU Saturate MAC 1 MAC 2 MAC 3 Address Data Cache 1 Data Cache 2 Write back Reg Write WRITE

34 Full Cortex-A8 Pipeline Diagram 13-Stage Integer Pipeline NEON register file Architectural register file Stage NEON Pipeline

35 Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines AMBA Development Tools 35

36 An Example AMBA System High Performance ARM processor High Bandwidth External Memory Interface AHB UART Timer APB Bridge Keypad High-bandwidth on-chip RAM DMA Bus Master High Performance Pipelined Burst Support Multiple Bus Masters 36 APB PIO Low Power Non-pipelined Simple Interface

37 AHB Structure Arbiter Master #1 HADDR HWDATA HADDR HWDATA HRDATA Slave #1 HRDATA Address/Control Master #2 Slave #2 Write Data Read Data Slave #3 Master #3 Slave #4 Decoder 37

38 Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines AMBA Development Tools 38

ARM Debug Architecture Ethernet Debugger (+ optional trace tools) EmbeddedICE Logic Provides breakpoints and processor/system access JTAG interface (ICE) Converts debugger commands to JTAG signals

39 ARM Debug Architecture Ethernet Debugger (+ optional trace tools) EmbeddedICE Logic Provides breakpoints and processor/system access JTAG interface (ICE) Converts debugger commands to JTAG signals Embedded trace Macrocell (ETM) Compresses real-time instruction and data access trace Contains ICE features (trigger & filter logic) Trace port analyzer (TPA) Captures trace in a deep buffer 39 Trace Port JTAG port TAP controller ETM EmbeddedICE Logic ARM core

40 Keil Development Tools for ARM Includes ARM macro assembler, compilers (ARM RealView C/C++ Compiler, Keil CARM Compiler, or GNU compiler), ARM linker, Keil uvision Debugger and Keil uvision IDE Keil uvision Debugger accurately simulates on-chip peripherals (I2C, CAN, UART, SPI, Interrupts, I/O Ports, A/D and D/A converters, PWM, etc.) Evaluation Limitations 16K byte object code + 16K data limitation Some linker restrictions such as base addresses for code/constants GNU tools provided are not restricted in any way 40

41 Keil Development Tools for ARM 41

42 42

43 University Resources 43

44 Beagle Board 44

45 Targeting community development $149 > 1000 participants and growing Active & technical community Open access to hardware documentation Opportunity to tinker and learn 45 Personally affordable Wikis, blogs, promotion of community activity Freedom to innovate Addressing open source community needs Instant access to >10 million lines of code Free software

46 Fast, low power, flexible expansion OMAP3530 Processor 600MHz Cortex-A8 NEON+VFPv3 16KB/16KB L1$ 256KB L2$ 430MHz C64x+ DSP 32K/32K L1$ 48K L1D 32K L2 PowerVR SGX GPU 64K on-chip RAM POP Memory 128MB LPDDR RAM 256MB NAND flash 46 3 Peripheral I/O DVI-D video out SD/MMC+ S-Video out USB 2.0 HS OTG I2C, I2S, SPI, MMC/SD JTAG Stereo in/out Alternate power RS-232 serial USB Powered 2W maximum consumption OMAP is small % of that Many adapter options Car, wall, battery, solar,

47 And more Other Features 4 LEDs USR0 USR1 PMU_STAT PWR 2 buttons USER RESET 4 boot sources SD/MMC NAND flash USB Serial 47 On-going collaboration at BeagleBoard.org Live chat via IRC for 24/7 community support Links to software projects to download 3 Peripheral I/O DVI-D video out SD/MMC+ S-Video out USB HS OTG I2C, I2S, SPI, MMC/SD JTAG Stereo in/out Alternate power RS-232 serial

48 Project Ideas Using Beagle OS Projects OS porting to ARM/Cortex (TI OMAP), such as open source FreeBSD MythTV system Super-Beagle stack of Beagles as compute engine and task distribution NEON Optimization Projects Codec optimization in ffmpeg (pick your favorite codec) Voice and image recognition Open-source Flash player optimizations (swfdec) 48

49 Fin 49

The ARM Architecture T H E A R C H I T E C T U R E F O R TM T H E D I G I T A L W O R L D

The ARM Architecture T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D 1 Agenda Introduction to ARM Ltd Programmers Model Instruction Set System Design Development Tools 2 2 ARM Ltd Founded